SU1298685A1 - Phase-meter - Google Patents

Abstract

The invention relates to a phase metering technique. It can be used to create a high-precision fully automatic digital phase meter with a wide dynamic and frequency range. The aim of the invention is to improve measurement accuracy and reliability based on the use of micro-

Description

processor technology. The device contains in each of the two conversion channels input drivers, mixers 5 and 6, tunable goethe | one 7, filters 38 and 39, shapers 13 and 12 short pulses, triggers 14 and 15 and, in addition, matching element 16, pulse counter 17, control block 40, digital indicator 19, switch 22. To achieve the goal in device introduced frequency detector 24,. amplitude limiters 23 and 29, amplifier 25 high

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frequency, mixer 26, intermediate frequency amplifier 27, short pulse formaler 31, trigger 32, and new functional connections are formed. The goal is achieved by correcting the additive phase-frequency and phase-amplitude components without interrupting the measurement process. Automatic adjustment of the amplitudes of the mixable signals reduces the multiplicative component of the measurement error due to inter-channel communication of signals through a common local oscillator. 4 hp f-ly, 1 ill.

one

The invention relates to a phase-measuring technique and can be used to create a highly accurate fully automatic digital phase meter in a wide dynamic and frequency range.

The purpose of the invention is to increase measurement accuracy and reliability based on the use of microprocessor technology.

The drawing shows a structural diagram of the phase meter. .

The phase meter contains in each conversion channel serially connected input attenuators 1 and 2, high-frequency amplifiers 3 and 4, mixers 5 and 6, the second inputs of which are connected to tunable local oscillator 7, intermediate-frequency amplifiers 8 and 9 tuned to the reference frequency, phase shifters 10 and 11, the short pulse pulse drivers 12 and 13, the triggers 14 and 15, connected to the first and second inputs of the coincidence element 16, the output of which is connected to the series-connected pulse counters 17, microprocessor system 18, a microprocessor, an input / output interface, operational and permanent storage devices, and a digital indicator 19, interconnected generator 20 clock pulses connected to the control input of the microprocessor system and the input of the divider 21 reference frequency, three-channel

The two-way switch 22, the inputs of the first channel of which are connected to the output of splitter 21 and the output of trigger 15 of the conversion channel, the output is connected via the first amplitude limiter 23 to the input of the frequency detector 24, the inputs of the second channel are connected to the outputs of attenuators 1 and 2, the output is connected via serially connected a high-frequency amplifier 25, a mixer 26, a second KOTOporov input is connected to a tunable local oscillator 7, and an intermediate-frequency amplifier 27 with an input of an amplitude detector 28, the inputs of the third channel connected to the outputs of the flip-flops 14 and 15 of the conversion channels, the output is connected via the second amplitude limiter 29 to the input of the phase detector 30, the second input of which is connected to the output of the intermediate-frequency amplifier 27 through the series-connected short pulse shaper 31 and the trigger 32, the outputs of the detectors 24, 28 and 30 are connected to the inputs of a three-position switch 33, the output of which is connected via an analog-to-digital converter (A1SCH) 34 to the data bus of the microprocessor system 18 via an input interface, a three-channel Digital to analogue converter (PID): 33t connected to the data bus of the microprocessor system 18 via an output interface, the first channel of which is connected to the control input of the tunable local oscillator 7, the second to the control input of the attenuator 1, the third to the control the input of the phase shifter 10, while the control inputs of the pulse counter 17, the digital indicator 19, the ADC 34 and the DAC 35 are connected to the control bus of the microprocessor system 18 via an input / output interface,

Input attenuators 1 and 2 and high-frequency amplifiers 3 and 4 are included in input drivers 36 and 37. Intermediate-frequency amplifiers 8 and 9 and phase shifters 10 and 11 are included in filters 38 and 39. Microprocessor system 18, oscillator 20 clock pulses, divider 21 of the reference frequency, A1SC 34 and D / A converter 35 are included in control unit 40.

Phase meter works as follows.

The signals of the input frequency f with a phase shift q are fed through the input attenuators 1 and 2, amplifiers 3 and 4 of high frequency to mixers 5 and 6, the second inputs of which receive a signal of frequency f, local oscillator 7.

: - tunable Of mixed signals

by selective amplifiers 8 and 9 pro ZO Last selected

The intermediate frequency signals are separated by the difference frequency, f2, which are shifted in phase by the phase shifters 10 and 11 and fed to the formers 12 and 13, which form short pulses corresponding to zero crossings of the low-frequency signals of the frequency f ,, Output voltages of the trigger 14 and 15, switched by short pulses, act on the first and second inputs of the coincidence element 16, forming a time interval At, proportional to the sum of the measured phase shift.

(f

frequency f. divider 21.), In this case, the number of pulses in each packet at the output of the element 16 is proportional to

35 phase shifts in degrees, and the number of packs q over the averaging time bt (, & t2fQ kcL) is a constant number.

The reference voltage f is f

40 cut commutator 22 and amplitude limiter 23 arrives at a frequency detector 24, with which it is converted into a constant voltage proportional to the frequency r. Q) and phase shifts introduced by the voltage through the switch 33 of the phase meter to the ADC. 34, where the converter and the phase shifters 10 and 11. The third input of the coincidence element 16 is sent into a digital code. At the command of the microprocessor, A1SCh 34 through the data bus input interface enters

The pulses with a frequency f from the generator of 20 clock pulses go, controlling the operation of the microprocessor system 18 and simultaneously filling the time interval ut,. A gating pulse produced inside the microprocessor system 1B is supplied to the fourth input of the element 16, which represents a temporary gate of duration Ut it, ri defining the averaging time from i. j fO

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measured phase shift. The filling-ups of these temporary gates of the burst of clock pulses f are counted by the counter 17, in which the corresponding code is formed. At the command of the microprocessor, this code is fed into the microprocessor system 18 by the pin of the data, in the memory of which the number of bursts of pulses is stored as a constant during the averaging time. The calculated average phase shift value is transmitted by the microprocessor command to digital display 19.

In parallel with the output of the generator 20, the clock frequency f pulses excite the divider 2 of the reference frequency, the output voltage of which is fed to one of the inputs of the first channel of the two-position switch 22 (the lower channel of the switch according to the drawing). The intermediate channel voltage is fed to the other input of the switch channel from the trigger output 15 of the phase meter channel. The ratio of the;; Ne frequency ka of the divider 21 selects-: with equal 3.6-10, where, 2,3 ..., depending on the discreteness of measuring the phase shift in one period of the signals of the intermediate frequency.

Last choose

equal to the reference

(f

frequency f. divider 21.) In this case, the number of pulses in each packet at the output of element 16 is proportional to the value

phase shift in degrees, and the number of packs q over the averaging time bt (, & t2fQ kcL) is a constant number.

The voltage of the reference frequency f through the switch 22 and the amplitude limiter 23 is fed to the frequency detector 24, through which it is converted into a constant voltage proportional to the frequency r. This voltage is fed through the switch 33 to the ADC 34, where the conversion is

in a digital code. At the command of the microprocessor, the code A1 SCH 34 through the data bus input interface

to system 18, where it is memorized.

When switching switch 22, a voltage proportional to intermediate frequency f is generated at the output of frequency detector 24

which is converted by the ADC 34 to a code. The output of the ADC code enters-. c into a microprocessor and is compared with the code stored in system 18, corresponding to the frequency f,

The calculated difference of the codes, the characteristic difference of the reference and intermediate frequencies, is fed through the output interface to the inputs 11Д11 35 "The voltage generated at the output of the first channel of the DAC 35 changes, for example, using a varicap, the frequency of the heterodyne 7 fj in the direction of decreasing the difference between comparable frequencies ff, f2. and f, the execution of this subroutine by repeatedly comparing the frequency codes f and f /

-five .

allows automatically detecting the equality of the intermediate Frequency f and the reference f when the frequency of the input signals f or the heterodyne f 2 is changed.

The inputs of the second channel of the switch 22 receive the output signals of the attenuators 1 and 2. These signals are alternately amplified by the high-frequency amplifier 25, mixed with the tunable local oscillator 7 signal in the mixer 26, amplified at the frequency frequency by the intermediate-frequency amplifier 27 and higher with the amplitude detector 28. The output voltages of the detector 28 through the coke 33 are fed to the AC 34, where they are converted into codes.

In accordance with the second subroutine, which is analogous to the first one, the difference of codes generated by the microprocessor system 18, creates

output of the second channel of the CDL 35 control - 35 measurement process -. Automatic

The voltage that changes the attenuation of attenuator 1 to equalize the amplitudes of the signals at the inputs of amplifiers 3 and 4. The inputs of the third channel of the switch 22 receive the output voltages of the trigger M and 15 channels of the phase meter, which are alternately equalized by the amplitudes by the limiter 29 and affect the input phase detector, 30, the second input of which receives a signal of the intermediate frequency from the output of the amplifier. bodies 27 through the forgator 3 short pulses and trigger 32. The output voltages of the phase detector 30 are proportional to the difference in phase shifts of the conversion channels of the phase meter and the reference channel (25-27, 31 and 32). These voltages are alternately fed to the ADC 34, in which are encoded. At the output of the third channel 1 CAP 35, in accordance with the third sub-program, a control is generated

.

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Voltage 5 which changes the phase shift GG introduced by the phase rotator body 10, the phase shift introduced by this phase shifter equalizes the phase shifts introduced by the conversion channels of the phase meter (Z. Z 10 10 ,, 12

14 and 4 6, 9s 11, 13, 15). I

Switches 22 and 23 are controlled

ko1. ; microprocessor ands from control cables. In addition, in each of the three positions of the switch 33

0

five

The corresponding subroutine of adjustment of the correction elements of the circuit (7 and 1 and W), Variable attenuator 2 and phase shifter I: are used in the initial adjustment of the mode parameters in one of the 1 channels of the phase meter.

Thus, in rez. The result is the settings of the converter ;; Aspects of the phase meter with a microprocessor processor;;; the guns-1sc is supported by the RAVEX; the MSW of the reference frequency and the set clock frequency of the microprocessor 3 equalize the amplitudes of the input signals and equalize the phase shifts. the process of the continuation of hy.x measurements of the phase shift.

The posed goal was achieved by adjusting the additive phase-shift to the phase-amplitude composition-;:

equalizing the amplitudes of the mixed signals decreases multiplicatively. component of measurement error due to inter-channel communication of signals

40 through a common local oscillator, Coding, processing the results of measuring and correction of the errors of the conversion channels using a microprocessor-processing system will increase reliability

45 self adjusting phase meter.

Formula inventions

Claims (4)

I, Phase meters Ssocherdd in each 50 short circuit of two conversion channels connected to the input drivers, mixers, the second inputs of which are connected to the tunable local oscillator, the filtersj forming short 55 pulse pulsesj triggers, the outputs connected to the first and second inputs of the element coincide, the output of which Connected with a consistent:; United account 7 A pulse generator, a digital indicator control unit, and switches, characterized in that frequency, amplitude and phase detectors, amplitude limiters and additional high frequency amplifiers, mixers, and intermediate frequency amplifiers are entered into it for measuring accuracy and reliability. , the short pulse shaper and the trigger, the output of the first amplitude limiter is connected to the input of the frequency detector, the output of the high-frequency amplifier is connected via a serially connected mixer, Torah input of which is connected to the output perestrivaemogo oscillator, an intermediate frequency amplifier to the inputs of an amplitude detector and a short-pulse, posledneg output via the trigger is connected to the input of the phase detektoraj second input coupled to the second output of the amplitude limiter. 2. Phase meter according to claim 1, characterized in that the input driver consists of serially connected input attenuators, inputs connected to the inputs of conversion channels, and high-frequency amplifiers, outputs connected to the inputs of mixers. 3. Phase meter according to claim I, characterized in that the filters of the conversion channels consist of series-connected intermediate frequency amplifiers with inputs connected to the outputs of the mixers, and phase shifters, outputs connected to the inputs of the short pulse formers. 4. Phase meter according to claim 1, characterized in that the switches plug one three-channel two-position switch and the other three-way switch, with one input of the first channel of the three-channel two-position switch connected to the trigger output of the conversion channel, and the output is with the input of the first amplitude limiter, the inputs of the second channel of the switch are connected respectively VEYShPI Order 885/48 Circulation 731 Subscription Proizv.-poly. pr-tie, Uzhgorod, st. Project, 4 0 8685 eight with the inputs of attenuators of input drivers, and the output with the input of an additional high-frequency amplifier, the inputs of the third channel of the switch are connected respectively to the outputs of the trigger channels of the conversion channels, and the output with the input of the second amplitude limiter, the inputs of the three-position switch are connected respectively with the outputs of frequency, amplitude and phase detectors. 5, Phase meter according to claim 1, about tl and - h and y and with the fact that the unit upf5 20 The unit consists of a microprocessor system, a clock pulse generator, a reference frequency divider, an analog-digital converter and a digital-analog converter, and the clock input of the microprocessor system is connected to the clock pulse generator output, a reference frequency divider input, and the third input of the matching element 25, the other input terminal with the output of the counter, and the third input - with the analog-digital converter, the first output is connected to the input of the digital indicator, and the second - to the input of the digital-to-analog output In addition, the outputs of the microprocessor system are connected, respectively, with the control inputs of the digital indicator, digital-analog converter, three-channel two-position switch, three-position switch, counter, analog-digital converter, and the fourth input of the coincidence element divider output the reference frequency is connected to the corresponding input of the first channel of the three-channel two-stage switch, the outputs of the digital-to-analog converter are connected to the corresponding control The main inputs of the attenuator of the input shaper, phase shifter, filter of one conversion channel and with the control input of the tunable heterodyne, the input of the analog-digital converter are connected to the output of the three-position switch. 0 five