RU1771075C - Device for receiving binary data in serial code - Google Patents

Abstract

The device contains: 1 decoder (1), 1 shift register (2), 1 write register (3), 2 inverters (4, 5), 2 delay blocks (6, 7), 2 triggers (8, 9), 1 element OR (10). 1-2-3, 1-4-2-3, 1-6-8-10-3, 1-8, 6-5-9-7-10, 4-9. 1 ill.

Description

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The invention relates to a communication technique for receiving binary information in a bi-pulse code and can be used in data transmission equipment.

Known devices in which short pulses act as a clock signal (see, for example, an article by VV Abramov and other Radio Engineering, 1982, Ns 2, p. 18-50). They provide information at a low speed, because the transmitted signal with a shortened clock has an extended frequency band, which must fit into a limited bandwidth of the transmission channel.

Other devices for receiving binary information are also known in which the pulses are forbidden in the used bi-pulse code (see, for example, the article by Korovkin VV, Permikov SV, Tatsenko VG Radio engineering, 1986, Ns 6, pp. 79-81; U.S. Pat. No. 2,180,712; U.S. Pat. No. 4,276,656).

The closest to the claimed technical essence and the fastest is the receiving device, known from the article by V.F. Sokol et al. (Multichannel data transmission system through a fiber waveguide with temporary channel compaction, Electronic Engineering in Automation, 1982, issue 13, pp. 60-266).

In this transmission system, a long pause, having a low level, and subsequent logical 1 in a bi-pulse code, serves as a clock signal.

The device contains a receiving unit (including an LED and microchips A2, A3), a clock isolator (microchips A1, A4, A7), a trigger (D1.1). control circuit (D1,2, D4), pulse shaper (D2, DZ), counter (D5, D6.1), inverter (D6.2), shift register (D8-D11) and write register (D12-D15).

The isolator input, the trigger S-input and the first input of the driver are connected to the outputs of the receiving unit, respectively. Trigger R inputs and control circuits are connected to the inverter output. The clock and third inputs and the first output of the control circuit are connected to the outputs of the isolator and trigger and the second input of the driver, respectively. The counter input is connected to the second output of the control circuit and the shift input of the shift register, and the output is connected to the input of the shift register record. The information input of the shift register is connected to the output of the driver, and the information outputs are connected to the information inputs of the recording register, respectively.

The input of the device is the input of the receiving unit, and the outputs are the outputs of the recording register.

The receiving device operates as follows.

The receiver unit converts the signal from the communication line to a form suitable for operation of the remaining units. A separator extracts clock pulses from the received signal.

0 The trigger goes into the logical 1 state when the first logical 1 in the input word arrives at its S-input, and after the pulse from the inverter goes to the R-input, the trigger returns to logical 0. The control circuit passes the clock pulses to its output when the presence of logical G at the third input and the absence of a pulse at the R-input.

The shaper modulates the pulses of the input signal to write them to the shift register. The counter counts the clock pulses and generates a transfer pulse through the number of clock cycles equal to the number of bits in the word. By this impulse occurs

5 overwriting information from the shift register to the write register. The shift register shifts the serial code, and the write register stores the parallel code until the next word arrives. In order to reliably restore synchronization upon receipt of the first sync pulse in this device, the pause should have a duration of at least the duration of the data words, because otherwise it cannot be distinguished from the information word. Thus, for example, for transmitting information bits, bits containing information and a clock signal are required. Such excess reduces the speed of information transfer in the known device E 2 (M + 1) / M times compared with the potential. The purpose of the invention is to increase noise immunity due to acceleration

5 establishing synchronization.

The essence of the invention consists in E decoding the input data and extracting clock pulses from them, followed by a shift of the decoded data i

0 overwrite them according to the signal received by t adding up the clock pulses of the clocks delayed by the delayed clock pulses, with the delayed signal being the result of clocking

5 verified clock pulses with sustained and inverted clock pulses.

The drawing shows structural diagrams, an example of a specific implementation of the invention.

The device comprises a decoder 1, the input of which is the input of the receiving device, register 2, shift, the information input of which is connected to the information output of the decoder, the register 3 of the record, the outputs of which are the outputs of the device, and the information inputs are connected to the outputs of the register 2, respectively. inverters 4 and 5 (first and second, respectively), delay blocks b and 7 (first and second, respectively), trigger 8 (the first combined inverse R and D inputs of which are connected to the inputs of element 6 and inverter 4 and the clock output of the decoder 1, and C-input - to the output of element 6 and the input of inverter 5, trigger 9 (second), the combined inverse R- and D-inputs of which are connected to the output of inverter 4 and the clock input of register 2, C-input - to the output of inverter 5 and the output is with the input of the element OR 10, the inputs of which are connected to the outputs of the trigger 8 and element 7, respectively, and the output is to the input of the register 3.

A device that implements the invention provides higher noise immunity, resulting in less loss of information when synchronization fails, since it is installed after the first clock signal, in contrast to the known device, where the synchronization is established after the clock signal following the first word in the information parts

which either the syncrocombi is absent or is shifted closer to the beginning of the word than in the previous word.

Claims (1)

SUMMARY OF THE INVENTION A device for receiving binary information in a serial code comprising a first inverter, a first trigger, a shift register, the outputs of which are connected to the information inputs of a recording register, the outputs of which are the outputs of the device, characterized in that, in order to increase the noise immunity by accelerating the establishment of synchronization, a second inverter, a second trigger, two delay units, an OR element, and a decoder, the input of which is the input of the device, and the information output is connected to the information by the shift register input, the decoder clock output is connected to the inverse R and D inputs of the first trigger, through the first inverter to the shift register clock input and the inverse R and D inputs of the second trigger, and through the first delay block with the C input of the first trigger and the input of the second inverter, the output of which is connected to the C-input of the second trigger, the output of which through the second delay unit is connected to the first input of the OR element, the second input of which is connected to the output of the first trigger, and the output to the input of the recording register record.