RU139233U1 - DEVICE FOR MONITORING AND MANAGING RECONFIGURATION OF A THREE-CHANNEL COMPUTING SYSTEM - Google Patents

Abstract

A device for monitoring and controlling the reconfiguration of a three-channel computing system, which differs from the known ones in that it contains three computing modules, three asynchronous and one synchronous comparison circuit, one majority element, a fault code register, random access memory, a counter of the number of fault code repeats, nine AND elements, three OR elements, two single-pulse generators, configuration ROM, configuration loading device, device data input, three computing data inputs muzzle, three inputs of the “Reset” command, three inputs of the “Stop” command, three inputs of the configuration download, input of the initiator command, three outputs of the “Ready” command, three outputs of the data of the computing modules, the output of the device data, and the device data input is connected to the data inputs first to third computing modules, the data output of the first computing module is connected to the first input of the first asynchronous comparison circuit, the second input of the third asynchronous comparison circuit and the first input of the majority element, the data output of the second computing about the module is connected to the first input of the second asynchronous comparison circuit, the second input of the first asynchronous comparison circuit and the third input of the majority element, the data output of the third computing module is connected to the first input of the third asynchronous comparison circuit, the second input of the second asynchronous comparison circuit and the second input of the majority element, output the majority element is connected to the device data output, the inverse output of the first asynchronous comparison circuit is connected to the first input of the first AND element, the second input is second

Description

The utility model relates to the field of automation and computer engineering and can be used in control and computing systems with n - versions of software, as well as in debugging systems of complex control systems.

The closest analogue of the proposed utility model is a control device for restoring the computing process in a three-channel system (US Pat. RF No. 109304).

A disadvantage of the known device is a significant decrease in the reliability of the operation during the manifestation of software defects that lead to pairwise system failures.

The purpose of the utility model is to increase the reliability of the functioning of a three-channel computer system by controlling the change of software versions in redundant computing modules.

In the future, software versions will be understood as a set of two or more information processing programs loaded into computing modules developed separately according to the same functional requirements.

The essence of the utility model is as follows.

The device operates in a three-channel configuration. In the process of functioning, the data is processed by computational modules and through the majority element are sent to the output of the device. At the same time, the data from the outputs of the computing modules are fed to the inputs of asynchronous comparison circuits, which, using a group of AND elements, form a fault code. The DTC is entered in the DTC register. In addition, the first OR element and the second group of AND elements use the signals from the outputs of the asynchronous comparison circuits and the outputs of the Ready command of the computing modules to generate control actions on the input of the first single pulse generator.

The pulses from the output of the first single pulse generator are counted by the counter of the number of repetitions of the fault code, which controls the operating modes of the random access memory (write, read), modifies the (n-1) th bit of the initiating command, and also forms a command using the second OR element "Reset" for computing modules and controls the second single-pulse generator. The presence in the counter of the number of repetitions of the fault code of the first pulse corresponds to the transfer of random access memory to the data recording mode from the output of the fault code register, and the arrival of the second pulse indicates the permission to read data from the output of the random access memory.

The data from the outputs of the random access memory and the malfunction code register are synchronously compared by bit by the arrival of the clock from the output of the second single pulse generator. Depending on the comparison results, the senior (nth) bit of the initiating command is modified or the failed computing module is blocked using the signals from the outputs of the third group of elements I.

If the initiating command is modified, its submission to the input of the initiating command of the configuration loading control device allows you to integrate software versions into computing modules and replace the defective software version with a working one.

The device for monitoring and controlling the reconfiguration of the three-channel computing system contains (Fig. 1): three computing modules 1-3, three asynchronous 4-6 and one synchronous 21 comparison circuit, one majority element 25, a fault code register 13, random access memory 16, a counter the number of repetitions of the fault code 17, nine elements AND 7-9, 11, 12, 18-20, 26, three elements OR 10, 15, 27, two single pulse generators 14, 22, configuration ROM 23, boot device configuration 24, input device data 28, three compute data inputs unit modules 1.1-3.1, three inputs of the Reset command 1.2-3.2, three inputs of the Stop command 1.5-3.5, three inputs of the configuration download 1.6-3.6, input of the initiator command 24.1, three outputs of the Ready command 1.3-3.3, three data output of computing modules 1.4-3.4, data output of the device 29.

The purpose of the individual elements and blocks of the circuit.

The first 1 - third 3 computing modules process data.

The first 4 - third 6 asynchronous comparison circuits perform bitwise comparison of the data processing results of the first 1 - third 3 computing modules with each other and form a single signal at their inverse outputs in case of data mismatch and at direct outputs in case of coincidence.

The synchronous comparison circuit is intended for bitwise comparison of data from the outputs of the malfunction code register 13 and random access memory 16 using synchronizing signals from the output of the second single pulse generator 22 and generating a single signal at the inverse output in case of data mismatch and at the direct output in case of coincidence.

The majority element 25 selects the data coming from the first 1 - third 3 computing modules according to the 2/3 scheme and transmits the data corresponding to most of the input to the output of the device 29.

The malfunction code register 13 is designed to receive, store and issue a code corresponding to a malfunctioning computing module to the data input of random access memory 16, the second input of the synchronous comparison circuit 21 and the input of the initiator command 24.1. Moreover, the register has a capacity of - n. Zero, first and second digits contain a fault code, and (n-1) and n-th digits contain information about the software download mode.

The random access memory 16 receives data from the fault code register 13, stores and issues the fault code to the first input of the synchronous comparison circuit 21, depending on the control signals from the outputs of the counter for the number of repetitions of the fault code 17.

The counter of the number of repetitions of the fault code 17 performs the counting of pulses from the output of the single pulse generator 14, which corresponds to the number of repetitions of the fault code, controls the operating modes of the random access memory 16 and the second single pulse generator 22.

The first 7 - third 9 elements AND carry out the formation of a code that corresponds to the number of the faulty computing module, according to the signals from the inverse outputs of the first 4 - third 6 asynchronous comparison circuits.

The fourth element And 11 is designed to control the operation of the first 14 single pulse generator.

The fifth element And 12 generates a reset signal counter for the number of repetitions of trouble code 17 and supplies a single signal to the third input of the second element OR 15.

The sixth element And 18 forms a blocking signal of the third 3 computing module.

The seventh element And 19 forms a blocking signal of the second 2 computing module.

The eighth element And 20 generates a blocking signal of the first 1 computing module.

The ninth element And 26 is designed to generate a signal on the fourth input of the second element OR 15 according to the data obtained from the direct outputs of the first 4-third 6 asynchronous comparison circuits.

The first element OR 10 is designed to transmit a signal from the inverse outputs of the first 4 - third 6 asynchronous comparison circuits to the first input of the fourth 11 element I.

The second element OR 15 provides a signal to the inputs of the command "Reset" 1.2-3.2 of the first 1 - third 3 computing module.

The third element OR 27 generates a signal to set the counter for the number of repetitions of trouble code 17 to zero.

The first single pulse generator 14 generates a pulse to the counting input of the counter of the number of repetitions of the fault code 17 by the signal from the output of the fourth 11 element I.

The second single pulse generator 22 is designed to generate a clock pulse to the synchronization input of the synchronous comparison circuit 21 by command from the first 2 ¹ output of the counter of the number of repetitions of the fault code 17.

Configuration ROM 23 is used to store n - versions of data processing programs that are loaded into the first 1 - third 3 computing modules.

The configuration loading device 24 downloads the versions of the data processing programs into the first 1 - third 3 computing modules depending on the signal at the input of the initiator command 24.1.

The data input of the device 28 is designed to supply data to the first 1 - third 3 computing modules.

The first 1.1 - third 3.1 data inputs receive and download data from the data input of the device 28 into the first 1 - third 3 computing modules.

The first 1.2 - the third 3.2 inputs of the "Reset" command receive a signal from the output of the second 15 OR elements. The inputs are dynamic and respond to changes in the input logic signal from low to high.

The first 1.5 - the third 3.5 inputs of the Stop command receive signals from the outputs of the sixth 18th - eighth of 20 elements I.

The first 1.6 - third 3.6 configuration loading inputs are intended for loading versions of data processing programs from configuration ROM 23 into the first 1 - third 3 computing modules.

The input of the initiator command 24.1 receives control commands that determine the loading order of the versions of the data processing programs from the output of the fault code register 13.

The first 1.3 - third 3.3 outputs of the "Ready" command give a single signal in case of completion of data processing in the first 1 - third 3 computing module, respectively, on the second - fourth inputs of the fourth 8 element I.

The first 1.4 - third 3.4 outputs of the data of the computing modules are designed to transfer data from the first 1 - third 3 computing modules to the inputs of the first 4 - third 6 comparison circuits and the inputs of the majority element.

The output of the device 29 transmits the processed data to consumers.

The control device and control reconfiguration of a three-channel computing system operates as follows.

In the initial state, all the bits of the register of the fault code 13, the counter of the number of repetitions of the fault code 17, are in the zero state, the write enable (WR) and read enable (RE) inputs of the RAM 16 are set to zero, the first 1.2 - third 3.2 inputs “Reset” command, at the first 1.5 - third 3.5 inputs of the “Stop” command - a zero signal, at the first 1.3 - third 3.3 outputs of the “Ready” command, a logic zero is set, at the input of the initiator command 24.1 a zero signal is set. In addition, different versions of software that implement the same information processing algorithm are loaded into each computing module. The initialization circuits of FIG. 1 conventionally not shown.

There are three modes of operation of the device.

The first mode of operation characterizes the proper functioning of three computing modules. In this case, information through the data input of the device 28 is simultaneously supplied to the first 1.1 - third 3.1 data inputs of the first 1 - third 3 computing modules that process the received information. After that, the processing results simultaneously arrive at the first 1.4 - third 3.4 data outputs of the first 1 - third 3 computing modules. At the same time, on the first 1.3 - third 3.3 output of the Ready command of computing modules, single signals are set.

Information from the first 1.4 - third 3.4 data outputs of the first 1 - third 3 computing modules simultaneously arrives at the inputs of the majority element 25 and the inputs of the first 4 - third 6 asynchronous comparison circuits. Next, the majority element 25 selects the received information according to scheme 2/3 and through the data output of the device 29 transfers to the consumer the data that corresponds to most of the input. In turn, the first 4 - third 6 asynchronous comparison circuits perform bitwise comparison of the information received from the first 1.4 - third 3.4 outputs of the data of computing modules. Since, all computational modules are operational, on the direct outputs of the first 3 - third 6 asynchronous comparison circuits, single signals are set, and on their inverse outputs - zero. Zero signals at the inverted outputs of the first 3 - third 6 asynchronous comparison circuits, upon entering the first inputs of the first 7 - third 9 elements And install at their outputs, and, therefore, at the inputs of the malfunction code register 13 low level signals. In addition, the zero signals from the inverse outputs of the first 3 - third 6 asynchronous comparison circuits, passing through the first 10 OR element, will go to the first input of the fourth 11 And element and block it. In this case, the first single pulse generator 14 will not generate a counting pulse, the state of the counter of the number of repetitions of the fault code 17 will not change, and the signal from the output of the fault code register 13 will not be written to the random access memory 16. In turn, the signals from the direct outputs of the first 4 - third 6 asynchronous comparison circuits will go to the first - third inputs of the fifth 12 element And, which is closed by a low level signal at the zero 2 ° output of the counter for the number of repetitions of fault code 17, and the first - third inputs of the ninth 26 e And, which allows you to set a single signal at the output of the second 15 OR element, and, therefore, at the first 1.2 - third 3.2 inputs of the "Reset" command of the first 1 - third 3 computing modules. Having received the “Reset” command for the logic signal difference from low to high at the first 1.3 - third 3.3 outputs of the “Ready” command of the first 1 - third 3 computing modules, zero signals are set. Next, the computing modules through the data input of the device 28 and the first 1.1 - third 3.1 data inputs receive the next packet of information for processing and the cycle repeats.

The second mode of operation of the device characterizes the presence of a failure in the computing module.

Consider the operation of the device when a failure occurred in the second 2 computing module. The functioning of the device in this case consists of two cycles.

In the first cycle, information from the data input of the device 28 through the first 1.1 - third 3.1 data inputs goes to the first 1 - third 3 computing modules, where it is processed by the loaded program. When the data processing is completed, the first 1.3 - third 3.3 outputs of the "Ready" command will set up single signals, and the processing results through the first 1.4 - third 3.4 outputs of the data of the computing modules are simultaneously sent to the first - third inputs of the majority element 25 and the first - second inputs of the first 4 - third 6 asynchronous comparison circuits.

Next, the majority element 25 selects the received information according to scheme 2/3 and through the data output of the device 29 transfers to the consumer the data that corresponds to most of the input. If a failure occurs in the second 2 computational module, a single signal will be established at the inverse output of the first 4 asynchronous comparison circuit, and zero at the direct output, a single signal will appear at the inverse output of the second 5 asynchronous comparison circuit, and the third 6 asynchronous output at the inverse output of the second 5 the comparison circuit will establish a zero signal, and at the direct output - a single one.

Such a combination of signals will allow:

firstly, set the output of the first 7 element AND a zero signal, the output of the second 8 element AND a single signal, the output of the third 9 element AND a zero signal, therefore, zero is located in the zero bit of the fault code register 13, one is in the first bit, in the second category, zero;

secondly, to establish a single signal at the output of the first 10 element OR, and consequently, at the first input of the fourth element And 11, which, together with single signals at the first 1.3 - third 3.3 outputs of the Ready command, will start the first single pulse generator 14;

third, close the fifth 12th and ninth 26th elements of I.

The pulse generated by the first single pulse generator 14 will arrive at the counting input of the counter of the number of repetitions of the fault code 17 and will set its zero discharge 2 ° to a single state. In turn, a single state of zero discharge 2 ° of the counter of the number of repeats of the malfunction code 17 will put the random access memory 16 into recording mode (a single signal at the input WR), which will allow writing the code located in the register of the malfunction code 13 to the random access memory 16 data input. A single signal from the zero-bit output 2 ° of the counter for the number of repetitions of the DTC 17 modifies the (n-1) -th bit of the initiating command at the output of the DTC 13 register and, passing through the second 15 OR element, will go to the first 1.2 - third 3.2 command inputs "Reset" of the first 1 - third 3 computing modules.

By the “Reset” command, when changing from a low to a high level of a logic signal, the first 1.3 - third 3.3 outputs of the “Ready” command of the first 1 - third 3 computational modules set zero signals. At the same time, the modified initiator command from the output of the fault code register 13 will go to the input of the initiator command 24.1, which will start the software version change in the first 1 - 3 of 3 computing modules through the first 1.6 - third 3.6 configuration loading inputs.

Changing software versions is as follows.

The software, which was located in the first 1 computing module, is loaded into the second 2 computing module.

The software, which was located in the second 2 computing module, is loaded into the third 3 computing module.

The software, which was located in the third 3 computing module, is loaded into the first 1 computing module.

Computing modules through the data input of the device 28 and the first 1.1 - the third 3.1 data inputs receive the next packet of information for processing, after which the second cycle starts.

The second cycle of the device’s functioning, in the event of a failure in the second 2 computing module, is characterized by the restoration of its proper functioning after changing the software in the computing modules. In this case, the transmission of information to the output of the device 29 occurs similarly to the above and on the direct outputs of the asynchronous comparison circuits, single signals are set, and on the inverted ones - zero, on the first 1.3 - third 3.3 outputs of the “Ready” command of the computing modules, single signals are set. Such a combination of signals will lead to the installation of the outputs of the first 7 - third 9 elements AND zero signals, which will change the state of the least significant bits (zero, first and second) of the DTC 13 register to zero. The zero signal at the first input of the fourth 11th element And closes it and thereby prohibits changing the state of the counter of the number of repetitions of fault code 17, and single signals at the first - fourth inputs of the fifth 12th element And initiate the installation of a high level signal at its output, which is received through the first input the third element OR 27 to the reset input R ₀ counter of the number of repetitions of the trouble code 17 will translate its bits to zero. The low-level signal at the zero-bit output 2 ° of the counter for the number of repetitions of fault code 17 will set the (n-1) -th bit of the initiator command to zero. At the same time, a single signal, passing through the second 15 OR element, will go to the first 1.2 - third 3.2 inputs of the "Reset" command of the first 1 - third 3 computing modules and will set on the first 1.3 - third 3.3 outputs according to the logic signal difference from low to high "Ready" commands zero signals, which will allow the reception of the next information module through the data input of the device 28.

In case of failures in other channels, the device operates similarly to the above.

The third mode of operation of the device characterizes the presence of failure in the computing module.

Consider the operation of the device in the case when the second 2 computing module failed.

The first cycle of the operation of the device in case of failure of the second 2 computing module is similar to the first cycle of the operation of the device in the event of a failure.

The difference between the second cycle and the previous mode is as follows.

After changing the software in the first 1 - third 3 computing modules and processing the received information through the majority element 25 and the data output of the device 29, the consumer will receive the data that corresponds to most of the input. At the same time, high-level signals will appear on the first 1.3 - third 3.3 outputs of the "Ready" command.

Further, there are two options for the operation of the device.

The first option characterizes the operation of the device in case of failure of the element base of the computing module. In this case, on the inverse outputs of the first 4 and second 5 of the asynchronous comparison circuit and on the direct output of the third 6 comparison circuit, single signals will be established, at their other outputs - zero,

This combination of signals will result in the following:

firstly, it will allow to establish a zero signal at the outputs of the first 7 and third 9 AND elements, and a single signal at the outputs of the second 8 AND element. These signals will record low and low level signals in the zero and second digits of the DTC register 13, and a single signal in its first digit;

secondly, with the help of single signals at the first 1.3 - third 3.3 outputs of the “Ready” command and at the output of the first 11 OR element, the first 14 single pulse generator will generate a signal to the counter input of the number of repeats of the fault code 17, which will increase the counter by one, what initiates the appearance of a single signal at its first 2 ¹ output;

thirdly, a single signal at the first 2 ¹ output of the counter of the number of repeats of the fault code 17 will put the random access memory 16 (a single signal at the input of RE) into read mode, which will initiate the appearance of a fault code recorded in the previous cycle on its output.

The code from the output of the random access memory 16 will go to the first input of the synchronous comparison circuit 21, and the code from the output of the malfunction code register 13 will go to its second input. In turn, the synchronous clock comparison circuit from the output of the second 22 single pulse generator, which will be triggered by a single signal from the first 2 ¹ output of the counter of the number of repeats of the fault code 17, will perform a bitwise comparison of these codes.

The equality of these codes indicates the failure of the computing module (in the situation under consideration, the second 2 computing modules), since the change of software versions did not lead to the restoration of the computing process or the change in the code obtained in the first cycle. If the codes are equal, the direct output of the synchronous comparison circuit will establish a single signal, which is fed to the second inputs of the sixth 18 - eighth 20 elements I. The first inputs of these elements will receive signals from the lower digits of the fault code register 13, and the signal from the zero bit goes to the first input of the sixth 18th element And, the signal from the first bit is fed to the first input of the seventh 19th element And and the signal from the second bit is fed to the first input of the eighth 20th element I. In this case, in a single state is he first discharge DTC register 13. This means that the output of the seventh AND gate 19 will be a high level signal which goes to a second 2.5 "Stop" input commands and blocks 2 of the second computer module.

Next, the second 15 OR element, on the basis of the signal from the output of the first bit 2 of the counter for the number of repetitions of the fault code 17, generates a single signal to the first 1.2 - third 3.2 inputs of the Reset command of the first 1 - third 3 computing modules and by the logic signal difference from low to high will reset the device.

In addition, the signal from the output of the second single pulse generator 22 through the second input of the third element OR 27 will go to the reset input R _{0 of the} counter of the number of repetitions of the fault code 17 and will translate it into a zero state.

The zero state of the counter prohibits reading and writing to the random access memory 16 and prohibits the formation of a pulse by the second single pulse generator 22, which will block the synchronous comparison circuit 21.

The second option describes the operation of the device in the event of a software version failure.

Since, after the first cycle, the software located in the second 2 computational module is loaded into the third 3 computational module, single signals will be installed on the inverse outputs of the second 5 and third 6 comparison circuits, and zero on their other outputs.

This will allow you to record a single signal in the second bit of the fault code register 13, and low level signals in the zero and first bits. Therefore, the code at the outputs of random access memory 16 and the register of the fault code 13 do not match.

The difference in the codes at the inputs of the synchronous comparison circuit 21 indicates a software version failure, and a single signal is installed at its inverse output, which modifies the highest (nth) bit of the initiating command, which, upon entering the initiating command 24.1, will configure the configuration loading device 24 to load the software into the computing modules in such a way that the failed version will be replaced by the backup one.

In addition, the sixth 18 - eighth 20 elements And will be closed by a zero signal at the direct output of the synchronous comparison circuit 21, therefore, the blocking of the computing modules does not occur.

The remaining attributes of the functioning of the device in this embodiment are similar to the variant characterizing the operation of the device in the event of a failure of the element base of the computing module.

In the absence of a backup version of the software, the device can load one version of the software into serviceable computing modules, that is, switch to functioning in a single-version version.

In case of failures in other channels, the device operates similarly to the above.

In the event of a failure or failure, when one of the computing modules is already excluded from the configuration, the device operates only in the third mode.

A complete failure of the device will occur in case of failure of two computing modules or all versions of the software.

Thus, the developed device improves the reliability of the three-channel computing system by controlling the change of software versions in the backup computing modules.

Claims (1)

A device for monitoring and controlling the reconfiguration of a three-channel computing system, which differs from the known ones in that it contains three computing modules, three asynchronous and one synchronous comparison circuit, one majority element, a fault code register, random access memory, a counter of the number of fault code repeats, nine AND elements, three OR elements, two single-pulse generators, configuration ROM, configuration loading device, device data input, three computing data inputs muzzle, three inputs of the “Reset” command, three inputs of the “Stop” command, three inputs of the configuration download, input of the initiator command, three outputs of the “Ready” command, three outputs of the data of the computing modules, the output of the device data, and the device data input is connected to the data inputs first to third computing modules, the data output of the first computing module is connected to the first input of the first asynchronous comparison circuit, the second input of the third asynchronous comparison circuit and the first input of the majority element, the data output of the second computing about the module is connected to the first input of the second asynchronous comparison circuit, the second input of the first asynchronous comparison circuit and the third input of the majority element, the data output of the third computing module is connected to the first input of the third asynchronous comparison circuit, the second input of the second asynchronous comparison circuit and the second input of the majority element, output the majority element is connected to the device data output, the inverse output of the first asynchronous comparison circuit is connected to the first input of the first AND element, the second input is second of the second AND element and the third input of the first OR element, the inverse output of the second comparison circuit is connected to the first input of the second AND element, the second input of the third AND element and the second input of the first OR element, the inverse output of the third asynchronous comparison circuit is connected to the first input of the third AND element, the second the input of the first AND element and the first input of the first OR element, the direct output of the first asynchronous comparison circuit is connected to the first input of the fifth AND element and the first input of the ninth AND element, the direct output of the second asynchronous circuit Comparison is connected to the second input of the fifth element And and the second input of the ninth element And, the direct output of the third asynchronous comparison circuit is connected to the third input of the fifth element And and the third input of the ninth element And, the output of the ninth element And is connected to the fourth input of the second OR element, the output of the first element And is connected to the zero input of the fault code register, the output of the second element is connected to the first input of the fault code register, the output of the third element is connected to the second input of the fault code register, you One of the first OR elements is connected to the first input of the fourth AND element, the output of the “Ready” command of the first computing module is connected to the fourth input of the fourth AND element, the output of the “Ready” command of the second computing module is connected to the third input of the fourth AND element, the output of the “Ready” command of the third the computing module is connected to the second input of the fourth element And, the output of the fourth element And is connected to the input of the first single pulse generator, the output of the fifth element And is connected to the first input of the third OR element and with t by the second input of the second OR element, code register output the malfunction is connected to the data input of the random access memory, the second input of the synchronous comparison circuit and the input of the initiator command of the configuration ROM, the output of the first single pulse generator is connected to the counting input of the counter of the number of repeats of the fault code, the zero-bit output of the counter of the number of repeats of the fault code is connected to the fourth input of the fifth element And, the input enable recording of random access memory, the first input of the second OR element and (n-1) -th bit of the command in initiator, the output of the first bit of the counter of the number of repeats of the fault code is connected to the input of the second single pulse generator, the read enable input of the random access memory and the second input of the second OR element, the output of the second OR element is connected to the inputs of the Reset command of the first to third computing modules, the output of the second a single pulse generator is connected to the synchronization input of the synchronous comparison circuit and the second input of the third OR element, the output of the third OR element is connected to the reset input and the counter of the number of repeats of the fault code, the output of the random access memory is connected to the first input of the synchronous comparison circuit, the zero bit of the output of the random access memory is connected to the first input of the sixth element AND, the first discharge of the output of random access memory is connected to the first input of the seventh element And, the second discharge random access memory is connected to the first input of the eighth element And, the direct output of the synchronous comparison circuit is connected to the second inputs of the eighth and eighth element AND, the inverse output of the synchronous comparison circuit is connected to the highest (nth) bit of the initiator command, the output of the sixth element And is connected to the input of the Stop command of the third computing module, the output of the seventh element And is connected to the input of the Stop command of the second computing module, the output of the eighth element AND is connected to the input of the Stop command of the first computing module, the output of the configuration ROM is connected to the input of the configuration loading device, the output of the configuration loading device is connected to the first - third input loading configurations of the first to third computing modules.

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