RU1378681C - Matrix memory storage made in mosfet with variable threshold - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: stray capacitance of memory access bus which charging time is about 40-60% overall access time. So, this effects access speed a lot. EFFECT: increased speed. 2 cl, 3 dwg

Description

 The invention relates to computer technology and can be used in the design of integrated circuits of electrically reprogrammable read-only memory devices (EEPROM).

 The aim of the invention is to increase performance.

 In FIG. 1 shows the electrical circuit of the drive; in FIG. 2 - typical time diagrams of the drive in the modes of recording and reading information; in FIG. 3 - an example of the implementation of the drive (p. 1 file).

 The drive contains a group of memory transistors 1, which form memory cells 2, the sources and drains of transistors 1 are combined with the source 3 and 4 drain buses, respectively, the gates of the transistors 1 are connected to the number buses 5. In addition, the drive is equipped with additional discharge buses 6,7, additional numeric buses 8-11, the control bus 12 and the control MOS transistors 13,14, for example n-channel, two for each cell.

 To program the selected memory transistor 1, let it be the upper transistor 1 for definiteness, in the upper left cell (see Fig. 1), a programming voltage with an amplitude of 20-25 V and a duration is applied to the gate bus 5 connected to the gate of the selected transistor 1-3 ms (see Fig. 2).

 An additional discharge bus 6 connected to the selected section is grounded and then, opening an additional transistor 13 with high potential on the bus 8, connect the bus 6 to the source bus 3 of this section. In this case, the second additional transistors 14 are closed by low potential on the additional numerical bus 9. As a result, the channel potential of the selected transistor 1 will be equal to zero and under the influence of the programming voltage applied entirely to the gate dielectric of this transistor, its threshold voltage will increase, for example, from 1, 5 to 6 V. In order to prevent programming of an unselected transistor 1 located on the same line (i.e., an MNOS transistor located in the upper right cell and the gate It is connected to the same gate numerical bus 5) to unselected additional bit buses, for example, to bus 7, a half-sampling voltage with an amplitude, for example, 10-15 V and the same duration as the programming pulse, is applied. This voltage through an open transistor 13 is supplied to the source bus and channels of the unselected transistors 1, applied to their gate gate voltage dielectric, for example 10 V, is not enough to change their threshold voltage, which retains its previous value of 1.5 V.

 If, in accordance with the second paragraph of the formula, the corresponding gate numeric buses of each section are interconnected, then to prevent the programming of unselected MNOS transistors in other sections of the sections (for example, the lower sections in Fig. 2), a half-sample voltage is also applied to their channel. To do this, the half-sampling voltage is set on the control bus 12, which is connected through transistors 14, open with high potential on another numerical bus 10, to the drain discharge buses of unselected sections.

 To read the selected transistor 1 (let it still be the upper transistor in the upper left section in Fig. 1), the drain bit line 4 of the selected section is connected via an open transistor 14 to the control bus 12, on which a voltage, for example, 5 V. An additional transistor 13 of the selected section is opened with a voltage of 5 V on the bus 8, and an additional discharge bus 6 of the selected section is connected through the column decoder to the input of the readout amplifier. Then, a read voltage with an amplitude of, for example, 5 V is supplied to the selected gate digital bus 5. If the threshold voltage of the selected memory transistor is 1.5 V, it opens and the potential on the bus 6 starts to increase, which will be detected by the read amplifier as a logical state " 0 "of this transistor. If the threshold voltage of the selected transistor is 5 V or more, then the selected transistor will be closed, the potential on the additional discharge bus 6 will not increase and this will correspond to the logical state "1" of this transistor.

 Before writing new information to the drive, the previously recorded information is erased, i.e., the threshold voltages of all transistors 1 are aligned at, for example, 1-1.5 V. This procedure differs from the programming mode described above only in that the transistors are supplied to the gates 1, the erase voltage differs in amplitude from the programming voltage, for example, less than it and is equal to 15-20 V. Such an organization of erasure makes it possible to perform this operation selectively. You can also immediately erase information from the entire drive. To do this, it is enough to apply the erase voltage to all the gate numeric buses, and connect all the source buses 3 to additional discharge buses, which in turn connect everything to ground.

 The increase in performance in the drive of the proposed design is achieved by reducing the parasitic capacitance of the discharge bus, the charging time of which when reading is usually 40-60% of the total sampling time and therefore has a significant impact on performance. (56) Application (EPO) N 0081951, cl. H 01 L 29/60, 1983.

 Application (EPO) N 0209006, CL G 11 C 29/00, 1984.

Claims (2)

 1. MATRIX DRIVE ON MOSFET TRANSISTORS WITH VARIABLE THRESHOLD INCLUSIONS, containing memory cells, each of which consists of a group of memory transistors, each of which has a corresponding group of gates connected to a terminal and connected to a terminal , characterized in that, in order to increase the speed of the matrix drive, it contains additional numerical discharging and control buses, and control MIS transistors are inserted into each memory cell, ok the first control MIS transistor is connected to the sources of the memory transistors of this memory cell, the drains of which are connected to the drain of the second control MIS transistor, moreover, in each line of the shutter of the first and second control wires to the second , the sources of the second and first control MOS transistors of odd and even lines, respectively, are connected to the control bus.  2. The drive according to claim 1, characterized in that the corresponding gate numerical buses of each memory cell are combined.

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