KR100193450B1 - Isolated Sense Amplifiers in Nonvolatile Semiconductor Memory - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Sense amplifier element of semiconductor memory.

2. The technical problem to be solved by the invention

Provides an improved isolated sense amplifier.

3. Summary of Solution to Invention

An isolation part electrically connected to the first and second bit lines connected to the cell array and electrically isolated from the first and second bit lines in response to an isolation signal applied during sensing operation, and first connected to the front end of the input / output gating part. A precharge and equalizer for precharging and equalizing the first and second amplified bit lines in response to a precharge and equalization signal connected to and applied to a second amplified bit line, and a front end of the precharge and equalizer And a latch type sense amplifier unit positioned at a position between the latch type sense amplifier unit and the isolation unit and performing a sensing operation according to a latch voltage applied to the first and second amplified bit lines. Each gate terminal is connected to a line, and drain terminals thereof are respectively connected to the first and second amplification bit lines, and source terminals are connected to a predetermined power supply. It has a latch portion consisting of a sense amplifier isolated by the first and second transistors respectively receiving.

4. Important uses of the invention

It is suitably used for semiconductor memories.

Description

Isolated Sense Amplifiers in Nonvolatile Semiconductor Memory

1 is a circuit diagram of a sense amplifier according to the prior art.

2 is a timing diagram of a normal sensing operation according to FIG.

3 is a circuit diagram of an isolated sense amplifier according to an embodiment of the present invention.

4A and 4B are timing diagrams for the normal sensing operation and the inverted sensing operation according to FIGS. 3 and 6, respectively.

5A and 5B are graphs showing simulation results of normal sensing and inverted sensing according to FIGS. 3 and 6, respectively.

6 is a circuit diagram of an isolated sense amplifier according to another embodiment of the present invention.

The present invention relates to a nonvolatile semiconductor memory, and more particularly to an isolated sense amplifier of a flash memory having a NAND cell structure.

In general, many devices controlled by computers or microprocessors require the development of high density electrically erasable and programmable nonvolatile semiconductor memories ("EEPROM"). Moreover, the use of hard disk devices with rotating magnetic disks as auxiliary memory devices in portable computer or notebook-sized battery power systems occupies a relatively large area, so designers of such systems have a high density, high performance that occupies smaller areas. Are more interested in the development of EEPROM. In order to make such a high density and high performance EEPROM, it is important to reduce the area occupied by memory cells. Recently, as one of the technologies to solve such a problem, an EEPROM having a NAND structured cell capable of reducing the number of select transistors per cell and the number of connection openings with a bit line has been developed in the art. The improved device structure formed on the P well region formed in the N-type semiconductor substrate and the improved erase and program technology using the device structure are also disclosed in Symposium on VLSI Technology, published in 1990, Pages 129-130 are disclosed under the heading “A NAND STRECTURED CELL WITH A NEW PROGRAMMING TECHNOLOGY FOR HIGHLY RELIABLE 5V-ONLY FLASH EEPROM”.

Meanwhile, in the art, as described above, an EEPROM having a NAND cell structure has a mode of temporarily erasing memory transistors in a memory cell array, which is commonly referred to as a flash memory.

The sense amplifiers used in such flash memories are responsible for sensing and amplifying the voltages appearing on the bit lines of the memory cell array. Typically, in the memory, OV is applied to the gate terminal of the selected cell transistor during the read operation.

In this case, if the selected cell is programmed to have a positive threshold voltage, the connected bit line appears to maintain the initial precharge level, and conversely, to have a negative threshold voltage. If the erased cell is selected, the bit line remains at ground level.

Therefore, as described above, the sense amplifier amplifies the potential difference between the reference bit line and the developed bit line represented by the precharge level or the ground level by the threshold voltage of the selected cell during the read operation.

A conventional sense amplifier performing the above operation is shown in FIG. Referring to FIG. 1, electrically switching an NMOS sense amplifier unit 103, a PMOS signal amplifier unit 104, and a cell array 101 that are connected to a bit line having a folded bit line structure and perform an amplification function. The isolation section 102, the transistor element 105 for precharging the amplification stage bit line, and the input / output gating and the IO line 106 constitute a sense amplifier.

The normal sensing operation of the sense amplifier of FIG. 1 will be described with reference to FIG.

First, an erased cell is selected and a developed voltage is displayed on the bit line BL1 connected to the first end of the cell array 101 of FIG. 1, and a reference cell is selected on the bit line BL2 connected to the second end to display the voltage accordingly. Assume that this is the case. In this case the reference cell is designed as an intermediate level for the voltages of the erased and programmed cells.

The pulse signal ISO of FIG. 2 drives the transistor in the isolation section 102 in the bit line BL1,2, which is sufficiently developed. Here, the high level of the pulse signal must be equal to or more than the sum (Vcc + 2Vt) level of the power supply voltage and the threshold voltage twice, to prevent the voltage of the bit lines from being dropped by the isolation transformers. Accordingly, the level of the bit lines of the cell array 101 stage developed as shown by the waveforms BL1 and 2 of FIG. 2 is shifted to the waveforms SBL1 and 2. This transition level appears on the bit lines SBL1, 2 of the amplifier stage precharged to the power supply voltage Vcc level. As the sense amplifier enable signals LA and LAB are applied to the NMOS and PMOS sense amplifier units, the voltage level of the amplifier stage SBL1 is sensed at 0 volts and the voltage level of the amplifier stage SBL2 is sensed at the power supply voltage Vcc. This sensed voltage is applied to input / output gating and IO line 106.

In the conventional sense amplifier described with reference to FIGS. 1 and 2, the bit line isolation signal ISO must be maintained in the form of a pulse having a predetermined interval during sensing operation, and the high level of the pulse is twice the power supply voltage and the threshold voltage. There is a design constraint that must be at least the sum (Vcc + 2Vt) level. In addition, bit line loading of the cell array stage affects the amplification stage of the rear stage during sensing, causing a delay in sensing speed and an increase in peak current. In addition, the above circuit has a problem that only the normal sensing operation and the inverted sensing operation that performs the sensing operation so that the data opposite to the selected cell data can be performed can free the design of the input / output gating unit. It becomes the factor to make it impossible.

Accordingly, an object of the present invention is to provide a sense amplifier that can solve the above-mentioned conventional problems.

Another object of the present invention is to provide a sense amplifier of a nonvolatile semiconductor memory having a folded bit line structure capable of performing a stable sensing operation without applying a bit line isolation signal in a pulse form.

Another object of the present invention is to provide a sense amplifier that can electrically isolate a bit line of a memory cell array stage from a bit line of an amplifier stage in a sensing operation.

Still another object of the present invention is to provide a sense amplifier for flash memory capable of performing an inverted sensing operation for performing a sensing operation to output not only normal sensing operations but also opposite logic data to selected cell data.

According to the sense amplifier of the present invention for achieving the above object, in the sense amplifier circuit of a nonvolatile semiconductor memory having a folded bit line structure:

An isolation unit electrically connected to the first and second bit lines respectively connected to a cell array having a reference cell and a NAND cell structure and electrically isolating the first and second bit lines in response to an isolation signal applied during a sensing operation;

A precharge and equalizer for precharging and equalizing the first and second amplified bit lines in response to precharge and equalization signals connected to and applied to the first and second amplified bit lines respectively connected to the front end of the input / output gating part; ;

A latch type sense amplifier unit positioned at a front end of the precharge and equalization unit and connected to the first and second amplified bit lines to perform a sensing operation according to an applied latch voltage;

First and second transistors disposed between the latch type sense amplifier and the isolation unit, each gate terminal of which is connected to the first and second bit lines and drain terminals thereof connected to the first and second amplifying bit lines, respectively; And an isolation latch part including third and fourth transistors respectively applying a predetermined power voltage to the source terminals of the first and second transistors in response to an external control signal indicating the start of sensing.

Hereinafter, a preferred sense amplifier circuit according to the present invention will be described with reference to the accompanying drawings. The same reference numerals among the reference numerals in the accompanying drawings indicate that they have the same configuration and function as much as possible, even if indicated on different drawings.

Therefore, if a reference numeral is shown in the drawings of the prior art will be understood as equivalents or corresponding equivalent elements. In the following description, the detailed items for such configurations are described in detail in order to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. Moreover, features and configurations of well-known basic elements are not described in detail in order not to obscure the present invention.

First, referring to FIG. 3 illustrating an example of a sense amplifier according to the present invention, an isolation signal connected to first and second bit lines respectively connected to a cell array 101 having a reference cell and a NAND cell structure and applied during a sensing operation is provided. In response to the precharge and equalization signals connected to and applied to the isolation section 102 for electrically isolating the first and second bit lines, and to the first and second amplification bits, respectively connected to the front end of the input / output gating section 106. Precharge and equalizer 206 for precharging and equalizing the first and second amplified bit lines, and placed in front of the precharge and equalizer 206 and connected to and applied to the first and second amplified bit lines. A latch type sense amplifier unit 103 and 104 and a latch type sense amplifier unit 103 and the isolation unit 102 which perform a sensing operation according to a latch voltage are located, and each gate terminal is cross-connected to the first and second bit lines. And its drain terminals are respectively connected to the first and second amplification bit lines, and the source terminals are isolated latch portions 203 made up of first and second transistors N1 and N2 respectively receiving a predetermined power supply voltage in response to an external control signal. It is composed. Here, the preset power supply voltage VSA is provided by enMOS transistors N3 and N4 driven according to the external control signal PISA.

Referring to FIG. 6 showing another example of the sense amplifier according to the present invention, the isolation unit 102, the precharge and equalization unit 206, the latch type sense amplifier unit 103, 104, and the latch type sense amplifier unit 103 are shown in FIG. The sense amplifier section 103 has the same configuration as that of FIG. 3, and is located between the sense amplifier section 103 and the isolation section 102, and each gate terminal corresponds to the first and second bit lines. And the drain terminals thereof are respectively connected to the first and second amplification bit lines, and the source terminals of the first and second transistors N1 and N2 respectively receive a predetermined power supply voltage in response to an external control signal. It consists of. Here, the preset power supply voltage VSA is provided by enMOS transistors N3 and N4 driven according to the external control signal PISA.

The operation of the sense amplifier configured as shown in FIG. 3 will be described below with reference to FIGS. 4 and 5. First, referring to FIG. 4A, in the normal sensing operation, the first and second amplified bit lines SBL1 and 2 are precharged to the power supply voltage Vcc level by the N-type transistor in the precharge and equalizer 206. In addition, the preset power supply voltage VSA applied by the external control signal PISA is applied as OV. The latch signals LA and LAB are both precharged to the power supply voltage Vcc level. Under this initial condition, if one of the first and second bit lines is developed according to the state of the cell selected by the word line control signal, the developed bit line and the referer after a predetermined time as shown in FIG. 4A. The operation of sensing the potential difference between the lance bit lines is started. Accordingly, the transistors N3 and 4 are turned on by the external control signal PISA transitioning high, and the latch type sense amplifiers 103 and 104 start a sensing operation. Here, the signal PISA is a predetermined time later to prevent the ground DC current path of the first and second amplified bit lines SBL1 and SBL2 caused by the gate bias of the first and second bit lines BL1 and BL2 which are developed after sensing. The signal is disabled. In addition, it is preferable to continuously disable the bit line isolation signal ISO to low level to develop the SBL1 and 2 lines in a state where the bit line loading is completely excluded. In this case, the first and second amplified bit lines SBL1 and 2 are sensed as Vcc and VSA is precharged or switched to ground, so that BL1 is developed to OV and Bl2 is developed to a reference level. In the case of sensing on-cell data, the line SBL1 is developed with OV and SBL2 is developed with Vcc to access the same phase data as the cell data.

Next, the inverted sensing operation will be described with reference to FIG. 4b. The first and second amplified bit lines SBL1 and 2 are discharged to OV through the precharge and equalizer 206 and Vcc is applied to the VSA and LA. The above operation is performed under an initial condition where both LABs are charged to OV. In this case, since the sensing operation similar to the normal operation is performed, when BL1 is an OV, BL2 is an on-cell (erased cell) data sensing that is developed at a reference level, SBL1 is developed into Vcc and SBL2 is developed into OV. The data of the phase opposite to the data is accessed.

5a and b are graphs showing simulation results of normal sensing and inverted sensing according to FIG. 3, respectively. When the power supply voltage Vcc is 3.8V and the temperature is -5 ° C, the waveform of each line for normal and inverted sensing is shown corresponding to the line number in FIG. Accordingly, in FIG. 3, since the bit lines of the cell array unit are electrically isolated during the sensing operation, the sensing speed and the peak current are significantly reduced.

Meanwhile, the operation of the sense amplifier configured as shown in FIG. 6 will be described below with reference to FIGS. 4 and 5. First, referring to FIG. 4A, when the inverted sensing operation is performed, the first and second amplified bit lines SBL1 and 2 are precharged to the power supply voltage Vcc level by the N-type transistor in the precharge and equalizer 206. In addition, the preset power supply voltage VSA applied by the external control signal PISA is applied as OV. The latch signals LA and LAB are both precharged to the power supply voltage Vcc level. Under this initial condition, if one of the first and second bit lines is developed according to the state of the cell selected by the word line control signal, the developed bit line and the referer after a predetermined time as shown in FIG. 4A. The operation of sensing the transition difference between the lance bit lines is started. Accordingly, the transistors N3 and 4 are turned on by the external control signal PISA transitioning high, and the latch type sense amplifiers 103 and 104 start a sensing operation. Here, the signal PISA is a predetermined time later to prevent the ground DC current path of the first and second amplified bit lines SBL1 and SBL2 caused by the gate bias of the first and second bit lines BL1 and BL2 which are developed after sensing. The signal is disabled. In addition, it is preferable to continuously disable the bit line isolation signal ISO to low level to develop the SBL1, 2 lines in a state where the bit line loading is completely excluded. In this case, the first and second amplified bit lines SBL1 and 2 are sensed at Vcc, and the VSA is precharged or switched to ground, so that BL1 is OV and BL2 is developed at a reference level. In the case of sensing on-cell data, the line SBL1 is developed to Vcc and SBL2 to OV to access phase data opposite to the cell data.

Next, the normal sensing operation will be described with reference to FIG. 4b. The first and second amplified bit lines SBL1 and 2 are discharged to OV through the precharge and equalizer 206 and Vcc is applied to the VSA, and LA, The above operations are performed under an initial condition where both LABs are charged to OV. In this case, since the sensing operation similar to the normal operation is performed, when BL1 is OV, BL2 is on-cell (erased cell) data sensing at the reference level, SBL1 is OV and SBL2 is developed at Vcc. Data on the same phase as the data is accessed.

5a and b are graphs showing simulation results of inverted and normal sensing according to FIG. 6, respectively. When the power supply voltage Vcc is 3.8V and the temperature is -5 ° C, the waveform of each line for inverted sensing and normal sensing is shown corresponding to the line number of FIG. Accordingly, it can be seen that FIG. 6 shows that the bit line of the cell array unit is electrically isolated during the sensing operation, thereby significantly reducing the sensing speed and the peak current.

As described above, according to the sense amplifier of the present invention, it is possible to perform a stable sensing operation without applying the bit line isolation signal in the form of a pulse. In addition, in the sensing operation, the bit line of the memory cell array stage may be electrically isolated from the bit line of the amplifying stage, thereby increasing the sensing speed and reducing the peak current. In addition, it is possible to perform an inverted sensing operation that performs not only the normal sensing operation but also the sensing operation so that the data of the opposite logic is output to the selected cell data.

Claims (8)

A sense amplifier circuit of a nonvolatile semiconductor memory having a folded bit line structure, the sense amplifier circuit comprising: in response to an isolation signal connected to first and second bit lines respectively connected to a cell array having a reference cell and a NAND cell structure and applied during a sensing operation; An isolation portion for electrically isolating the first and second bit lines; A precharge and equalizer for precharging and equalizing the first and second amplified bit lines in response to precharge and equalization signals connected to and applied to the first and second amplified bit lines respectively connected to the front end of the input / output gating part; ; A latch type sense amplifier unit positioned at a front end of the precharge and equalization unit and connected to the first and second amplified bit lines to perform a sensing operation according to an applied latch voltage; First and second transistors disposed between the latch type sense amplifier and the isolation unit, each gate terminal of which is connected to the first and second bit lines and drain terminals thereof connected to the first and second amplifying bit lines, respectively; And an isolation latch part including third and fourth transistors respectively applying a predetermined power voltage to source terminals of the 1.2 transistor in response to an external control signal indicating the start of sensing. The circuit of claim 1, wherein the isolation unit comprises N-type MOS transistors having drain terminals connected to the first and second bit lines, and OV is applied to gates of the transistors during a sensing operation. The circuit of claim 1, wherein the first and second transistors of the isolation latch unit are formed of N-type transistors. The circuit of claim 1, wherein the external control signal is a signal enabled at a high level when sensing. The circuit of claim 1, wherein the latch time sense amplifiers are configured in the form of latches of PMOS and NMOS transistors, and the initial levels of the enable signals have a power supply voltage or an OV voltage when normal sensing is performed. . 6. The method of claim 5, wherein the initial level of the enable signal has a voltage opposite to that of the normal sensing when inverted sensing, and the enable timing is concurrent with the time when the voltage is applied to the source terminal of the isolation latch unit. Or after that circuit. A sense amplifier of a flash memory having a folded bit line structure, the sense amplifier comprising: electrically connecting the first and second bit lines in response to an isolation signal applied to a first and second bit lines respectively connected to a NAND structure cell array and applied during a sensing operation. An isolation section for isolation; A precharge and equalizer for precharging and equalizing the first and second amplified bit lines in response to precharge and equalization signals connected to and applied to the first and second amplified bit lines respectively connected to the front end of the input / output gating part; ; A latch type sense amplifier unit positioned at a front end of the precharge and equalization unit and connected to the first and second amplified bit lines to perform a sensing operation according to an applied latch voltage; Located between the latch type sense amplifier and the isolation unit, each gate terminal is cross-connected to the first and second bit lines, drain terminals thereof are connected to the first and second amplified bit lines, and source terminals are external control signals. And an isolation latch means comprising first and second transistors respectively receiving a predetermined power supply voltage responsive to the first and second drain terminals of the first and second transistors, respectively, to supply the power supply voltage. Sense amp. A sense amplifier circuit of a nonvolatile semiconductor memory having a folded bit line structure, the sense amplifier circuit comprising: in response to an isolation signal connected to first and second bit lines respectively connected to a cell array having a reference cell and a NAND cell structure and applied during a sensing operation; An isolation portion for electrically isolating the first and second bit lines; A precharge and equalizer for precharging and equalizing the first and second amplified bit lines in response to precharge and equalization signals connected to and applied to the first and second amplified bit lines respectively connected to the front end of the input / output gating part; ; A latch type sense amplifier unit positioned at a front end of the precharge and equalization unit and connected to the first and second amplified bit lines to perform a sensing operation according to an applied latch voltage; First and second transistors disposed between the latch type sense amplifier and the isolation unit, the gate terminals corresponding to the first and second bit lines, and the drain terminals thereof respectively connected to the first and second amplification bit lines. And an isolation latch part comprising third and fourth transistors respectively applying a predetermined power voltage to source terminals of the first and second transistors in response to an external control signal indicating the start of sensing.