RU134378U1 - DECODER - Google Patents

Abstract

A decoding device containing a maximum signal selection unit and a multiplier and an integrator connected in series, the output of each integrator is connected to the input of the maximum signal selection unit, one input of each multiplier is connected to the input of the decoding device, characterized in that it contains N decoders, the maximum signal selection unit on N inputs, K bit shift register, binary encoder and memory block for allowed code combinations on 2 outputs, each of which is connected to another input multiplier, wherein each decoder is made of a maximum signal selection block for (2) / N inputs and (2) / N series-connected multipliers and integrators, outputs (2) / N of integrators are connected to (2) / N inputs of the selection block the maximum signal at (2) / N inputs, the outputs of N decoders are connected to the N inputs of the block for selecting the maximum signal at N inputs, the output of which is connected through a binary encoder to the inputs K of the bit shift register, the outputs of which are the output of the decoding device in a binary serial K bit ohm code.

Description

The invention relates to the field of transmission, reception and processing of encoded data and can be used in receivers for optimal decoding of a received code combination.

Known decoding device, which is an implementation of a method for decoding a cyclic error-correcting code, containing a latch S _{i of} code combinations of a given length n _min -n _max , a calculator N of the largest common factors and a selection block of N polynomials of common factors with the smallest degree that corresponds to the codeword [1] . The known device allows you to determine the parameters of the error-correcting code used directly from the received code sequence before decoding.

A disadvantage of the known decoding device is that it requires sophisticated equipment to identify the code word from the received code sequence and it takes a long time to decide on the result of decoding.

Closest to the proposed known technical solution is a multi-alternative device for detecting and distinguishing (decoding) signals, comprising a maximum signal selection unit and a multiplier and an integrator connected in series, the output of each integrator is connected to the input of the maximum signal selection unit, one input of each multiplier is connected to the input of the decoding device, as well as the known device contains sequentially interconnected block squaring n signal, an integrator, an extractor from the square root of the received signal and a multiplier, the output of which is connected through the comparison unit to the control input of the key, the output of which is connected to the output "Presence" of the signal, and the other output of the comparison unit is connected to the output "Absence" of the signal [2 ]. From the accepted 2 ^K realizations of the random signal, where K is the number of information symbols in the code, the presence or absence of the signal is determined by t - Student's criterion and a decision is made in favor of one or another signal, that is, decoding is performed.

вычислительных операций, каждая из которых выполняется за время, равное t_П. При этом общее время декодирования, например, при числе комбинаций 2^K=1024 составит 523776·t_П, что является чрезмерно большой величиной.The disadvantage of the prototype is that in order to make a decision on the result of decoding the adopted code combination by t - student criterion

computing operations, each of which is performed for a time equal to t _P. Moreover, the total decoding time, for example, with the number of combinations 2 ^K = 1024 will be 523776 · t _P , which is an excessively large value.

The purpose of the utility model (technical result) is to reduce the decoding time of the received code combination by dividing the decoding procedure into three consecutive stages, in the first of which N binary combinations are analyzed simultaneously (in parallel), then the one that has the maximum number of matches is selected from N previously selected combinations with one of the allowed combinations (maximum correlation coefficient) and, finally, the resulting binary combination corresponding to the maximum signal is translated I'm in serial binary.

The essence of the utility model is that, in addition to the well-known and general distinguishing features, namely: the maximum signal selection unit and the multiplier and integrator connected in series, the output of each integrator is connected to the input of the maximum signal selection unit, one input of each multiplier is connected to the input decoding device, the proposed decoding device contains N decoders, a block for selecting the maximum signal for N inputs, K is a bit shift register, a binary encoder and a memory block bit shennyh codewords is 2 ^K outputs, each of which is connected to another input of the multiplier, wherein each decoder is adapted to the maximum signal selecting unit to (2 ^K) / N inputs and (2 ^K) / N sequentially interconnected multiplier and integrator, the outputs of (2 ^K ) / N integrators are connected to (2 ^K ) / N inputs of the maximum signal selection block at (2 ^K ) / N inputs, the outputs of N decoders are connected to N inputs of the maximum signal selection block at N inputs, the output of which is connected via binary encoder with inputs of K - bit shift register, output which are the output of the decoding device in a binary serial K bit code.

The novelty of the utility model lies in the fact that the proposed decoding device contains N decoders, a block for selecting the maximum signal for N inputs, a K bit shift register, a binary encoder and a block for storing allowed code combinations for 2 ^K outputs, each of which is connected to a different input of the multiplier, in this case, each decoder is made from the maximum signal selection block for (2 ^K ) / N inputs and (2 ^K ) / N series-connected multipliers and integrators, outputs (2 ^K ) / N of integrators are connected to (2 ^K ) / N inputs block selecting the maximum signal (2 ^K) / N inputs, outputs N decoders connected to N inputs of maximum signal selecting unit to N inputs, whose output is connected via a binary encoder with input K-bit shift register, the outputs of which are the output of the decoding device in the binary sequential K bit code, which reduces the decoding time of the received code pattern.

The scheme of the proposed decoding device is shown in the drawing, where it is indicated:

1.1, 1.2, ..., 1. (2 ^K ) / N - multipliers (bitwise comparison blocks);

2.1, 2.2, ..., 2. (2 ^K ) / N - integrators;

3.1, 3.2, ..., 3.N - blocks for selecting the maximum signal for (2 ^K ) / N inputs of each block;

4 - block memorization of allowed code combinations for 2 ^K outputs;

5 - block selection of the maximum signal to N inputs;

6 - binary encoder;

7 - K bit shift register (K shift register);

8.1, 8.2, ..., 8.N - decoders;

K is the number of bits of a binary sequential code.

In the initial position (static), the outputs of the multipliers 1 through integrators 2 are connected to the corresponding inputs of blocks 3 for selecting the maximum signal. The outputs of block 4 for storing allowed code combinations are associated with one input of each multiplier 1, the other inputs of which are connected to the input of the decoding device. The inputs of the maximum selection block 5 are connected to the outputs of the maximum signal selection blocks 3, and the output of the maximum selection block 5 is connected through the binary encoder 6 to the inputs of the shift register 7. In each decoder 8, multipliers 1, integrators 2, and the maximum signal selection block are connected in series 3.

The proposed decoding device operates as follows. The accepted binary code combination with possible errors, as in the prototype, is analyzed using well-known functional blocks: multipliers 1 (bitwise comparison blocks), integrators 2 (drives) and a maximum signal extraction unit 3. For each input of all multipliers (2 ^K ) / N each from N decoders, an input binary combination is received for bitwise comparison, and the corresponding allowed code combination is sent from the 2 ^K outputs of the memory unit 4 to the other input of these multipliers 1 The output signal of each multiplier 1 in each decoder 8 after integration (accumulation) by the corresponding integrator 2 is supplied to one of the (2 ^K ) / N corresponding inputs of the maximum signal 3 extraction unit of each of the N decoders 8.

The output signals of N decoders 8 are directed to the corresponding N inputs of the maximum signal extraction unit 5. The detected maximum signal at the output of block 5 in the form of a unitary potential through a binary encoder 6 is fed to the inputs K of the bit shift register 7 to present the maximum signal in the binary serial K bit code at the output of the decoding device.

The industrial feasibility of the utility model is justified by the fact that it uses the nodes and elements known in the analogue [1] and prototype [2] for their intended purpose. The applicant organization made a model of the declared decoding device in 2013.

(из 1024 по 2) определяется с помощью выражения:The positive effect of using the utility model is that it increases 522 times the speed of the decoding device in comparison with the prototype, where, for example, at K = 10 we have 2 ^K = 2 ¹⁰ = 1024 combinations, each of which can correspond to a combination accepted with distortions . Therefore, for decoding, you need to sort through all the combinations in pairs to determine the maximum matches. The number of pairwise searches (combinations)

(from 1024 to 2) is determined using the expression:

From the expression (1) it follows that to select the maximum value of the received signal with one of the allowed combinations, a time equal to 523776 · t _P is required, which reduces the speed of the known decoding device.

In the proposed decoding device, for example, with N = 32 and K = 10, we have the following decoding time

Expression (2) includes three consecutive decoding steps. The first two stages, as in the prototype, are determined by the number of combinations (combinations) of 32 to 2 characters of the received binary code. The final step involves converting the parallel code into a serial K bit binary. Comparing expressions (1) and (2), we conclude that the proposed decoding device provides an increase in performance by 522 times. Moreover, the increase in the number of elements is insignificant, because requires N maximum selection circuits, one encoder and one L bit shift register.

Information sources:

1. Patent RU 2284085 for the invention "Method for decoding a cyclic noise-immune code", IPC G06F 11/00, H03M 13/15, priority: 10.03.2005, authors: Egurnov V.O. et al., patent holder: Military Academy of Communications, (analogue).

2. V.I. Borisov, V.M. Zinchuk, A.I. Limarev, V.I. Shestopalov. Interference immunity of radio communication systems with spreading of the spectrum by direct modulation by a pseudo-random sequence / Ed. IN AND. Borisov. Ed. 2nd, rev. and add. - M .: RadioSoft. - 2011 .-- 550 s; silt. 281, p. 283, fig. 7.12, (prototype).

Claims (1)

A decoding device containing a maximum signal selection unit and a multiplier and an integrator connected in series, the output of each integrator is connected to the input of the maximum signal selection unit, one input of each multiplier is connected to the input of the decoding device, characterized in that it contains N decoders, the maximum signal selection unit on N inputs, K bit shift register, binary encoder and memory block for allowed code combinations for 2 ^K outputs, each of which is connected to another input multiplier, with each decoder made up of a block for selecting the maximum signal for (2 ^K ) / N inputs and (2 ^K ) / N series-connected multipliers and integrators, outputs (2 ^K ) / N of integrators connected to (2 ^K ) / N inputs of the maximum signal selection block at (2 ^K ) / N inputs, the outputs of N decoders are connected to N inputs of the maximum signal selection block at N inputs, the output of which is connected through a binary encoder to the inputs of the K bit shift register, the outputs of which are the output of the decoding device in binary follower Mr. To the bit code.

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