RU128424U1 - SYNCHRONOUS FORMULATOR - Google Patents

Abstract

A clock generator, consisting of an asynchronous random access memory, a first adder, a second adder, a third adder, a fourth adder, a multiplexer, a counter for switching the control code of the multiplexer, a counter for the number of synchronization pulses, a counter for generating a pause duration, a counter for generating pulse durations, an SR trigger, the first output of asynchronous RAM, the input of which is the first input of the clock generator, is connected by a bus to the first input of the counter the number of synchronization pulses whose output is connected to the first input of the pause duration counter, the output of the pause duration counter is connected to the first input of the SR trigger, the output of which is the output of the clock generator, the second output of the asynchronous RAM is connected to the first input of the counter of the pulse duration, the first input of the first adder, the first input of the second adder, the first input of the third adder and the first input of the fourth adder, the third asynchronous output RAM bus is connected to the second input of the first adder, the fourth output of the asynchronous RAM bus is connected to the second input of the second adder, the fifth output of the asynchronous RAM bus is connected to the second input of the third adder, the sixth output of the asynchronous RAM bus is connected to the second input of the fourth adder, the output of the first adder bus connected to the first input of the multiplexer, the output of the second adder by a bus connected to the second input of the multiplexer, the output of the third adder by a bus connected to the third input of the multiplexer, the output of four

Description

The proposed utility model relates to a pulsed technique for processing a digital signal and can be used in synchronization systems of multifunctional radars (MFRS).

It is known "Device clock synchronization of a digital signal" [2286007 C1 publ. 20.10.2006], which contains two triggers with inverse asynchronous reset and installation inputs, two NAND elements, a binary counter that contains a clock input and an asynchronous inverse reset input, an OR-NOT element, a synchronized digital signal input, a clock input and the first exit. In addition, it additionally contains a logical 1 input, a second output, an OR element, an exclusive OR element, and a code input for programming the threshold duration of barrage filtering of synchronization of the input digital signal as interference. Moreover, each of the triggers additionally contains a clock input and an information input, the counter is synchronous and additionally equipped with a code input, which is a code input for programming the duration of the barrage filtering of the synchronization of the input digital signal as interference, a direct account resolution input and an inverse recording resolution input, priority over the account resolution input .

Closest to the proposed utility model is the "Synchronization Device" [67318 G11C 8/18 publ. 20.10.2007], which contains an asynchronous random access memory, a first adder, a second adder, a third adder, a fourth adder, a multiplexer, a multiplexer control code switching counter, a counter of the number of synchronization pulses, a pause duration generation counter, a pulse duration generation counter, an SR trigger .

The disadvantages of these devices are the limitations of functionality and the inability to control the moment the start of the formation of synchronization pulses.

The technical result of the proposed utility model is the multimode of the shaper of the sync pulses i.e. programming the operating modes of the shaper in each working cycle, as a result of which it becomes possible to control the delay (pause) of the beginning of the formation of clock pulses using control codes.

The essence of the proposed utility model consists in that the clock generator consists of an asynchronous random access memory, a first adder, a second adder, a third adder, a fourth adder, a multiplexer, a multiplexer control code switching counter, a counter of the number of synchronization pulses, a pause duration counter, a formation counter pulse duration, SR-trigger. The first output of the asynchronous RAM, the input of which is the first input of the clock generator, is connected via a bus to the first input of the counter for the number of synchronization pulses, the output of which is connected to the first input of the pause duration counter, the output of the pause duration counter is connected to the first input of the SR trigger, the output of which is the output of the shaper of the clock pulses, the second output of the asynchronous RAM is connected via a bus to the first input of the counter for forming the pulse duration, the first input of the first the adder, the first input of the second adder, the first input of the third adder and the first input of the fourth adder, the third output of the asynchronous RAM bus is connected to the second input of the first adder, the fourth output of the asynchronous RAM is connected to the second input of the second adder, the fifth output of the asynchronous RAM is connected to the second input the third adder, the sixth output of the asynchronous RAM bus connected to the second input of the fourth adder, the output of the first adder bus connected to the first input of the multiplexer, the output of the second sum is connected by a bus to the second input of the multiplexer, the output of the third adder is connected via a bus to the third input of the multiplexer, the output of the fourth adder is connected by a bus to the fourth input of the multiplexer, the output of the multiplexer is connected to the second input of the pause duration counter, the output of the pulse duration counter is connected to the second input SR -trigger, the output of which is connected to the second input of the counter of the number of synchronization pulses and the input of the counter of switching the control code of the multiplexer, the output of which is connected by bus to the fifth input of the multiplexer.

The introduction of a pause counter for the start of pulse formation, a D-flip-flop, a 56 MHz generator, a comparator, a counter for generating a reference frequency is new. The seventh output of the asynchronous RAM is connected via a bus to the input of the pause counter of the beginning of pulse formation, the output of which is connected to the second input of the D-trigger, the output of the generator is connected to the input of the comparator, the output of which is connected to the first input of the reference frequency generation counter, the combined second input of the reference frequency generation counter and the third input of the D-flip-flop are the second input of the device, a high logic level VCC is connected to the first input of the D-flip-flop, the output of the D-flip-flop is connected to the third input of the counter of the number of imp lsov synchronization with fourth input of the counter forming the pause duration, the third input of the counter forming the pulse duration, the formation of the reference frequency counter output is connected to the third input of the counter forming the duration of the pause and the second input counter forming pulse duration.

Figure 1 presents the functional diagram of the proposed driver of the clock.

The clock generator consists of an asynchronous random access memory (RAM) (1), a pause counter for the start of pulse formation (2), a D-trigger (3), a first adder (4), a second adder (5), a third adder (6), and a fourth an adder (7), a counter for switching a control code of a multiplexer (8), a multiplexer (9), a counter for the number of synchronization pulses (10), a counter for generating a pause duration (11), a counter for generating pulse durations (12), an SR trigger (13), 56 MHz oscillator (14), comparator (15), counter Nia reference frequency (16).

The first output of asynchronous RAM (1), the input of which is the first input of the clock generator, is connected via a bus to the first input of the counter of the number of synchronization pulses (10), the output of which is connected to the first input of the counter for generating the pause duration (11). The output of the pause duration generation counter (11) is connected to the first input of the SR trigger (13), the output of which is the output of the clock driver. The second output of the asynchronous RAM (1) is connected via a bus to the first input of the pulse duration meter (12), the first input of the first adder (4), the first input of the second adder (5), the first input of the third adder (6) and the first input of the fourth adder (7) ) The third output of the asynchronous RAM (1) is connected via a bus to the second input of the first adder (4), the fourth output of the asynchronous RAM (1) is connected by a bus to the second input of the second adder (5), the fifth output of the asynchronous RAM (1) is connected to the second input of the third adder (6), the sixth RAM output (1) is connected by a bus to the second input of the fourth adder (7), the seventh RAM output (1) is connected by a bus to the input of the pause counter of the beginning of pulse formation (2), the output of which is connected to the second input of the D-trigger ( 3). The output of the first adder (4) is connected via a bus to the first input of the multiplexer (9), the output of the second adder (5) is connected by a bus to the second input of the multiplexer (9), the output of the third adder (6) is connected via a bus to the third input of the multiplexer (9), the output of the fourth the adder (7) bus connected to the fourth input of the multiplexer (9). The output of the multiplexer (9) is connected via a bus to the second input of the pause duration generation counter (11). The output of the generator (14) is connected to the input of the comparator (15), the output of which is connected to the first input of the counter for the formation of the reference frequency (16). The combined second input of the counter for the formation of the reference frequency (16) and the third input of the D-trigger (3) is the second input of the device. High logic level VCC is connected to the first input of the D-trigger (3). The output of the D-trigger (3) is connected to the third input of the counter for the number of synchronization pulses (10), to the fourth input of the counter for generating the pause duration (11), and to the third input of the counter for generating the pulse duration (12). The output of the counter for forming the reference frequency (16) is connected to the third input of the counter for forming the pause duration (11) and the second input of the counter for forming the pulse duration (12). The output of the counter for generating the pulse duration (12) is connected to the second input of the SR trigger (13), the output of which is connected to the second input of the counter of the number of synchronization pulses (10) and the input of the counter for switching the control code of the multiplexer (8), the output of which is connected to the fifth input by a bus multiplexer (9).

The clock generator operates as follows: 16-bit control codes are received at input 1 of asynchronous RAM (1)

dd [15..0] - code for the duration of the synchronization pulse,

dp [0] [15..0] - code of the 1st period of the synchronization pulse,

dp [1] [15..0] - code of the 2nd period of the synchronization pulse,

dp [2] [15..0] - code of the 3rd period of the synchronization pulse,

...

dp [n] [15..0] - code of the n-th period of the synchronization pulse,

dn [15..0] - code of the number of synchronization pulses,

ds [15 ... 0] - code delay before the formation of pulses.

An external sync pulse arrives at input 2 of the clock driver, which then goes to the second input of the installation of the counter for generating the reference frequency (16) and to the third input of the D-trigger reset (3). The output of the generator (14) is connected to the input of the comparator (15), in which the sinusoidal signal from the generator (14) is converted to a digital meander. From the output of the comparator (15), the signal is fed to the counting first input of the counter for forming the reference frequency (16), in which the signal of the reference frequency f _op is generated, by the presence of an external clock pulse. The reference frequency signal f _o from the output of the reference frequency generation counter (16) is fed to the counting third input of the pause duration generation counter (11) and to the second input of the pulse duration formation counter (12), from which the entire frequency grid of the clock generator is formed. The counter for generating pulse durations (12) counts the duration of the generated pulse (the synchronization pulse duration code dd [15..0] is sent to the data input 1 via the bus from the second output of asynchronous RAM (1)), the counter for generating pause durations (11) counts and generates a pause between two synchronization pulses (pause codes are applied to the second input of the counter data to generate periods of synchronization pulses), and the SR trigger (13) generates leading and trailing edges of the synchronization pulse train.

Pause codes are generated by the first adder (4), the second adder (5), the third adder (6) and the fourth adder (7) operating in the subtraction mode and at the output of the multiplexer (9), pause codes dpa [...] [15..0 ] of each adder are equal to the difference of the codes dp [...] [15..0] and dd [...] [15..0] for each period of the generated sync pulse. Codes dpa [...] [15..0] from the output of the multiplexer (9) are sent via the bus to the second data input of the counter for generating the pause duration (11). The multiplexer channel number (9) is selected by the fifth control input with a 2-bit code from the output of the switching counter of the multiplexer control code (8), to the counting input of which the generated synchronization output pulses are fed.

According to the code ds [15 ... 0], received at the input of the pause counter of the beginning of pulse formation (2), the interval is determined from the beginning of the external sync pulse received at input 2 of the device until the formation of synchronization pulses. From the output of the transfer of the pause counter of the beginning of the formation of pulses (2), the output signal of the end of the pause is fed to the second input of the D-trigger (3). High logic level VCC is connected to the first input of the D-trigger (3). At the output of the D-trigger (3), an interval (pause) is formed before the start of the generation of synchronization pulses - the enable strobe and goes to the reset inputs (initial setting) of the counters: to the third input of the counter of the number of synchronization pulses (10), to the fourth input of the counter for generating the pause duration (11) and to the third input of the counter forming the pulse duration (12).

According to the code dn [15..0] received at the first input of the counter of the number of synchronization pulses (10), the number of clock pulses in the packet is determined, then an enable signal is generated, which is fed to the resolution input 1 of the counter for generating the pause duration (11) to form a pause between the clock pulses .

Code dd [15..0] is calculated based on the required value of the duration of the clock:

dd [15..0] = τ _and -1;

code dp [...] [15..0] is calculated based on the required value of the period of the synchronization pulse T _and :

dp [...] [15..0] = T _and -1;

code dn [15..0] is calculated based on the required value of the number of clock pulses in the packet N _and :

dn [15..0] = N;

code ds [15 ... 0] is calculated on the basis of the required delay before the formation of clock pulses:

ds [15 ... 0] = T _C -1.

Thus, both single and bursts of synchronization pulses, adjustable in duration from pulse to pulse and repetition period, are formed with control of the moment of the beginning of the formation of clock pulses, an increase in productivity is achieved due to the possibility of controlling the moment of the start of the formation of synchronization pulses.

Claims (1)

A clock generator, consisting of an asynchronous random access memory, a first adder, a second adder, a third adder, a fourth adder, a multiplexer, a counter for switching a control code of a multiplexer, a counter for the number of synchronization pulses, a counter for generating a pause duration, a counter for generating pulse durations, an SR trigger, the first output of asynchronous RAM, the input of which is the first input of the clock generator, is connected by a bus to the first input of the counter the number of synchronization pulses, the output of which is connected to the first input of the pause duration counter, the output of the pause duration counter, is connected to the first input of the SR trigger, the output of which is the output of the clock generator, the second output of the asynchronous RAM is connected to the first input of the pulse duration counter, the first input of the first adder, the first input of the second adder, the first input of the third adder and the first input of the fourth adder, the third asynchronous output RAM bus is connected to the second input of the first adder, the fourth output of the asynchronous RAM bus is connected to the second input of the second adder, the fifth output of the asynchronous RAM bus is connected to the second input of the third adder, the sixth output of the asynchronous RAM bus is connected to the second input of the fourth adder, the output of the first adder bus connected to the first input of the multiplexer, the output of the second adder by a bus connected to the second input of the multiplexer, the output of the third adder by a bus connected to the third input of the multiplexer, the output of four the second adder is connected by a bus to the fourth input of the multiplexer, the output of the multiplexer is connected to the second input of the pause duration counter, the output of the pulse duration counter is connected to the second input of the SR trigger, the output of which is connected to the second input of the counter of the number of synchronization pulses and the input of the control code switching counter a multiplexer, the output of which is connected by a bus to the fifth input of the multiplexer, characterized in that a pause counter for initiating pulse formation is introduced, D-flip-flop, 56 MHz generator, comparator, reference frequency generation counter, the seventh output of the asynchronous RAM being connected via a bus to the input of the pause counter of the beginning of pulse formation, the output of which is connected to the second input of the D-flip-flop, the generator output is connected to the comparator input, the output of which is connected with the first input of the reference frequency forming counter, the combined second input of the reference frequency forming counter and the third input of the D-trigger are the second input of the device, a high logic level VCC is connected to the first the input of the D-trigger, the output of the D-trigger is connected to the third input of the counter for the number of synchronization pulses, with the fourth input of the counter for generating the pause duration, with the third input of the counter for generating the duration of the pulses, the output of the counter for generating the reference frequency is connected to the third input of the counter for generating the pause duration and the second input counter forming pulse duration.

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