PT84445B - Unidade de comando central com multiprocessadores protegida contra as avarias e com uma disponibilidade elevada de um sistema de comutacao e processo para a operacao da configuracao da memoria desta unidade de comando central - Google Patents

Unidade de comando central com multiprocessadores protegida contra as avarias e com uma disponibilidade elevada de um sistema de comutacao e processo para a operacao da configuracao da memoria desta unidade de comando central

Info

Publication number
PT84445B
PT84445B PT84445A PT8444587A PT84445B PT 84445 B PT84445 B PT 84445B PT 84445 A PT84445 A PT 84445A PT 8444587 A PT8444587 A PT 8444587A PT 84445 B PT84445 B PT 84445B
Authority
PT
Portugal
Prior art keywords
multiprocessors
switching system
protected against
control unit
centralized control
Prior art date
Application number
PT84445A
Other languages
English (en)
Portuguese (pt)
Other versions
PT84445A (de
Inventor
Rudolf Bitzinger
Walter Engl
Siegfried Humml
Klaus Schreier
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of PT84445A publication Critical patent/PT84445A/pt
Publication of PT84445B publication Critical patent/PT84445B/pt

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/54558—Redundancy, stand-by
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/5455—Multi-processor, parallelism, distributed systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Hardware Redundancy (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Exchange Systems With Centralized Control (AREA)
PT84445A 1986-03-12 1987-03-11 Unidade de comando central com multiprocessadores protegida contra as avarias e com uma disponibilidade elevada de um sistema de comutacao e processo para a operacao da configuracao da memoria desta unidade de comando central PT84445B (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3608245 1986-03-12
DE3625036 1986-07-24

Publications (2)

Publication Number Publication Date
PT84445A PT84445A (de) 1987-04-01
PT84445B true PT84445B (pt) 1989-10-04

Family

ID=25841898

Family Applications (1)

Application Number Title Priority Date Filing Date
PT84445A PT84445B (pt) 1986-03-12 1987-03-11 Unidade de comando central com multiprocessadores protegida contra as avarias e com uma disponibilidade elevada de um sistema de comutacao e processo para a operacao da configuracao da memoria desta unidade de comando central

Country Status (11)

Country Link
US (1) US4860333A (en, 2012)
EP (1) EP0238841B1 (en, 2012)
CN (1) CN1016828B (en, 2012)
AR (1) AR245831A1 (en, 2012)
AT (1) ATE69346T1 (en, 2012)
BR (1) BR8701107A (en, 2012)
DE (1) DE3774309D1 (en, 2012)
DK (1) DK166702B1 (en, 2012)
FI (1) FI89443C (en, 2012)
GR (1) GR3003729T3 (en, 2012)
PT (1) PT84445B (en, 2012)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4956766A (en) * 1985-07-25 1990-09-11 International Business Machines Corp. Systems for inhibiting errors caused by memory cartridge insertion/removal using an idle loop
ES2025099B3 (es) * 1986-07-23 1992-03-16 Siemens Ag Sistema de comunicacion isdn estructurado modular con formacion y anuncio de textos de faltas
CA1297593C (en) * 1987-10-08 1992-03-17 Stephen C. Leuty Fault tolerant ancillary messaging and recovery system and method within adigital switch
US5289586A (en) * 1988-11-29 1994-02-22 Hitachi, Ltd. Digital information transmission apparatus and method of driving information transmission bus system thereof
US5295258A (en) * 1989-12-22 1994-03-15 Tandem Computers Incorporated Fault-tolerant computer system with online recovery and reintegration of redundant components
ATE115805T1 (de) * 1990-03-23 1994-12-15 Siemens Ag Schaltungsanordnung für die routineprüfung einer schnittstelle zwischen anschlussgruppen und dem koppelnetz eines pcm- fernmeldevermittlungssystems.
US5544180A (en) * 1992-06-08 1996-08-06 Qlogic Corporation Error-tolerant byte synchronization recovery scheme
US5771367A (en) * 1992-12-17 1998-06-23 International Business Machines Corporation Storage controller and method for improved failure recovery using cross-coupled cache memories and nonvolatile stores
US5937029A (en) * 1996-08-02 1999-08-10 Nice Systems, Ltd. Data logging system employing M N +1! redundancy
KR19980020514A (ko) * 1996-09-09 1998-06-25 김광호 종합정보통신망 사설교환기의 결함내성 구현방법
JPH11331376A (ja) * 1998-05-08 1999-11-30 Fujitsu Ltd 電子交換機の試験手順実行方法及びそのシステム
US7111228B1 (en) 2002-05-07 2006-09-19 Marvell International Ltd. System and method for performing parity checks in disk storage system
US7007114B1 (en) * 2003-01-31 2006-02-28 Qlogic Corporation System and method for padding data blocks and/or removing padding from data blocks in storage controllers
US7287102B1 (en) 2003-01-31 2007-10-23 Marvell International Ltd. System and method for concatenating data
US7064915B1 (en) 2003-03-10 2006-06-20 Marvell International Ltd. Method and system for collecting servo field data from programmable devices in embedded disk controllers
US7080188B2 (en) 2003-03-10 2006-07-18 Marvell International Ltd. Method and system for embedded disk controllers
US7039771B1 (en) 2003-03-10 2006-05-02 Marvell International Ltd. Method and system for supporting multiple external serial port devices using a serial port controller in embedded disk controllers
US7870346B2 (en) 2003-03-10 2011-01-11 Marvell International Ltd. Servo controller interface module for embedded disk controllers
US7492545B1 (en) 2003-03-10 2009-02-17 Marvell International Ltd. Method and system for automatic time base adjustment for disk drive servo controllers
US7526691B1 (en) 2003-10-15 2009-04-28 Marvell International Ltd. System and method for using TAP controllers
US7139150B2 (en) 2004-02-10 2006-11-21 Marvell International Ltd. Method and system for head position control in embedded disk drive controllers
US7120084B2 (en) 2004-06-14 2006-10-10 Marvell International Ltd. Integrated memory controller
US8166217B2 (en) 2004-06-28 2012-04-24 Marvell International Ltd. System and method for reading and writing data using storage controllers
US7757009B2 (en) 2004-07-19 2010-07-13 Marvell International Ltd. Storage controllers with dynamic WWN storage modules and methods for managing data and connections between a host and a storage device
US9201599B2 (en) 2004-07-19 2015-12-01 Marvell International Ltd. System and method for transmitting data in storage controllers
US8032674B2 (en) * 2004-07-19 2011-10-04 Marvell International Ltd. System and method for controlling buffer memory overflow and underflow conditions in storage controllers
US7386661B2 (en) 2004-10-13 2008-06-10 Marvell International Ltd. Power save module for storage controllers
US7240267B2 (en) 2004-11-08 2007-07-03 Marvell International Ltd. System and method for conducting BIST operations
US7802026B2 (en) * 2004-11-15 2010-09-21 Marvell International Ltd. Method and system for processing frames in storage controllers
US7609468B2 (en) * 2005-04-06 2009-10-27 Marvell International Ltd. Method and system for read gate timing control for storage controllers
US7283418B2 (en) * 2005-07-26 2007-10-16 Micron Technology, Inc. Memory device and method having multiple address, data and command buses
JP5014899B2 (ja) * 2007-07-02 2012-08-29 ルネサスエレクトロニクス株式会社 再構成可能デバイス
US9847105B2 (en) * 2016-02-01 2017-12-19 Samsung Electric Co., Ltd. Memory package, memory module including the same, and operation method of memory package
CN108153648B (zh) * 2017-12-27 2021-04-20 西安奇维科技有限公司 一种实现灵活调度的多冗余计算机的方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2232256A5 (en, 2012) * 1973-05-29 1974-12-27 Labo Cent Telecommunicat
US3882455A (en) * 1973-09-14 1975-05-06 Gte Automatic Electric Lab Inc Configuration control circuit for control and maintenance complex of digital communications system
IT1111606B (it) * 1978-03-03 1986-01-13 Cselt Centro Studi Lab Telecom Sistema elaborativo modulare multiconfigurabile integrato con un sistema di preelaborazione
US4371754A (en) * 1980-11-19 1983-02-01 Rockwell International Corporation Automatic fault recovery system for a multiple processor telecommunications switching control
DE3334773A1 (de) * 1983-09-26 1984-11-08 Siemens AG, 1000 Berlin und 8000 München Verfahren zum betrieb eines in normalbetriebszeit parallel betriebenen speicherblockpaares

Also Published As

Publication number Publication date
FI89443C (fi) 1993-09-27
CN87101839A (zh) 1987-12-02
DK124587D0 (da) 1987-03-11
PT84445A (de) 1987-04-01
FI89443B (fi) 1993-06-15
EP0238841A1 (de) 1987-09-30
FI871059A0 (fi) 1987-03-11
BR8701107A (pt) 1987-12-29
US4860333A (en) 1989-08-22
DE3774309D1 (de) 1991-12-12
FI871059A7 (fi) 1987-09-13
CN1016828B (zh) 1992-05-27
AR245831A1 (es) 1994-02-28
DK124587A (da) 1987-09-13
DK166702B1 (da) 1993-06-28
GR3003729T3 (en, 2012) 1993-03-16
ATE69346T1 (de) 1991-11-15
EP0238841B1 (de) 1991-11-06

Similar Documents

Publication Publication Date Title
PT84445B (pt) Unidade de comando central com multiprocessadores protegida contra as avarias e com uma disponibilidade elevada de um sistema de comutacao e processo para a operacao da configuracao da memoria desta unidade de comando central
BR8701106A (pt) Processo para a operacao de uma unidade de comando central-multiprocessador com alta disponibilidade e com seguranca contra falhas,pertencente a um sistema de comutacao
BR8707421A (pt) Sistema para controlar o acesso a uma memoria de informacoes
BR8906001A (pt) Metodo e sistema para o estabelecimento de interfaces com uma pluralidade de programas de aplicacao
BR8705053A (pt) Processo para a fabricacao de um eixo de comando e eixo de comando
ES544377A0 (es) Una instalacion de control de acceso a memoria,de aplicaciona ordenadores
BR8801959A (pt) Dispositivo de comando de platinas para maquineta jacquard de cala aberta
IT1215741B (it) Procedimento e dispositivo per comandare l'intervento di organi di comando su un filatoio.
ES544045A0 (es) Un controlador de entrada-salida de una instalacion de orde-nador para multitud de memorias seriadas
BR8802460A (pt) Maquina ou instalacao,sistema de comando para um aparelho movel e processo para o controle de uma maquina ou instalacao
BR8707976A (pt) Processo para a operacao de uma unidade de comando central/multiprocessador de um sistema de comutacao
BR8907433A (pt) Processo para o tratamento de uma estrutura de titanio
BR8505166A (pt) Processo e disposicao de circuito para o controle funcional de instalacoes de alarme de ultra-som
PT90776A (pt) Processo para a deslenhificacao enzimatica de material lignocelulosico
ES549976A0 (es) Procedimiento para el control de un determinado numero de subprocesos al producirse un fallo de funcionamiento en un sistema de control distribuido
DE68927015D1 (de) Direktspeicherzugriffssteuerung
PT91286A (pt) Processo para a preparacao de sistemas de expressao de pectinas-liases
BR9104022A (pt) Instalacao para a operacao de um sistema multiprocessador,sobretudo de um comando numerico
CA2007004A1 (en) Multiprocessor controller having shared control store
BR8805347A (pt) Processo para controle de uma pluralidade de cabines de elevador;e sistema de controle operativo com o processo
PT90598A (pt) Sistema de comando e de controlo para uma instalacao que utiliza contactores
BR8701165A (pt) Processo para o controle de uma instalacao de injecao de combustivel e instalacao de injecao de combustivel
BR8805349A (pt) Processo para o controle de uma pluralidade de cabines de elevador;e sistema de controle operativo com o processo
BR8502263A (pt) Processo para o tratamento de liquidos de descontaminacao com acidos organicos e instalacao para o mesmo
ES2016373B3 (es) Proceso y dispositivo para el control redundante de un organo de potencia.

Legal Events

Date Code Title Description
MM3A Annulment or lapse

Free format text: LAPSE DUE TO NON-PAYMENT OF FEES

Effective date: 19990930