PT1025496E - Um metodo para a forte particao de um bus de plano posterior de multi-processadores vne - Google Patents

Um metodo para a forte particao de um bus de plano posterior de multi-processadores vne

Info

Publication number
PT1025496E
PT1025496E PT98949682T PT98949682T PT1025496E PT 1025496 E PT1025496 E PT 1025496E PT 98949682 T PT98949682 T PT 98949682T PT 98949682 T PT98949682 T PT 98949682T PT 1025496 E PT1025496 E PT 1025496E
Authority
PT
Portugal
Prior art keywords
message
vme
vmebus
vne
processing
Prior art date
Application number
PT98949682T
Other languages
English (en)
Inventor
F Mohamed Younis
Jeffrey X Zhou
Original Assignee
Allied Signal Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Allied Signal Inc filed Critical Allied Signal Inc
Publication of PT1025496E publication Critical patent/PT1025496E/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/546—Message passing systems or structures, e.g. queues
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/865—Monitoring of software

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • Quality & Reliability (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
PT98949682T 1997-09-29 1998-09-29 Um metodo para a forte particao de um bus de plano posterior de multi-processadores vne PT1025496E (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/939,943 US6047391A (en) 1997-09-29 1997-09-29 Method for strong partitioning of a multi-processor VME backplane bus

Publications (1)

Publication Number Publication Date
PT1025496E true PT1025496E (pt) 2002-06-28

Family

ID=25473977

Family Applications (1)

Application Number Title Priority Date Filing Date
PT98949682T PT1025496E (pt) 1997-09-29 1998-09-29 Um metodo para a forte particao de um bus de plano posterior de multi-processadores vne

Country Status (9)

Country Link
US (1) US6047391A (pt)
EP (1) EP1025496B1 (pt)
JP (1) JP2001518661A (pt)
AT (1) ATE212738T1 (pt)
AU (1) AU9595698A (pt)
CA (1) CA2305151A1 (pt)
DE (1) DE69803692T2 (pt)
PT (1) PT1025496E (pt)
WO (1) WO1999017198A1 (pt)

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US7239406B1 (en) 1999-09-30 2007-07-03 Ricoh Co., Ltd System for capturing facsimile data in an electronic document management system
EP1102472B1 (en) * 1999-11-12 2002-12-04 Ricoh Company, Ltd. Capturing facsimile data in an electronic document management system
DE19957594B4 (de) * 1999-11-30 2004-08-26 OCé PRINTING SYSTEMS GMBH Verfahren zum Synchronisieren von threads eines Computerprogramms
US6725317B1 (en) * 2000-04-29 2004-04-20 Hewlett-Packard Development Company, L.P. System and method for managing a computer system having a plurality of partitions
US6907560B2 (en) * 2001-04-02 2005-06-14 Nortel Networks Limited Forward error correction (FEC) on a link between ICs
US7152232B2 (en) * 2001-07-16 2006-12-19 Sun Microsystems, Inc. Hardware message buffer for supporting inter-processor communication
US8984199B2 (en) * 2003-07-31 2015-03-17 Intel Corporation Inter-processor interrupts
CN100338579C (zh) * 2004-02-24 2007-09-19 希旺科技股份有限公司 内建储存装置的usb集线器
US20050246474A1 (en) * 2004-04-29 2005-11-03 Wolfe Sarah M Monolithic VMEbus backplane having VME bridge module
US8898246B2 (en) * 2004-07-29 2014-11-25 Hewlett-Packard Development Company, L.P. Communication among partitioned devices
US7721260B2 (en) * 2004-09-08 2010-05-18 Kozio, Inc. Embedded Test I/O Engine
TWI254868B (en) * 2004-11-23 2006-05-11 Inst Information Industry System for fast developing and testing communication protocol software
WO2006058142A2 (en) * 2004-11-24 2006-06-01 Sioptical, Inc. Soi-based optical interconnect arrangement
US7457128B2 (en) * 2005-07-22 2008-11-25 Hewlett-Packard Development Company, L.P. Flexible cell configuration for multi-processor systems
US8046837B2 (en) 2005-08-26 2011-10-25 Sony Corporation Information processing device, information recording medium, information processing method, and computer program
JP4765485B2 (ja) * 2005-08-26 2011-09-07 ソニー株式会社 情報処理装置、情報記録媒体、および情報処理方法、並びにコンピュータ・プログラム
US7996714B2 (en) 2008-04-14 2011-08-09 Charles Stark Draper Laboratory, Inc. Systems and methods for redundancy management in fault tolerant computing
FR2933557B1 (fr) * 2008-07-02 2013-02-08 Airbus France Procede et dispositif de protection de l'integrite de donnees transmises sur un reseau
US8131975B1 (en) 2008-07-07 2012-03-06 Ovics Matrix processor initialization systems and methods
US7958341B1 (en) 2008-07-07 2011-06-07 Ovics Processing stream instruction in IC of mesh connected matrix of processors containing pipeline coupled switch transferring messages over consecutive cycles from one link to another link or memory
US8145880B1 (en) 2008-07-07 2012-03-27 Ovics Matrix processor data switch routing systems and methods
US7870365B1 (en) 2008-07-07 2011-01-11 Ovics Matrix of processors with data stream instruction execution pipeline coupled to data switch linking to neighbor units by non-contentious command channel / data channel
US8327114B1 (en) 2008-07-07 2012-12-04 Ovics Matrix processor proxy systems and methods
FR2943036B1 (fr) * 2009-03-11 2011-04-15 Airbus France Systeme distribue de commande de vol implemente selon une architecture avionique modulaire integree.
FR2945646B1 (fr) * 2009-05-18 2012-03-09 Airbus France Methode d'aide a la realisation et de validation d'une plateforme avionique
FR2945647A1 (fr) * 2009-05-18 2010-11-19 Airbus France Methode d'optimisation d'une plateforme avionique
US8792289B2 (en) 2010-07-28 2014-07-29 Hewlett-Packard Development Company, L.P. Rewriting a memory array
JP4905587B2 (ja) * 2010-12-28 2012-03-28 ソニー株式会社 情報処理装置、および情報処理方法、並びにコンピュータ・プログラム
US9558048B2 (en) * 2011-09-30 2017-01-31 Oracle International Corporation System and method for managing message queues for multinode applications in a transactional middleware machine environment
CN102868584B (zh) * 2012-10-11 2015-05-06 江苏西电南自智能电力设备有限公司 一种采用串行通信接口的同步时分多路复用总线通信方法
US10560542B2 (en) * 2014-09-15 2020-02-11 Ge Aviation Systems Llc Mechanism and method for communicating between a client and a server by accessing message data in a shared memory
US10037301B2 (en) * 2015-03-04 2018-07-31 Xilinx, Inc. Circuits and methods for inter-processor communication
WO2023194938A1 (en) * 2022-04-06 2023-10-12 New York University In Abu Dhabi Corporation System, method and computer-accessible medium for a zero-copy data-coherent shared-memory inter-process communication system

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EP0340901A3 (en) * 1988-03-23 1992-12-30 Du Pont Pixel Systems Limited Access system for dual port memory
US5204864A (en) * 1990-08-16 1993-04-20 Westinghouse Electric Corp. Multiprocessor bus debugger
DE69314353T2 (de) * 1992-06-15 1998-03-05 British Telecommunications P.L.C., London Diensteinrichtung
JPH0816419A (ja) * 1994-04-05 1996-01-19 Internatl Business Mach Corp <Ibm> メッセージ・データ・エラー検出システム

Also Published As

Publication number Publication date
JP2001518661A (ja) 2001-10-16
EP1025496A1 (en) 2000-08-09
DE69803692T2 (de) 2002-08-14
ATE212738T1 (de) 2002-02-15
US6047391A (en) 2000-04-04
WO1999017198A1 (en) 1999-04-08
CA2305151A1 (en) 1999-04-08
EP1025496B1 (en) 2002-01-30
AU9595698A (en) 1999-04-23
DE69803692D1 (de) 2002-03-14

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