PL445768A1 - RFID carrier frequency divider - Google Patents
RFID carrier frequency dividerInfo
- Publication number
- PL445768A1 PL445768A1 PL445768A PL44576823A PL445768A1 PL 445768 A1 PL445768 A1 PL 445768A1 PL 445768 A PL445768 A PL 445768A PL 44576823 A PL44576823 A PL 44576823A PL 445768 A1 PL445768 A1 PL 445768A1
- Authority
- PL
- Poland
- Prior art keywords
- flip
- flop
- series
- input
- output
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/84—Pulse counters comprising counting chains; Frequency dividers comprising counting chains using thyristors or unijunction transistors
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
Przedmiotem zgłoszenia jest dzielnik częstotliwości nośnej RFID posiadający przynajmniej dwa przerzutniki (D1, D2, D3, D4) o różnicowych wejściach i różnicowych wyjściach połączone w szereg tak, że wyjścia poprzedniego przerzutnika w szeregu (D1, D2, D3) dołączone są kolejno do wejść następnego przerzutnika w szeregu (D2, D3, D4). W dzielniku zacisk wejściowy (RF) dołączony jest jednocześnie do niezanegowanego wejścia pierwszego przerzutnika (D1) oraz poprzez układ odwracający fazę (Ri, Ti) do zanegowanego wejścia pierwszego przerzutnika (D1), a przynajmniej jedno wyjście ostatniego przerzutnika w szeregu (D4) dołączone jest do wyjścia dzielnika. Pomiędzy przynajmniej dwoma kolejnymi przerzutnikami (D1, D2), niezanegowane wyjście poprzedzającego przerzutnika (D1) dołączone jest do niezanegowanego wejścia następującego przerzutnika (D2) poprzez rezystor formujący (Rf1) i dwa inwertery połączone szeregowo (Ri1, Ti1), (Ri3, Ti3), a zanegowane wyjście poprzedzającego przerzutnika (D1) dołączone jest do zanegowanego wejścia następującego przerzutnika (D2) poprzez inny rezystor formujący (Rf2) i dwa inne inwertery połączone szeregowo (Ri2, Ti2), (Ri4, Ti4).The subject of the application is an RFID carrier frequency divider having at least two flip-flops (D1, D2, D3, D4) with differential inputs and differential outputs connected in series so that the outputs of the previous flip-flop in the series (D1, D2, D3) are connected in turn to the inputs of the next flip-flop in the series (D2, D3, D4). In the divider, the input terminal (RF) is connected simultaneously to the non-negated input of the first flip-flop (D1) and via a phase inverting circuit (Ri, Ti) to the negated input of the first flip-flop (D1), and at least one output of the last flip-flop in the series (D4) is connected to the output of the divider. Between at least two successive flip-flops (D1, D2), the non-inverted output of the preceding flip-flop (D1) is connected to the non-inverted input of the following flip-flop (D2) via a forming resistor (Rf1) and two series-connected inverters (Ri1, Ti1), (Ri3, Ti3), and the non-inverted output of the preceding flip-flop (D1) is connected to the non-inverted input of the following flip-flop (D2) via another forming resistor (Rf2) and two other series-connected inverters (Ri2, Ti2), (Ri4, Ti4).
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PL445768A PL248469B1 (en) | 2023-08-05 | 2023-08-05 | RFID carrier frequency divider |
| PCT/IB2024/057516 WO2025032464A1 (en) | 2023-08-05 | 2024-08-02 | Rfid carrier frequency divider and bistable |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PL445768A PL248469B1 (en) | 2023-08-05 | 2023-08-05 | RFID carrier frequency divider |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| PL445768A1 true PL445768A1 (en) | 2024-12-02 |
| PL248469B1 PL248469B1 (en) | 2025-12-15 |
Family
ID=93706916
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PL445768A PL248469B1 (en) | 2023-08-05 | 2023-08-05 | RFID carrier frequency divider |
Country Status (1)
| Country | Link |
|---|---|
| PL (1) | PL248469B1 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| PL156098B1 (en) * | 1988-12-27 | 1992-02-28 | Inst Lacznosci | Programmable frequency divider |
| US20090289671A1 (en) * | 2008-05-21 | 2009-11-26 | Advanced Analog Technology, Inc. | Frequency divider circuit |
| US20110044424A1 (en) * | 2007-10-16 | 2011-02-24 | Austriamicrosystems Ag | Frequency Divider and Method for Frequency Division |
-
2023
- 2023-08-05 PL PL445768A patent/PL248469B1/en unknown
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| PL156098B1 (en) * | 1988-12-27 | 1992-02-28 | Inst Lacznosci | Programmable frequency divider |
| US20110044424A1 (en) * | 2007-10-16 | 2011-02-24 | Austriamicrosystems Ag | Frequency Divider and Method for Frequency Division |
| US20090289671A1 (en) * | 2008-05-21 | 2009-11-26 | Advanced Analog Technology, Inc. | Frequency divider circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| PL248469B1 (en) | 2025-12-15 |
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