CN116032260B - Output pulse width adjustable frequency multiplication circuit and chip - Google Patents
Output pulse width adjustable frequency multiplication circuit and chip Download PDFInfo
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- CN116032260B CN116032260B CN202310317340.6A CN202310317340A CN116032260B CN 116032260 B CN116032260 B CN 116032260B CN 202310317340 A CN202310317340 A CN 202310317340A CN 116032260 B CN116032260 B CN 116032260B
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Abstract
The invention discloses a frequency doubling circuit and a chip with adjustable output pulse width, wherein the frequency doubling circuit comprises: the input end of the buffer is used for receiving input signals, and the first output end and the second output end of the buffer are used for outputting a group of differential clock signals; the input end of the delay adjustable frequency dividing unit is used for receiving the frequency multiplication signal output by the frequency multiplication circuit, and the first output end and the second output end of the delay adjustable frequency dividing unit are used for outputting another group of differential clock signals; the input end of the logic circuit is used for receiving the two groups of differential clock signals, and the output end of the logic circuit outputs a frequency multiplication signal based on logic operation on the two groups of differential clock signals. The frequency doubling circuit and the chip with adjustable output pulse width effectively inhibit the problem of output frequency accuracy caused by mismatch of rising edges and falling edges of input signals, and reduce the influence of the frequency doubling circuit and the chip on linearity in the application of a phase-locked loop system and reference spurious emission under crystal oscillator frequency.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to a frequency multiplier circuit and a chip with adjustable output pulse width.
Background
In a frequency synthesizer or a clock generator in the field of analog integrated circuits, a crystal oscillator frequency with a higher frequency is generally required to improve a loop bandwidth, reduce an influence of in-band noise and reduce an influence of quantization noise of a DSM (delta sigma modulator), but a crystal oscillator with a high output frequency means a higher cost, so that a frequency doubling circuit is adopted to improve an input crystal oscillator frequency, which is a common processing mode. However, a great difficulty is faced here, and on the premise of ensuring that the duty ratio of the frequency-doubled input signal is 50%, the frequency-doubled circuit is also ensured to output an accurate frequency-doubled signal, that is, the fundamental wave and third harmonic components of the crystal oscillator frequency in the frequency-doubled output frequency spectrum are small enough, otherwise, reference spurious components of the system output are increased, the linearity of the system is deteriorated, and the like.
As shown in fig. 1, in the conventional frequency doubling circuit, a processed clock signal with 50% duty cycle is processed by a delay module 101 and then is processed by an exclusive-or logic 102 with the original clock signal with 50% duty cycle to obtain a frequency-doubled clock signal. However, this method cannot effectively cope with the problem of mismatch between the rising edge and the falling edge of the clock signal, so that the frequency accuracy of the output of the frequency doubling circuit is greatly affected, and the system performance is deteriorated.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide a frequency doubling circuit and a chip with adjustable output pulse width, which can effectively solve the problem of mismatch between the rising edge and the falling edge of a crystal oscillator clock signal, thereby greatly improving the frequency precision of the output of the frequency doubling circuit.
To achieve the above object, an embodiment of the present invention provides a frequency multiplier circuit with adjustable output pulse width, which is characterized by comprising: buffer, delay adjustable frequency division unit and logic circuit.
The input end of the buffer is used for receiving an input signal, and the first output end and the second output end of the buffer are used for outputting a group of differential clock signals; the input end of the delay adjustable frequency dividing unit is used for receiving a frequency multiplication signal output by the frequency multiplication circuit, the first output end and the second output end of the delay adjustable frequency dividing unit are used for outputting another group of differential clock signals, and the delay adjustable frequency dividing unit can adjust delay time between the two groups of differential clock signals; the input end of the logic circuit is used for receiving two groups of differential clock signals, and the output end of the logic circuit outputs a frequency multiplication signal based on logic operation on the two groups of differential clock signals.
In one or more embodiments of the present invention, the delay adjustable frequency dividing unit includes an adjustable delay buffer and a frequency divider, an input end of the adjustable delay buffer is used for receiving the frequency multiplication signal, an output end of the adjustable delay buffer is used for outputting the delay signal, an input end of the frequency divider is used for receiving the delay signal, and an output end of the frequency divider is used for outputting a set of corresponding differential clock signals.
In one or more embodiments of the present invention, the logic circuit includes a first nand gate, a second nand gate, and a third nand gate, where a first input terminal and a second input terminal of the first nand gate are respectively configured to receive one single-ended clock signal of the set of differential clock signals and one single-ended clock signal of the other set of differential clock signals, a first input terminal and a second input terminal of the second nand gate are respectively configured to receive the other single-ended clock signal of the set of differential clock signals and the other single-ended clock signal of the other set of differential clock signals, and a first input terminal and a second input terminal of the third nand gate are respectively connected to an output terminal of the first nand gate and an output terminal of the second nand gate, and an output terminal of the third nand gate is configured to output a frequency-doubled signal.
In one or more embodiments of the invention, the adjustable delay buffer comprises a multistage cascaded inverter.
In one or more embodiments of the invention, the frequency divider is a divide-by-two frequency divider.
The invention also discloses a chip comprising the frequency doubling circuit with adjustable output pulse width.
The invention also discloses a chip which comprises a duty ratio calibration circuit, the frequency doubling circuit with adjustable output pulse width and a phase-locked loop which are connected in sequence.
Compared with the prior art, the frequency doubling circuit with adjustable output pulse width outputs a group of differential clock signals through the buffer, so that better matching is realized between the rising edge and the falling edge of the group of differential clock signals; according to the actual crystal oscillator frequency, the output pulse width of the frequency doubling circuit can be adjusted by adjusting the delay adjustable frequency dividing unit. The invention effectively suppresses the problem of output frequency accuracy caused by mismatch of rising edges and falling edges of input signals, and reduces the influence of the output frequency accuracy on linearity in phase-locked loop system application and reference spurious under crystal oscillator frequency.
Drawings
Fig. 1 is a schematic circuit diagram of a frequency doubling circuit according to the prior art.
Fig. 2 is a schematic circuit diagram of a frequency doubling circuit with adjustable output pulse width according to an embodiment of the present invention.
Fig. 3 is a waveform diagram of a frequency multiplier circuit with adjustable output pulse width according to an embodiment of the present invention.
Fig. 4 is a system diagram of a chip according to an embodiment of the invention.
Detailed Description
Specific embodiments of the invention will be described in detail below with reference to the drawings, but it should be understood that the scope of the invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the term "comprise" or variations thereof such as "comprises" or "comprising", etc. will be understood to include the stated element or component without excluding other elements or components.
It should be appreciated that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and/or elements capable of storing instructions for execution by the programmable circuits. When an element or circuit is referred to as being "connected to" or "connected to" another element, or being "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.
The invention will be further described with reference to the drawings and examples.
As shown in fig. 2, a frequency multiplier circuit with adjustable output pulse width includes: buffer 10, delay adjustable frequency dividing unit and logic circuit.
An input of the buffer 10 is for receiving an input signal clkin, and a first output and a second output of the buffer 10 are for outputting a set of differential clock signals clkp, clkn. In the present embodiment, the first output terminal of the buffer 10 is a positive output terminal to output the clock signal clkp, and the second output terminal of the buffer 10 is a negative output terminal to output the clock signal clkn. In other embodiments, the first output of the buffer 10 is a negative output and the second output of the buffer 10 is a positive output.
The single-ended input signal clkin is converted into differential clock signals clkp, clkn by the buffer 10, and as shown in fig. 3, both rising and falling edges of the differential clock signals clkp, clkn can achieve better matching.
The input end of the delay adjustable frequency dividing unit is used for receiving a frequency multiplication signal clkout output by the frequency multiplication circuit, the first output end and the second output end of the delay adjustable frequency dividing unit are used for outputting another group of differential clock signals clk_q and clk_qb, and the delay adjustable frequency dividing unit can adjust the delay time between the two groups of differential clock signals.
In this embodiment, the delay adjustable frequency dividing unit includes an adjustable delay buffer 50 and a frequency divider 60, in this embodiment, the frequency divider 60 is a divide-by-two frequency divider, and in other embodiments, the frequency divider 60 may be a frequency divider with other structures. The input end of the adjustable delay buffer 50 is used for receiving the frequency multiplication signal clkout, the output end of the adjustable delay buffer 50 is used for outputting a delay signal, the input end of the frequency divider 60 is used for receiving the delay signal, and the output end of the frequency divider 60 is used for outputting a group of corresponding differential clock signals clk_q and clk_qb. The adjustable delay buffer 50 may be formed by using a multi-stage cascade inverter, and the delay time of the adjustable delay buffer 50 is adjusted by controlling the number of the inverters. In other embodiments, the adjustable delay buffer 50 may be implemented using a variety of other buffers having delay adjustment functions. In addition, divider 60 may be implemented using other circuits.
In the present embodiment, the frequency multiplication signal clkout outputted from the frequency multiplication circuit passes through a loop formed by the adjustable delay buffer 50 and the frequency divider 60 to generate the differential clock signals clk_q and clk_qb inputted to the logic circuit.
The input end of the logic circuit is used for receiving two groups of differential clock signals clkp, clkn and clkq, clkqb, and the output end of the logic circuit outputs a frequency multiplication signal clkout based on the logic operation of the two groups of differential clock signals clkp, clkn and clkq, clkqb.
In the present embodiment, the logic circuit includes a first nand gate 20, a second nand gate 30, and a third nand gate 40. The first and second inputs of the first nand gate 20 are for receiving a single-ended clock signal of one set of differential clock signals and a single-ended clock signal of the other set of differential clock signals, respectively. The first and second inputs of the second nand gate 30 are for receiving the other single-ended clock signal of the set of differential clock signals and the other single-ended clock signal of the other set of differential clock signals, respectively.
Specifically, the first input terminal of the first nand gate 20 is configured to receive a single-ended clock signal clkp in one set of differential clock signals, and the second input terminal of the first nand gate 20 is configured to receive a single-ended clock signal clk_qb in another set of differential clock signals; the first input of the second nand gate 30 is for receiving a single-ended clock signal clkn of one set of differential clock signals and the second input of the second nand gate 30 is for receiving a single-ended clock signal clk q of another set of differential clock signals. In other embodiments, the first and second inputs of the first nand gate 20 may be swapped and the first and second inputs of the second nand gate 30 may be swapped.
The first input terminal and the second input terminal of the third nand gate 40 are respectively connected to the output terminal of the first nand gate 20 and the output terminal of the second nand gate 30, and the output terminal of the third nand gate 40 is used for outputting the frequency multiplication signal. Specifically, a first input terminal of the third nand gate 40 is connected to the output terminal of the first nand gate 20 to receive the signal clk_a, and a second input terminal of the third nand gate 40 is connected to the output terminal of the second nand gate 30 to receive the signal clk_b. In other embodiments, a first input of the third NAND gate 40 is connected to the output of the second NAND gate 30, and a second input of the third NAND gate 40 is connected to the output of the first NAND gate 20.
Referring to fig. 2 and 3, in the present embodiment, one set of differential clock signals clkp and clkn is nand-processed with another set of differential clock signals clk_q and clk_qb after a delay time Δt, where the delay time Δt mainly includes signal transmission delays of the first nand gate 20, the second nand gate 30, the third nand gate 40, the adjustable delay buffer 50 and the frequency divider 60. If the delay time Δt is exactly equal to one-fourth of the period of the input signal clkin (the period of the input signal clkin is equal to the periods of the differential clock signals clkp and clkn), that is, the delay is 90 ° phase, the duty cycle of the waveforms of the signals clk_a and clk_b output by the first nand gate 20 and the second nand gate 30 is 25% and 75%, respectively, and the signal clk_b is delayed by half the period of the input signal clkin with respect to the signal clk_a, and the signals clk_a and clk_b obtain the frequency doubling signal clkout after passing through the third nand gate 40, and the output pulse width of the signal is equal to the period of the frequency doubling signal clkout (that is, 50% duty cycle).
It should be noted that the adjustable delay buffer 50, i.e. the delay time Δt, can be adjusted according to the output pulse width. Different adjustable delay buffer parameters can be set according to different input frequency ranges, and a sufficiently large delay adjustment range can be designed. In addition, according to the input frequency range of the input signal clkin, the frequency divider 60 may be designed to cover all frequency bands as much as possible, so that a wide range of input frequencies can be satisfied as much as possible. It should be noted that the circuit architecture of the adjustable delay buffer and the divide-by-two divider is not limited under the technical scheme and the working principle according to the present invention, and various circuit architecture implementations can be used.
The invention also discloses a chip comprising the frequency doubling circuit with adjustable output pulse width.
As shown in fig. 4, the invention also discloses a chip, which comprises a duty cycle calibration circuit DCC, the frequency doubling circuit reference clk doubler with adjustable output pulse width and a phase-locked loop PLL which are connected in sequence.
In general, in a PLL application system, under the comprehensive consideration of increasing loop bandwidth, reducing in-band noise, reducing the influence of DSM quantization noise and reducing the use cost of crystal oscillator, the scheme of fig. 4 is generally adopted, that is, the crystal oscillator clock signal fref generates an input signal clkin with 50% duty ratio through the duty ratio calibration circuit DCC, and then transmits the input signal clkin to the frequency doubling circuit reference clk doubler, and then generates an accurate frequency doubling signal clkout, and finally transmits the input signal clkout to the PLL to serve as a frequency doubling input reference clock of the phase discriminator.
In the application, the accurate frequency multiplication signal generated by the frequency multiplication circuit with adjustable output pulse width plays a vital role in increasing loop bandwidth, reducing in-band noise and other phase-locked loop system performances, reduces the influence of the frequency multiplication circuit on the linearity in the phase-locked loop system application and the reference spurious under the crystal oscillator frequency, and simultaneously reduces the use cost of a chip.
The foregoing descriptions of specific exemplary embodiments of the present invention are presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application to thereby enable one skilled in the art to make and utilize the invention in various exemplary embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (6)
1. An output pulse width adjustable frequency multiplier circuit, comprising:
the input end of the buffer is used for receiving an input signal, and the first output end and the second output end of the buffer are used for outputting a group of differential clock signals;
the input end of the delay adjustable frequency dividing unit is used for receiving a frequency multiplication signal output by the frequency multiplication circuit, the first output end and the second output end of the delay adjustable frequency dividing unit are used for outputting another group of differential clock signals, the delay adjustable frequency dividing unit can adjust delay time between the two groups of differential clock signals, the delay adjustable frequency dividing unit comprises an adjustable delay buffer and a frequency divider, the input end of the adjustable delay buffer is used for receiving the frequency multiplication signal, the output end of the adjustable delay buffer is used for outputting the delay signal, the input end of the frequency divider is used for receiving the delay signal, and the output end of the frequency divider is used for outputting a group of corresponding differential clock signals;
and the input end of the logic circuit is used for receiving the two groups of differential clock signals, and the output end of the logic circuit outputs a frequency multiplication signal based on logic operation on the two groups of differential clock signals.
2. The output pulse width adjustable frequency multiplier circuit of claim 1, wherein the logic circuit comprises a first nand gate, a second nand gate, and a third nand gate, wherein the first input terminal and the second input terminal of the first nand gate are respectively configured to receive one single-ended clock signal of the one set of differential clock signals and one single-ended clock signal of the other set of differential clock signals, the first input terminal and the second input terminal of the second nand gate are respectively configured to receive the other single-ended clock signal of the one set of differential clock signals and the other single-ended clock signal of the other set of differential clock signals, the first input terminal and the second input terminal of the third nand gate are respectively connected to the output terminal of the first nand gate and the output terminal of the second nand gate, and the output terminal of the third nand gate is configured to output the frequency multiplied signal.
3. The output pulse width adjustable frequency multiplier circuit of claim 1, wherein the adjustable delay buffer comprises a multistage cascaded inverter.
4. The output pulse width adjustable frequency multiplier circuit of claim 1, wherein the frequency divider is a divide-by-two frequency divider.
5. A chip comprising the frequency multiplier circuit with adjustable output pulse width according to any one of claims 1 to 4.
6. A chip comprising a duty cycle calibration circuit, an output pulse width adjustable frequency multiplier circuit according to any one of claims 1 to 4, and a phase locked loop connected in sequence.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021092601A2 (en) * | 2020-09-25 | 2021-05-14 | Futurewei Technologies, Inc. | Techniques for calibrating 50% duty cycle differential frequency doubler |
| CN215956369U (en) * | 2021-09-29 | 2022-03-04 | 珠海一微半导体股份有限公司 | Low-power-consumption frequency synthesizer |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6737927B2 (en) * | 2001-12-04 | 2004-05-18 | Via Technologies, Inc. | Duty cycle correction circuit for use with frequency synthesizer |
| CN110212915B (en) * | 2019-05-08 | 2023-01-03 | 东南大学 | Coupling type frequency multiplication delay phase-locked loop circuit with uniform split-phase output |
| US11595028B2 (en) * | 2020-06-30 | 2023-02-28 | Qualcomm Incorporated | Frequency doubler with duty cycle correction |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021092601A2 (en) * | 2020-09-25 | 2021-05-14 | Futurewei Technologies, Inc. | Techniques for calibrating 50% duty cycle differential frequency doubler |
| CN215956369U (en) * | 2021-09-29 | 2022-03-04 | 珠海一微半导体股份有限公司 | Low-power-consumption frequency synthesizer |
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