PE20010001A1 - Circuito integrado para la extraccion y adicion de trafico en modo de transferencia asincrono - Google Patents

Circuito integrado para la extraccion y adicion de trafico en modo de transferencia asincrono

Info

Publication number
PE20010001A1
PE20010001A1 PE1999001351A PE00135199A PE20010001A1 PE 20010001 A1 PE20010001 A1 PE 20010001A1 PE 1999001351 A PE1999001351 A PE 1999001351A PE 00135199 A PE00135199 A PE 00135199A PE 20010001 A1 PE20010001 A1 PE 20010001A1
Authority
PE
Peru
Prior art keywords
speed
atm
cells
structured according
traffic
Prior art date
Application number
PE1999001351A
Other languages
English (en)
Inventor
Lareo Jose Luis Conesa
Garcia Juan Carlos Diaz
Fernandez Luis Antonio Merayo
Prieto Jacobo Riesco
Original Assignee
Telefonica Sa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonica Sa filed Critical Telefonica Sa
Publication of PE20010001A1 publication Critical patent/PE20010001A1/es

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L12/5602—Bandwidth control in ATM Networks, e.g. leaky bucket
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5672—Multiplexing, e.g. coding, scrambling

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

DONDE DICHO CIRCUITO ESTA ESTRUCTURADO SEGUN UNA ARQUITECTURA QUE COMPRENDE: a) UNA SECCION DE TRANSPORTE Y PROCESAMIENTO DE CELULAS DE ALTA VELOCIDAD, ESTRUCTURADA SEGUN UN DIAGRAMA DE BLOQUES, QUE COMPRENDE UN BLOQUE RECEPTOR DE ENTRADA QUE CONTROLA LA INTEGRIDAD DE LAS CELULAS QUE RECIBE; b) UNA SECCION DE TRANSPORTE Y PROCESAMIENTO DE CELULAS DE BAJA VELOCIDAD, ESTRUCTURADA SEGUN UN DIAGRAMA DE BLOQUES, QUE COMPRENDE UN MODULO DE COLAS INTERMEDIAS PARA EL ALMACENAMIENTO INTERMEDIO DE DATOS; Y c) UN MODULO DE CONTROL QUE COMPRENDE UN BLOQUE DE CONTROL DE ACCESO AL MEDIO COMUN, ENCARGADO DE ARBITRAR EL ACCESO AL ENLACE DE ALTA VELOCIDAD SI EL CIRCUITO FUNCIONA EN MODO MULTIPLEXOR. ADEMAS ESTE CIRCUITO PERMITE LA INTERCONEXION DE SISTEMAS DE COMUNICACION ATM DE ALTA VELOCIDAD (2.5 Gbit/s), ES CONFIGURABLE EN MODO MULTIPLEXOR PARA ANADIR CANALES DE TRAFICO ATM HASTA (622 Mbit/s) PROCEDENTES DE UNA FUENTE EXTERIOR EN UN FLUJO O ENLACE COMUN ATM DE ALTA VELOCIDAD o EN MODO DEMULTIPLEXOR, EXTRAE CANALES DE TRAFICO ATM DE BAJA VELOCIDAD HACIA UN RECEPTOR EXTERIOR DE UN FLUJO DE TRAFICO DE ALTA VELOCIDAD, Y REALIZA OTRAS FUNCIONES EN AMBOS MODOS COMO MEDIDAS ESTADISTICAS SOBRE LOS FLUJOS ATM PARA DETECTAR CARACTERISTICAS DEL TRAFICO Y PERDIDAS DE INFORMACION, CONTROL DE CALIDAD DE LA TRANSMISION Y GENERACION DE ALARMAS
PE1999001351A 1998-12-30 1999-12-30 Circuito integrado para la extraccion y adicion de trafico en modo de transferencia asincrono PE20010001A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ES009802714A ES2149122B1 (es) 1998-12-30 1998-12-30 Circuito integrado para la extraccion y adicion de trafico en modo de transferencia asincrono.

Publications (1)

Publication Number Publication Date
PE20010001A1 true PE20010001A1 (es) 2001-02-12

Family

ID=8306251

Family Applications (1)

Application Number Title Priority Date Filing Date
PE1999001351A PE20010001A1 (es) 1998-12-30 1999-12-30 Circuito integrado para la extraccion y adicion de trafico en modo de transferencia asincrono

Country Status (5)

Country Link
EP (1) EP1018853A1 (es)
BR (1) BR9907365A (es)
ES (1) ES2149122B1 (es)
GT (1) GT199900230A (es)
PE (1) PE20010001A1 (es)

Also Published As

Publication number Publication date
BR9907365A (pt) 2000-10-10
ES2149122A1 (es) 2000-10-16
EP1018853A1 (en) 2000-07-12
GT199900230A (es) 2001-06-22
ES2149122B1 (es) 2001-05-16

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