NZ338097A - Digitally controlled envelope elimination and restoration phase lock loop radio frequency amplifier - Google Patents

Digitally controlled envelope elimination and restoration phase lock loop radio frequency amplifier

Info

Publication number
NZ338097A
NZ338097A NZ33809799A NZ33809799A NZ338097A NZ 338097 A NZ338097 A NZ 338097A NZ 33809799 A NZ33809799 A NZ 33809799A NZ 33809799 A NZ33809799 A NZ 33809799A NZ 338097 A NZ338097 A NZ 338097A
Authority
NZ
New Zealand
Prior art keywords
phase
information
processor
output signal
signal
Prior art date
Application number
NZ33809799A
Inventor
Stephen Ian Mann
Original Assignee
Tait Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tait Electronics Ltd filed Critical Tait Electronics Ltd
Priority to NZ33809799A priority Critical patent/NZ338097A/en
Priority to AU14195/00A priority patent/AU1419500A/en
Priority to PCT/NZ1999/000207 priority patent/WO2000033464A1/en
Priority to PCT/NZ2000/000189 priority patent/WO2001024356A1/en
Priority to AU79729/00A priority patent/AU782014B2/en
Priority to EP00970330A priority patent/EP1226651A4/en
Priority to CA002385948A priority patent/CA2385948A1/en
Publication of NZ338097A publication Critical patent/NZ338097A/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0261—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the polarisation voltage or current, e.g. gliding Class A
    • H03F1/0266—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the polarisation voltage or current, e.g. gliding Class A by using a signal derived from the input signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
    • H03F1/3247—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits using feedback acting on predistortion circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
    • H03F1/3282—Acting on the phase and the amplitude of the input signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators
    • H03L7/0898—Details of the current generators the source or sink current values being variable
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/102—A non-specified detector of a signal envelope being used in an amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/331—Sigma delta modulation being used in an amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Amplifiers (AREA)
  • Transmitters (AREA)

Abstract

An envelope elimination and restoration amplifier for a radio transmitter includes a digital processor 20 that determines envelope E and phase P information from the RF signal B to be transmitted. A phase locked loop 22 that is controlled by the processor generates a constant amplitude output signal having a phase modulation determined by the phase information, the output signal from the phase locked loop being amplified by the power amplifier 21 to provide the output signal S to the antenna. The amplitude modulation (power output) of the amplifier is modulated in accordance with the derived envelope information E.

Description

NEW ZEALAND PATENTS ACT, 1953 No: Date: COMPLETE SPECIFICATION IMPROVEMENTS RELATING TO EER TRANSMITTERS We, TAIT ELECTRONICS LIMITED, a New Zealand company, of 558 Wairakei Road, Burnside, Christchurch, New Zealand, do hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: INTELLECTUAL PROPERWOFRCFJ OF N.Z. 2 9 SEP 1999 FIELD OF THE INVENTION This invention relates to amplification systems for radio frequency signals and in particular but not solely to envelope elimination and restoration (EER) techniques 5 for radio transmitters. These techniques involve primarily digital rather than analog signal processing and a phase-lock-loop (PLL) arrangement having various aspects of phase modulation and phase adjustment. In one embodiment the PLL involves fractional-N frequency division.
BACKGROUND TO THE INVENTION Mobile communication systems require high frequency power amplifiers for both base station transmitters and portable units carried by users. These amplifiers operate most efficiently at saturation in the non-linear range of their input/output 15 characteristics. Efficiency is important for battery life and weight in the portable units while linearity is important for base stations with multiple carrier transmission. A number of techniques have been developed to compensate for non-linear amplifier operation. Techniques involving modulation feedback from the amplified signal can be divided in two groups depending on how the modulating signal is represented in 20 the baseband. Cartesian amplification systems apply a feedback signal to quadrature components of the modulating signal. Polar loop amplification systems are based on EER techniques with addition of envelope and phase feedback arrangements. The phase feedback forms a PLL although envelope feedback alone may be used.
SUMMARY OF THE INVENTION It is an object of the present invention to provide for improved amplification systems based on EER techniques. In one form the invention implements largely digital rather than analog processing methods to determine envelope and phase information 30 from a modulating signal and provide feedback from the output signal. In another form the invention implements a PLL with phase modulation by way of a fractional-N divider.
Accordingly in one aspect the invention may broadly be said to consist in an amplification system for a radio transmitter comprising: a processor which determines envelope information and phase information from an input signal, a phase-locked-loop which generates a substantially constant amplitude signal having 5 phase modulation determined by the phase information, and an amplifier which generates an output signal from the constant amplitude signal having amplitude modulation determined by the envelope information.
In another aspect the invention may be said to consist in an amplification system for 10 a radio transmitter comprising: a processor which determines envelope information and phase information from an input signal, and a phase-locked-loop controlled by the processor which generates a radio frequency output signal containing the envelope information and the phase information, wherein the phase-locked-loop includes a frequency divider which causes phase modulation of the output signal 15 according to the phase information.
In another aspect the invention may be said to consist in an amplification system for a radio transmitter comprising: a processor which determines envelope information and phase information from an input signal, and a phase-locked-loop controlled by 20 the processor which generates a radio frequency output signal containing the envelope information and the phase information, wherein the phase-locked-loop includes an amplifier which modulates the amplitude of the output signal according to the amplitude information.
In still another aspect the invention may be said to consist in an amplification system for a radio transmitter comprising: a processor which determines envelope information and phase information from an input signal, and a phase-locked-loop controlled by the processor which generates a radio frequency output signal containing the envelope information and the phase information, wherein the 30 processor modifies the envelope information or the phase information according to feedback from the output signal.
BRIEF LIST OF FIGURES Preferred embodiments of the invention will be described with reference to the drawings of which: Figure 1 schematically shows a radio transmitter with amplification of a 10 signal by a polar loop feedback system, Figure 2 shows an amplification system according to the invention, Figure 3 shows a PLL arrangement for use in the system of Figure 2, Figure 4 shows an alternative amplification system according to the invention, Figure 5 shows a PLL arrangement for use in the system of Figure 4, Figure 6 shows a digital envelope feedback arrangement, and Figure 7 shows an analog envelope feedback arrangement.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Referring to the drawings it will appreciated that the invention may be implemented in various forms and that these embodiments are described by way of example only. Details of existing mobile communication systems will also be known to a skilled reader and need not be given here.
Figure 1 shows EER implemented in a traditional polar loop system. An incoming RF signal I is converted by analog block 10 into polar signals 0, r respectively containing phase and envelope information. A phase controlled loop including power amplifier 11 operating in saturation then generates an output signal S 30 according to the information, for transmission by antenna 12. The phase controlled loop forms a PLL which receives signal 0 and provides a constant amplitude signal to the non-linear amplifier. A power supply to the amplifier receives signal r and thereby controls gain of the amplifier to restore envelope information and produce signal S. The PLL includes a phase comparator or detector 13 which compares the phases of signal 0 and feedback from signal S to determine the frequency of a voltage controlled oscillator 14. The oscillator in turn provides the constant amplitude signal to the amplifier. Signal r is also modified by addition in block 15 of feedback from signal S. The feedback arrangement includes an optional frequency downconverter 16 followed alternatively for signals 0, r by an amplitude limiter 16 and envelope detector 17.
Figure 2 shows one embodiment of an amplification system based on EER according to the invention. A digital sub-system or processor arrangement 20, such as a DSP, determines phase and envelope signals P and E from an incoming signal B. A power amplifier 21 generates an output signal S which contains signal B modulated on a radio frequency carrier. A PLL frequency synthesiser 22 containing a frequency divider such as shown in Figure 3 forms a phase modulation path which feeds the amplifier. An envelope modulation path varies the amplifier gain by way of a modulator 23, which may be a power supply to one stage of the amplifier for example. The digital sub-system also preferably determines a phase offset signal O provided to the PLL over an offset adjustment path as described further below. This provides a fine adjustment of the phase of signal S if required to compensate distortion, and also equalises discrepancies between the phase and envelope modulation paths. A feedback arrangement including detection of envelope and/or phase distortion in signal S preferably provides a feedback signal F for the digital sub-system. A detector and ADC system 24 may be implemented in various ways either separately or incorporated partly in the sub-system. An alternative embodiment in which the amplifier forms part of the PLL is described in Figure 4.
Figure 3 shows a PLL arrangement having a frequency divider which could be used in the embodiment of Figure 2. The arrangement produces an output signal having a frequency which is an integer or fractional multiple of a reference signal and which is modulated according to the phase signal P. A voltage controlled oscillator 30 receives a control signal from phase comparator 31 by way of loop filter 32, and produces a constant amplitude output for the amplifier 21. The loop filter generally integrates an output provided by the comparator according to phase differences between a reference signal from frequency reference 33 and a feedback signal from the controlled oscillator. A phase offset may be introduced between the reference and feedback signals by signal O from the digital sub-system 20, according to feedback from amplifier 21. This may control the action of an additional current source or sink at the input to the loop filter, for example. A frequency divider 34 under control of a modulator 35 introduces phase signal P from the digital sub-5 system. The modulator is preferably a sigma-delta arrangement which determines an instantaneous integer value N for the divider in accord with a clock signal from the output of the divider. Signal P forms a digital control word for the modulator.
Figure 4 shows another embodiment of an amplification system based on EER 10 according to the invention. The arrangement is generally similar to that of Figure 2 except that some or all of the stages represented by amplifier 21 and fed by PLL 22 are now included within PLL 40, such as shown in Figure 5. This has an advantage that AM-PM phase errors caused by the amplifier stages are inherently corrected, so that there may be less requirement for a phase adjustment by offset 15 signal O to compensate distortion. The signal may still be required to equalise discrepancies between the phase and envelope modulation paths. Coarse adjustment by a full cycle of the digital sampling period might still be required. On the other hand delay around the loop may be increased with loss of stability and possibly smaller bandwidth. Inclusion of amplification stages introduces additional delay in 20 the loop. The gain and therefore bandwidth must be reduced to maintain stability.
Figure 5 shows a PLL arrangement having a frequency divider which could be used in the embodiment of Figure 4. The arrangement is generally similar to that of Figure 3 except that power amplifier stages 51 being some or all stages of the 25 amplifier 21 in Figure 2, are included in the loop. Envelope information from the digital sub-system 22 is used to modulate the gain of the amplifier stages by way of signal E as before. A limiter 52 is also included to remove the envelope information from signal S before input to the divider 34. The limiter may form part of the input circuitry of the dividers, such as a high gain differential input of the kind found in 30 pre-scalers commonly used in frequency synthesisers.
Figures 6 and 7 show digital and analog systems for obtaining envelope feedback from the power amplifiers 21 or 51 to determine a signal F for the digital sub-system 20. Digital feedback generally requires an envelope detector 60 which may be implemented in many ways. ADC 61 and DAC 62 are also generally required. Typically the amplitude modulator is a switching type to which the digital signal is directly applied. A combination function 65 of the feedback information with envelope information from the incoming signal B may then be used to form signal 5 E for modulation of the amplifier. Analog feedback also requires an envelope detector 70. A combination function 75 of the feedback with the envelope information takes place outside the digital sub-system before formation of signal E.
Further feedback of distortion information may be provided by one or more signals 10 F as shown in Figures 2 and 4, in addition to or instead of phase or envelope feedback. This would enable pre-distortion of the envelope and phase information signals E and P. Processing to determine channel power or bandwidth effects might be used in signal S, for example.

Claims (16)

CLAIMS:
1. An amplification system for a radio transmitter comprising: a processor which determines envelope information and phase information from an input signal, a phase-locked-loop which generates a substantially constant amplitude signal having phase modulation determined by the phase information, and an amplifier which generates an output signal from the constant amplitude signal having amplitude modulation determined by the envelope information.
2. A system according to claim 1 wherein: the phase-locked-loop includes a frequency divider which is modulated according to the phase information.
3. A system according to claim 2 wherein: the frequency divider is modulated by a sigma-delta modulator which is controlled by the processor.
4. A system according to claim 1 wherein: the phase-locked-loop includes a phase comparator in which a phase offset between a reference signal and a feedback signal is adjusted by the processor.
5. A system according to claim 4 wherein: the processor adjusts the phase offset of the comparator according to feedback from the output signal from the amplifier.
6. A system according to claim 1 wherein: the processor modifies the envelope information according to feedback from the output signal from the amplifier.
7. A system according to claim 1 wherein: the processor modifies the phase information according to feedback from the output signal from the amplifier.
8. An amplification system for a radio transmitter comprising: a processor which determines envelope information and phase information from an input signal, and a phase-locked-loop controlled by the processor which generates a radio frequency output signal containing the envelope information and the phase information, wherein the phase-locked-loop includes a frequency divider which causes phase modulation of the output signal according to the phase information.
9. A system according to claim 8 wherein: the phase-locked-loop includes an amplifier which causes amplitude modulation of the output signal according to the envelope information.
10. A system according to claim 8 wherein: the frequency divider includes a digital modulator which operates in response to a control word received from the processor.
11. A system according to claim 8 wherein: the processor predistorts the phase modulation of the output signal according to the envelope information and feedback from the output signal.
12. A system according to claim 11 wherein: the processor predistorts the phase modulation of the output signal by modifying the phase information.
13. A system according to claim 11 wherein: the processor predistorts the phase modulation of the output signal by modifying the phase offset of a phase comparator in the phase-locked-loop.
14. A amplification system for a radio transmitter comprising: a processor which determines envelope information and phase information from an input signal, and - 10- a phase-locked-loop controlled by the processor which generates a radio frequency output signal containing the envelope information and the phase information, wherein the phase-locked-loop includes an amplifier which modulates the amplitude of the output signal according to the envelope information.
15. An amplification system for a radio transmitter comprising: a processor which determines envelope information and phase information from an input signal, and a phase-locked-loop controlled by the processor which generates a radio frequency output signal containing the envelope information and the phase information, wherein the processor modifies the envelope information or the phase information according to feedback from the output signal.
16. An amplification system substantially as herein described with reference to the accompanying drawings excluding Figure 1. By the authorised agents A. J. PARK
NZ33809799A 1998-12-02 1999-09-29 Digitally controlled envelope elimination and restoration phase lock loop radio frequency amplifier NZ338097A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
NZ33809799A NZ338097A (en) 1999-09-29 1999-09-29 Digitally controlled envelope elimination and restoration phase lock loop radio frequency amplifier
AU14195/00A AU1419500A (en) 1998-12-02 1999-12-02 Improvements relating to phase lock loops
PCT/NZ1999/000207 WO2000033464A1 (en) 1998-12-02 1999-12-02 Improvements relating to phase lock loops
PCT/NZ2000/000189 WO2001024356A1 (en) 1999-09-29 2000-09-29 Improvements relating to eer transmitters
AU79729/00A AU782014B2 (en) 1999-09-29 2000-09-29 Improvements relating to EER transmitters
EP00970330A EP1226651A4 (en) 1999-09-29 2000-09-29 Improvements relating to eer transmitters
CA002385948A CA2385948A1 (en) 1999-09-29 2000-09-29 Improvements relating to eer transmitters

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NZ33809799A NZ338097A (en) 1999-09-29 1999-09-29 Digitally controlled envelope elimination and restoration phase lock loop radio frequency amplifier

Publications (1)

Publication Number Publication Date
NZ338097A true NZ338097A (en) 2001-05-25

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Family Applications (1)

Application Number Title Priority Date Filing Date
NZ33809799A NZ338097A (en) 1998-12-02 1999-09-29 Digitally controlled envelope elimination and restoration phase lock loop radio frequency amplifier

Country Status (5)

Country Link
EP (1) EP1226651A4 (en)
AU (1) AU782014B2 (en)
CA (1) CA2385948A1 (en)
NZ (1) NZ338097A (en)
WO (1) WO2001024356A1 (en)

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US7386287B2 (en) 2001-07-03 2008-06-10 Siemens Aktiengesellschaft Method for controlling the gain of radio-frequency signal
DE10212569A1 (en) * 2002-03-12 2003-09-25 Deutsche Telekom Ag Procedure for transmitter amplifiers for mobile radio
US6646501B1 (en) 2002-06-25 2003-11-11 Nortel Networks Limited Power amplifier configuration
DE10230919B4 (en) 2002-07-09 2018-08-02 Rohde & Schwarz Gmbh & Co. Kg Radio frequency transmitter and method for efficiency-optimized operation of the radio-frequency transmitter
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EP1499011A1 (en) 2003-07-18 2005-01-19 Stichting Voor De Technische Wetenschappen Amplifying circuit comprising an envelope modulated limit cycles modulator circuit
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DE102004054586B4 (en) * 2004-11-11 2010-10-21 Palm, Inc. (n.d.Ges. d. Staates Delaware), Sunnyvale Method and device for amplifying an amplitude and phase modulated electrical signal
US7881683B2 (en) * 2004-12-21 2011-02-01 Telefonaktiebolaget Lm Ericsson (Publ) Generation of modulated radio frequency signals
US7403750B2 (en) * 2005-04-25 2008-07-22 Nokia Corporation Reuse of digital-to-analog converters in a multi-mode transmitter
WO2007144806A2 (en) * 2006-06-12 2007-12-21 Nxp B.V. Polar signal generator
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US8890528B2 (en) * 2009-09-18 2014-11-18 Analogic Corporation RF power transmitter
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Also Published As

Publication number Publication date
WO2001024356A1 (en) 2001-04-05
AU7972900A (en) 2001-04-30
EP1226651A4 (en) 2003-04-23
AU782014B2 (en) 2005-06-30
CA2385948A1 (en) 2001-04-05
EP1226651A1 (en) 2002-07-31

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Free format text: THE OWNER HAS BEEN CORRECTED TO 121164, TAIT LIMITED, 558 WAIRAKEI ROAD, BURNSIDE, CHRISTCHURCH 8053, NZ

Effective date: 20140528