NZ260962A

NZ260962A - Watchdog timer circuit and reset method for telephone subset microprocessor

Info

Publication number: NZ260962A
Application number: NZ26096294A
Authority: NZ
Inventors: Spiro Petratos; Murray David Wild
Original assignee: Alcatel Australia
Priority date: 1993-07-28
Filing date: 1994-07-08
Publication date: 1996-11-26
Also published as: BE1009037A3; GB9414749D0; GB2280568A

Description

<div class="application article clearfix" id="description"> 2 6 PATENTS ACT 1953 COMPLETE SPECIFICATION " WATCHDOG TIMER CIRCUIT FOR TELEPHONE SUBSET " WE, ALCATEL AUSTRALIA LIMITED, Oao 3(^3) A Company of the Stata of New South Wales, of 280 Botany Road, Alexandria, New South Wales, 2015, Australia, hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: 1 26 0 f This invention relates to a circuit arrangement for providing a reset signal to a microprocessor associated with a telephone subset, when the microprocessor becomes latched in an undefined state. This state can be brought about by, for example, electrical interference or an event inconsistent with the normal operation of the microprocessors software. Such circuits, generally referred to as watchdog timer circuits, are known and are arranged to reset the microprocessor when it fails to provide a service signal at predetermined regular intervals, which would occur when the microprocessor becomes latched. In telephone subsets incorporating microprocessors, because of strict on-hook power limitations known watchdog timers will only provide a reset signal to the microprocessor under certain conditions, viz. an initial power-up, when in the off-hook mode, and when a partially discharged dry cell used to provide power to the microprocessor in the on-hook mode is replaced by a fully charged dry cell. At all other times the circuit is prevented from transmitting a reset pulse to the microprocessor which, during this time, is in a state where it draws minimal current and has no need of, nor does it provide, service pulses. Modern computer controlled exchanges are capable of offering a number of exchange-based facilities. A subscriber wishing to access these facilities requires a telephone subset having a microprocessor to decode signals relating to facilities being provided. Some facilities, such as, for 2 example, "calling line identification", require the microprocessor to decode signals when the subset is on-hook. Furthermore, subset-based facilities such as, for example, "Time-of-day" display; "hands-free mode"; "redial mode" and "liquid crystal display contrast control" require the microprocessor to be running while the subset is in the on-hook mode. It is an object of the present invention to provide a watchdog timer circuit arrangement for use in a telephone subset having a microprocessor, the timer functioning in both the on-hook and off-hook modes. According to the invention there is provided a telephone subset arrangement including a processor means for use in association with a telephone exchange having one or more subscriber controlled facilities, said processor means including a service signal pulse output means, a method of providing a reset signal to said processor means when said processor means fails to generate a regular service signal pulse, said method comprising the steps of: (A) providing a gate means having a first input, a second input and an output, said output presenting either a first voltage state or a second voltage state depending upon voltage states applied to said inputs, said first input being coupled to said service signal pulse output means; (B) providing a controllable semiconductor switch means whose control element is coupled to said output of the gate means, and a switching path of which is arranged such that it is rendered conducting when said first 260 Po2 voltage state is present at the output of said gate means, and non-conducting when said second voltage is present at the output of the gate means; (C) providing a reset signal circuit means including a reset signal source and said switching path of the said switch means, said reset signal circuit means coupling said reset signal source to reset input means of said processor means and to said second input of the gate when said switch means is rendered conducting; (D) apply a clock signal pulse simultaneously to an input means of said processor means which input means is associated with said processor means' service signal pulse generation, and to said first input of said &jte means to cause a first voltage state to be present thereat for rendering said switch means conducting; (E) delay rendering said switch means conducting for a predetermined period by delay means; whereby if said regular service signal pulse is not generated within said predetermined period said switch means is rendered conducting thereby extending a reset signal to said reset input of the processor means and to said second input of the gate means to cause the first voltage state to present at said output of the gate means to change to the second voltage state and render said switch means non-conducting thereby disconnecting said reset signal, and whereby if said regular service signal is generated within said predetermined period said service signal pulse causes the first 26 0 &{< •> voltage state present at said output of the gate means to change to the second voltage state preventing the delayed rendering conducting of the said switch means. According to a further aspect of the present invention there is provided a telephone subset arrangement including a processor means for use in association with a telephone exchange having one or more subscriber controlled facilities, said processor means including a service signal pulse output means, an arrangement comprising a gate means having a first input, a second input and an output, said output presenting either a first voltage state or a second voltage state depending upon voltage states applied to said inputs, said first input being coupled to said service signal pulse output means, a controllable semiconductor switch means whose control element is coupled to said output of the gate means, and a switching path of which is arranged such that it is rendered conducting when said first voltage state is present at the output of said gate means, and non-conducting when said second voltage is present at the output of the gate means, a reset signal circuit means including a reset signal source and said switching path of said switch means, said reset signal circuit means coupling said reset signal source to reset input means of said processor means and to said second input of the gate when said switch means is rendered conducting, a clock means for providing a clock signal pulse coupled to both an input means of said processor means which input means is associated with said processor means' 5 26 0 S? service signal pulse generation, and to said first input of said gate means for causing a first voltage stat to be present thereat and rendering said switch means conducting, a delay means for delaying, for a predetermined period, the rendering of said switch means conducting, whereby if said regular service signal pulse is not generated within said predetermined period said switch means is rendered conducting thereby extending a reset signal to said reset input of the processor means and to said second input of the gate means to cause the first voltage state to present at said output of the gate means to change to the second voltage state and render said switch means non-conducting thereby disconnecting said reset signal, and whereby if said regular service signal is generated within said predetermined period said service signal pulse causes the first voltage state present at said output of the gate means to change to the second voltage state preventing the delayed rendering conducting of the said switch means. In order that the invention may be readily carried into effect, an embodiment thereof will now be described in relation to the accompanying drawings, in which: Figure 1 is a schematic representation of a telephone subset incorporating a processor and the watchdog timer of the present invention. Figure 2 is a schematic circuit of the watchdog timer of the present invention. Referring to Figure 1, the subset arrangement comprises a line switch 1 260 £ controlled by a processor 2; a power extraction circuit 4 for providing power to the arrangement; a keypad 5 coupled to processor 2; the subset's switch-hook 6 coupled to processor 2; a tone caller 7 coupled to the exchange line; an 12C bus connected to the processor's 12C serial interface 9; to the 12C bus is coupled a first RAM memory 10, a liquid crystal display means 11, a DTMF (dual tone multifrequency) generator 12; a second memory ROM 15 is coupled to processor 2. RAM 10 contains input data which can be changed by selecting appropriate functions; ROM 15 stores operating instructions which can be called up by processor 2 in response to instructions; a watchdog timer 16 coupled to processor 2 and a real time clock 17 coupled to said processor providing a clock signal every minute. Referring to Figure 2, the watchdog timer 17 comprises a service signal input A coupled to input "I" of a NOR gate G1, via a filter arrangement comprising capacitor C1, diode D1 and resistor R1. The filter arrangement filters out any DC component which may be present in the service signal from the microprocessor 2; a gate latching circuit comprising an NPN transistor TR1, resistor R2 and resistors R3 and R4; a time constant circuit coupled to output "3" of gate G1 comprising resistors R5, R6, and capacitor C2; a capacitor discharge circuit comprising resistor R6, diode D2, resistors R3 and R4; a controllable reset circuit comprising NPN transistor TR2, PNP transistor TR3 and resistors R7, R8, R9, R10, R11 and R12 and a reset signal output B; and a clock signal input C coupled to transistor TR1's base element via an 16 n f "■ inverting stage comprising PNP transistor TR4, resistors R, R13, R14, R15, R16 and capacitor C3. The clock signal is also extended to the microprocessor's interrupt line (INT) via output E. A voltage monitor input D is coupled to the base element of transistor TR1 via a coupling capacitor C4. In operation, with the subset in either the on-hook or off-hook mode, the clock delivers a periodic pulse, typically every minute, into input C and to output E. Each time this pulse is received at input C and output E, on the one hand the microprocessor senses the application of the pulse and prepares to respond, if it is functioning normally, with a » vice signal within typically 5-30 m/s, depending on its processing status; and on the other hand transistor TR4 turns on and an inverted voltage pulse at the collector of transistor TR4 is extended via capacitor C3 to the base of transistor TR1 which turns on thereby pulling input 1 of gate G1 LOW. This causes output 3 of gate G1 to go HIGH whereupon it becomes latched because output 3 is coupled to the base of transistor TR1. Capacitor C2 begins to charge towards V+ via R16, collector/base junction of transistor TR1, resistor R3, and the time constant circuit comprising resistors R5, R6, R7 and R8. The time constant circuit introduces a predetermined delay, typically 50 m/s, in charging capacitor C2. During the time capacitor C2 is charging, a reset signal is pending and the microprocessor must send a service signal into input A to cancel this pending reset. 8 £ h i. If the microprocessor becomes latched in an undefined state for any reason and fails to send the service signal wit! /in the period that capacitor C3 is charging the voltage on capacitor C2 eventually reaches 0.6 x (RB + R7)/R8 of a volt and transistor TR2 turns on which consequently turns or, transistor TR3. Because transistor TR3 is now conducting a HIGH condition applies at reset output B which is extended to microprocessor 2 to reset the microprocessor in the conventional way. At the same time, this HIGH condition is extended to input 2 of gate G1 thereby causing a LOW condition at output 3 of gate G1. Capacitor C2 now begins to discharge via resistor R6, diode D2, resistor R3 and resistor R4 to ground. When the voltage on capacitor C2 falls below 0.6 x (R8 + R7)/R8 of a volt, transistor TR2 turns off turning off transistor TR3. A LOW condition now applies at reset output B and the reset signal condition extended to the microprocessor is removed. On the other hand, if during the period capacitor C2 is charging and the reset signal is pending a service signal arrives at input A, input 1 of gate G1 is pulled HIGH causing output 3 to go LOW turning off transistor TR1 and discharging capacitor C2 as described above. Referring to the voltage monitor input D, while the subset's supply voltage is below a predetermined level the voltage monitor (not shown) disables the timer circuit and no reset signals are generated. When the supply voltage reaches an operating level, such as when it is first powered 9 (*"l /«i ,r\ & v u y 6 up, or when aged dry cells are replaced, the voltage monitor produces a HIGH condition on input D which turns on transistor TR1 and generates a reset signal as described above. Referring to hook-switch signal input F, each time the subset goes off-hook a LOW condition is produced at input F which generates a LOW condition at input 1 of gate G1 and generates a reset signal as described above. While the present invention has been described with regard to many particulars, it is understood that equivalents may be readily substituted without departing from the scope of the invention. 10 </div>

Claims

<div class="application article clearfix printTableText" id="claims"> £6 0r: - What we claim is:

1. In a telephone subset arrangement including a processor means for use in association with a telephone exchange having one or more subscriber controlled facilities, said processor means including a service signal pulse output means, a method of providing a reset signal to said processor means when said processor means fails to generate a regular service signal pulse, said method comprising the steps of: (A) providing a gate means having a first input, a second input and an output, said output presenting either a first voltage state or a second voltage state depending upon voltage states applied to said inputs, said first input being coupled to said service signal pulse output means; (B) providing a controllable semiconductor switch means whose control element is coupled to said output of the gate means, and a switching path of which is arranged such that it is rendered conducting when said first voltage state is present at the output of said gate means, and non-conducting when said second voltage is present at the output of the gate means; (C) providing a reset signal circuit means including a reset signal source and said switching path of the said switch means, said reset signal circuit means coupling said reset signal source to reset input means of said processor means and to said second input of the gate when said switch means is rendered conducting; (D) apply a clock signal pulse simultaneously to an input means of said 11 processor means which input means is associated with said processor means' service signal pulse generation, and to said first input of said gate means to cause a first voltage state to be present thereat for rendering said switch means conducting; (E) delay rendering said switch means conducting for a predetermined period by delay means; whereby if said regular service signal pulse is not generated within said predetermined period said switch means is rendered conducting thereby extending a reset signal to said reset input of the processor means and to said second input of the gate means to cause the first voltage state to present at said output of the gate means to change to the second voltage state and render said switch means non-conducting thereby disconnecting said reset signal, and whereby if said regular service signal is generated within said predetermined period said service signal pulse causes the first voltage state present at said output of the gate means to change to the second voltage state preventing the delayed rendering conducting of the said switch means.

2. A method as claimed in claim 1, wherein step D includes a further step of latching the gate means when the voltage state on the said gate means output is the first voltage state.

3. In a telephone subset arrangement including a processor means for use in association with a telephone exchange having one or more subscriber 12 controlled facilities, said processor means including a service signal pulse output means, an arrangement comprising a gate means having a first input, a second input and an output, said output presenting either a first voltage state or a second voltage state depending upon voltage states applied to said inputs, said first input being coupled to said service signal pulse output means, a controllable semiconductor switch means whose control element is coupled to said output of the gate means, and a switching path of which is arranged such that it is rendered conducting when said first voltage state is present at the output of said gate means, and non-conducting when said second voltage is present at the output of the gate means, a reset signal circuit means including a reset signal source and said switching path of said switch means, said reset signal circuit means coupling said reset signal source to reset input means of said processor means and to said second input of the gate when said switch means is rendered conducting, a clock means for providing a clock signal pulse coupled to both an input means of said processor means which input means is associated with said processor means' service signal pulse generation, and to said first input of said gate means for causing a first voltage stat to be present thereat and rendering said switch means conducting, a delay means for delaying, for a predetermined period, the rendering of said switch means conducting, whereby if said regular service signal pulse is not generated within said predetermined period said switch means is rendered conducting thereby extending a reset signal to said 13 260 r reset input of the processor means and to said second input of the gate means to cause the first voltage state to present at said output of the gate means to change to the second voltage state and render said switch means non-conducting thereby disconnecting said reset signal, and whereby if said regular service signal is generated within said predetermined period said service signal pulse causes the first voltage state present at said output of the gate means to change to the second voltage state preventing the delayed rendering conducting of the said switch means.

4. An arrangement as claimed in claim 3, including a latch means arranged to latch the gate means when the voltage state at the output of the gate means is the first voltage state.

5. An arrangement as claimed in claim 4, wherein said latch means comprises a second controllable semiconductor switch means whose control element is coupled to said output of the gate means and a switching path of which is coupled to said first input of said gate means, whereby when said first voltage state is present at said output of the gate means the switching path of said second controllable semiconductor switch applies a voltage state to said first input which maintains said first voltage state at said output of the gate.

6. An arrangement as claimed in any one of claims 3 to 5, wherein said output of said gate means is coupled to the control element of said first controllable semiconductor switch means via a time constant means whereby 14 26 0 c said first controllable semiconductor switch means is rendered conducting only after a period determined by said time constant means' elements.

7. An arrangement as claimed in claim 6, wherein said time constant means elements comprise an RC network arranged to introduce a delay of approximately 50 ms.

8. An arrangement as claimed in claim 7, including a discharge circuit to discharge the RC networks capacitor means when a second voltage state is present at the said output of the gate means.

9. An arrangement as claimed in any one of claims 5 to 8, including an inverting stage arranged to couple said clock signal pulse to said control element of the second controllable semiconductor switch means to provide said clock pulse with an appropriate logic sense.

10. An arrangement as claimed in any one of claims 3 to 9, including a hook-switch signal input means coupled to said first input of the gate means whereby upon said subset arrangement being brought into an off-hook mode a voltage state is applied to said first input such that the voltage state of the said output of the gate means changes from the second voltage state to the first voltage state to extend a reset signal to said reset input of the processor means and the next signal circuit.

11. An arrangement as claimed in any one of claims 5 to 10, including a voltage monitor input means coupled to the said output of the gate means, whereby upon the subset arrangement's supply voltage reaches a 15 260 96 2 predetermined voltage level a voltage monitor signal is produced at said voltage monitor input means such that a first voltage state is produced at the said output of the gate means thereby rendering said first switch means conducting to extend a reset signal to said reset input of said processor means.

12. An arrangement as claimed in any one of claims 3 to 11, wherein the pulse rate of said clock signal pulse is one pulse per minute.

13. An arrangement substantially as herein described with reference to Figures 1 to 2 of the accompanying drawings. ALCATEL AUSTRALIA LIMITED P.M. Conrick Authorized Agent P5/1/1703 16 </div>