GB2280568A - Timer circuit and method in or for a telephone subset - Google Patents
Timer circuit and method in or for a telephone subset Download PDFInfo
- Publication number
- GB2280568A GB2280568A GB9414749A GB9414749A GB2280568A GB 2280568 A GB2280568 A GB 2280568A GB 9414749 A GB9414749 A GB 9414749A GB 9414749 A GB9414749 A GB 9414749A GB 2280568 A GB2280568 A GB 2280568A
- Authority
- GB
- United Kingdom
- Prior art keywords
- input
- output
- gate
- voltage state
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M1/00—Substation equipment, e.g. for use by subscribers
- H04M1/738—Interface circuits for coupling substations to external telephone lines
- H04M1/7385—Programmable or microprocessor-controlled
Abstract
In a watchdog timer circuit in or for a telephone subset arrangement including a processor, for use in association with a telephone exchange having facilities which the subset decodes while the subset is in an on-hook mode, a regular clock signal is applied to an input (1) of the gate (G1) and to an input (INT) of the microprocessor. A voltage state at the output (1) of the gate (G1) causes a pending reset condition in which the time constant circuit (C2, R5, R6) introduces a delay of a predetermined period which is less than clock signal period to the operation of semiconductor switch (TR2, TR3). If the microprocessor is functioning correctly a service signal, triggered by the clock signal, is delivered to input A within the predetermined period of the delay and a reset signal is not sent. <IMAGE>
Description
TIMER CIRCUIT AND METHOD IN OR FOR A TELEPHONE SUBSET
This invention relates to a circuit arrangement and method for providing a reset signal to a microprocessor associated with a telephone subset, when the microprocessor becomes latched in an undefined state. This state can be brought about by, for example, electrical interference or an event inconsistent with the normal operation of the microprocessor's software.
Such circuits, generally referred to as watchdog timer circuits, are known and are arranged to reset the microprocessor when it fails to provide a service signal at predetermined regular intervals, which would occur when the microprocessor becomes latched.
In telephone subsets incorporating microprocessors, because of strict onhook power limitations known watchdog timers will only provide a reset signal to the microprocessor under certain conditions, viz. an initial power-up, when in the offhook mode, and when a partially discharged dry cell used to provide power to the microprocessor in the on-hook mode is replaced by a fully charged dry cell. At all other times the circuit is prevented from transmitting a reset pulse to the microprocessor which, during this time, is in a state where it draws minimal current and has no need of, nor does it provide, service pulses.
Modern computer controlled exchanges are capable of offering a number of exchange-based facilities. A subscriber wishing to access these facilities requires a telephone subset having a microprocessor to decode signals relating to facilities being provided. Some facilities, such as, for example, "calling line identification", require the microprocessor to decode signals when the subset is on-hook. Furthermore, subsetbased facilities such as, for example, "Time-of-day" display; "hands-free mode"; "redial mode" and "liquid crystal display contrast control" require the microprocessor to be running while the subset is in the on-hook mode.
It is an object of the present invention to provide a watchdog timer circuit arrangement for use in a telephone subset having a microprocessor, the timer functioning in both the on-hook and off-hook modes.
According to the invention there is provided a telephone subset arrangement including a processor means for use in association with a telephone exchange having one or more subscriber controlled facilities, the processor means including a service signal pulse output means, a method of providing a reset signal to the processor means when the processor means fails to generate a regular service signal pulse, the method comprising the steps of
(A) providing a gate means having a first input, a second input and an output, the output presenting either a first voltage state or a second voltage state depending upon voltage states applied to the inputs, the first input being coupled to the service signal pulse output means,
(B) providing a controllable semiconductor switch means whose control element is coupled to the output of the gate means, and a switching path of which is arranged such that it is rendered conducting when the first voltage state is present at the output of the gate means, and non-conducting when the second voltage is present at the output of the gate means,
(C) providing a reset signal circuit means including a reset signal source and the switching path of the switch means, the reset signal circuit means coupling the reset signal source to reset input means of the processor means and to the second input of the gate when the switch means is rendered conducting,
(D) apply a clock signal pulse simultaneously to an input means of the processor means which input means is associated with the processor means' service signal pulse generation, and to the first input of the gate means to cause a first voltage state to be present thereat for rendering the switch means conducting,
(E) delay rendering the switch means conducting for a predetermined period by delay means, whereby, if the regular service signal pulse is not generated within the predetermined period the switch means is rendered conducting thereby extending a reset signal to the reset input of the processor means and to the second input of the gate means to cause the first voltage state to present at the output of the gate means to change to the second voltage state and render the switch means non-conducting thereby disconnecting the reset signal, and whereby if the regular service signal is generated within the predetermined period, the service signal pulse causes the first voltage state present at the output of the gate means to change to the second voltage state preventing the delay and rendering conducting the switch means.
According to a further aspect of the present invention there is provided a telephone subset arrangement including a processor means for use in association with a telephone exchange having one or more subscriber controlled facilities, the processor means including a service signal pulse output means, an arrangement comprising a gate means having a first input, a second input and an output, the output presenting either a first voltage state or a second voltage state depending upon voltage states applied to the inputs, the first input being coupled to the service signal pulse output means, a controllable semiconductor switch means whose control element is coupled to the output of the gate means, and a switching path of which is arranged such that it is rendered conducting when the first voltage state is present at the output of the gate means, and non-conducting when the second voltage is present at the output of the gate means, a reset signal circuit means including a reset signal source and the switching path of the switch means, the reset signal circuit means coupling the reset signal source to reset input means of the processor means and to the second input of the gate when the switch means is rendered conducting, a clock means for providing a clock signal pulse coupled to both an input means of the processor means which input means is associated with the processor means' service signal pulse generation, and to the first input of the gate means for causing a first voltage state to be present thereat and rendering the switch means conducting, a delay means for delaying, for a predetermined period, the rendering of the switch means conducting, whereby if the regular service signal pulse is not generated within the predetermined period, the switch means is rendered conducting thereby extending a reset signal to the reset input of the processor means and to the second input of the gate means to cause the first voltage state to present at the output of the gate means to change to the second voltage state and render the switch means non-conducting thereby disconnecting the reset signal, and whereby if the regular service signal is generated within the predetermined period the service signal pulse causes the first voltage state present at the output of the gate means to change to the second voltage state preventing the delayed rendering the switch means conducting.
In order that the invention and its various other preferred features may be understood more easily, an embodiment thereof will now be described, by way of example only, with reference to the accompanying drawings, in which:
Figure 1 is a schematic representation of a telephone subset incorporating a processor and watchdog timer e.g. in accordance with the present invention, and
Figure 2 is a schematic circuit of the watchdog timer.
Referring to Figure 1, the subset arrangement comprises a line switch 1 controlled by a processor 2, a power extraction circuit 4 for providing power to the arrangement. a keypad 5 coupled to processor 2, the subset's switch-hook 6 coupled to processor 2, a tone caller 7 coupled to an exchange line, an 12C bus connected to the processor's 12C serial interface 9; -to the 12C bus is coupled a first RAM memory 10, a liquid crystal display 11, a DTMF (dual tone multifrequency) generator 12, a second memory formed by ROM 15 is coupled to processor 2. RAM 10 contains input data which can be changed by selecting appropriate functions. ROM 15 stores operating instructions which can be called up by processor 2 in response to instructions. A watchdog timer 16 is coupled to processor 2 and a real time clock 17 is coupled to the processor providing a clock signal every minute.
Referring to Figure 2, the watchdog timer 16 comprises a service signal input A coupled to input "1" of a NOR gate G1, via a filter arrangement comprising capacitor Cl, diode D1 and resistor R1. The filter arrangement filters out any DC component which may be present in the service signal from the microprocessor 2.
A gate latching circuit comprises an NPN transistor TR1, resistor R2 and resistors R3 and R4. A time constant circuit is coupled to output "3" of gate G1 and comprises resistors R5, R6, and capacitor C2. A capacitor discharge circuit comprises resistor R6, diode
D2, resistors R3 and R4. A controllable reset circuit comprising NPN transistor TR2, PNP transistor TR3 and resistors R7, R8, R9, R10, R11 and R12. A reset signal output B is provided and a clock signal input C coupled to transistor TR1's base element via an inverting stage comprising PNP transistor TR4, resistors R13, R14, R15, R16 and capacitor C3. The clock signal is also extended to the microprocessor's interrupt line (INT) via output
E.A voltage monitor input D is coupled to the base element of transistor TR1 via a coupling capacitor C4.
In operation, with the subset in either the onhook or off-hook mode, the clock delivers a periodic pulse, typically every minute, into input C and to output E. Each time this pulse is received at input C, and output E, on the one hand the microprocessor senses the application of the pulse and prepares to respond, if it is functioning normally, with a service signal within typically 5-30 m/s, depending on its processing status; and on the other hand transistor TR4 turns on and an inverted voltage pulse at the collector of transistor
TR4 is coupled via capacitor C3 to the base of transistor TR1 which turns on thereby pulling input 1 of gate G1 LOW. This causes output 3 of gate G1 to go HIGH whereupon it becomes latched because output 3 is coupled to the base of transistor TR1.
Capacitor C2 begins to charge towards V+ via R16, collector/base junction of transistor TR1, resistor R3, and the time constant circuit comprising resistors R5,
R6, R7 and R8. The time constant circuit introduces a predetermined delay, typically 50 m/s, in charging capacitor C2. During the time capacitor C2 is charging, a reset signal is pending and the microprocessor must send a service signal into input A to cancel this pending reset.
If the microprocessor becomes latched in an undefined state for any reason and fails to send the service signal within the period that capacitor C2 is charging the voltage on capacitor C2 eventually reaches 0.6 x (R8 t R7)/R8 of a volt and transistor TR2 turns on which consequently turns on transistor TR3. Because transistor TR3 is now conducting a HIGH condition applies at reset output B which is extended to microprocessor 2 to reset the microprocessor in the conventional way. At the same time, this HIGH condition is extended to input 2 of gate G1 thereby causing a LOW condition at output 3 of gate G1. Capacitor C2 now begins to discharge via resistor R6, diode D2, resistor
R3 and resistor R4 to ground.When the voltage on capacitor C2 falls below 0.6 x (R8 + R7)/R8 of a volt, transistor TR2 turns off turning off transistor TR3. A
LOW condition now applies at reset output B and the reset signal condition extended to the microprocessor is removed.
On the other hand, if during the period capacitor
C2 is charging and the reset signal is pending a service signal arrives at input A, input 1 of gate G1 is pulled
HIGH causing output 3 to go LOW turning off transistor
TR1 and discharging capacitor C2 as described above.
Referring to the voltage monitor input D, while the subset's supply voltage is below a predetermined level the voltage monitor (not shown) disables the timer circuit and no reset signals are generated. When the supply voltage reaches an operating level, such as when it is first powered up, or when aged dry cells are replaced, the voltage monitor produces a HIGH condition on input D which turns on transistor TR1 and generates a reset signal as described above.
Referring to hook-switch signal input F, each time the subset goes offhook a LOW condition is produced at input F which generates a LOW condition at input 1 of gate G1 and generates a reset signal as described above.
Claims (13)
1. In a telephone subset arrangement including a processor means for use in association with a telephone exchange having one or more subscriber controlled facilities, the processor means including a service signal pulse output means, a method of providing a reset signal to the processor means when the processor means fails to generate a regular service signal pulse, the method comprising the steps of::
(A) providing a gate means having a first input, a second input and an output, the output presenting either a first voltage state or a second voltage state depending upon voltage states applied to the inputs, the first input being coupled to the service signal pulse output means,
(B) providing a controllable semiconductor switch means whose control element is coupled to the output of the gate means, and a switching path of which is arranged such that it is rendered conducting when the first voltage state is present at the output of the gate means, and non-conducting when the second voltage is present at the output of the gate means,
(C) providing a reset signal circuit means including a reset signal source and the switching path of the switch means, the reset signal circuit means coupling the reset signal source to reset input means of the processor means and to the second input of the gate when the switch means is rendered conducting,
(D) apply a clock signal pulse simultaneously to an input means of the processor means which input means is associated with the processor means' service signal pulse generation, and to the first input of the gate means to cause a first voltage state to be present thereat for rendering the switch means conducting,
(E) delay rendering the switch means conducting for a predetermined period by delay means, whereby, if the regular service signal pulse is not generated within the predetermined period the switch means is rendered conducting thereby extending a reset signal to the reset input of the processor means and to the second input of the gate means to cause the first voltage state to present at the output of the gate means to change to the second voltage state and render the switch means non-conducting thereby disconnecting the reset signal, and whereby if the regular service signal is generated within the predetermined period, the service signal pulse causes the first voltage state present at the output of the gate means to change to the second voltage state preventing the delay and rendering conducting the switch means.
2. A method as claimed in claim 1, wherein step
D includes a further step of latching the gate means when the voltage state on the gate means output is the first voltage state.
3. In or for a telephone subset arrangement including a processor means for use in association with a telephone exchange having one or more subscriber controlled facilities, the processor means including a service signal pulse output means, an arrangement comprising a gate means having a first input, a second input and an output, the output presenting either a first voltage state or a second voltage state depending upon voltage states applied to the inputs, the first input being coupled to the service signal pulse output means, a controllable semiconductor switch means whose control element is coupled to the output of the gate means, and a switching path of which is arranged such that it is rendered conducting when the first voltage state is present at the output of 20 the gate means, and non-conducting when the second voltage is present at the output of the gate means, a reset signal circuit means including a reset signal source and the switching path of the switch means, the reset signal circuit means coupling the reset signal source to reset input means of the processor means and to the second input of the gate when the switch means 25 is rendered conducting, a clock means for providing a clock signal pulse coupled to both an input means of the processor means which input means is associated with the processor means' service signal pulse generation, and to the first input of the gate means for causing a first voltage state to be present thereat and rendering the switch means conducting, a delay means for delaying, for a predetermined period, the rendering of the switch means conducting, whereby if the regular service signal pulse is not generated within the predetermined period, the switch means is rendered conducting thereby extending a reset signal to the reset input of the processor means and to the second input of the gate means to cause the first voltage state to present at the output of the gate means to change to the second voltage state and render the switch means nonconducting thereby disconnecting the reset signal, and whereby if the regular service signal is generated within the predetermined period the service signal pulse causes the first voltage state present at the output of the gate means to change to the second voltage state preventing the delay rendering the switch means conducting.
4. An arrangement as claimed in claim 3, including a latch means arranged to latch the gate means when the voltage state at the output of the gate means is the first voltage state.
5. An arrangement as claimed in claim 4, wherein the latch means comprises a second controllable semiconductor switch means whose control element is coupled to the output of the gate means and a switching path of which is coupled to the first input of the gate means, whereby when the first voltage state is present at the output of the gate means the switching path of the second controllable semiconductor switch applies a voltage state to the first input which maintains the first voltage state at the output of the gate.
6. An arrangement as claimed in any one of claims 3 to 5, wherein the output of the gate means is coupled to the control element of the first controllable semiconductor switch means via a time constant means whereby the first controllable semiconductor switch means is rendered conducting only after a period determined by the elements of the time constant means'.
7. An arrangement as claimed in claim 6, wherein the elements of the time constant means comprise an RC network arranged to introduce a delay of approximately 50 ms.
8. An arrangement as claimed in claim 7, including a discharge circuit to discharge the RC networks capacitor means when a second voltage state is present at the output of the gate means.
9. An arrangement as claimed in any one of claims 5 to 8, including an inverting stage arranged to couple the clock signal pulse to the control element of the second controllable semiconductor switch means to provide the clock pulse with an appropriate logic sense.
10. An arrangement as claimed in any one of claims 3 to 9, including a hookswitch signal input means coupled to the first input of the gate means whereby upon the subset arrangement being brought into an offhook mode a voltage state is applied to the first input such that the voltage state of the output of the gate means changes from the second voltage state to the first voltage state to extend a reset signal to the reset input of the processor means and the next signal circuit.
11. An arrangement as claimed in any one of claims 5 to 10, including a voltage monitor input means coupled to the said output of the gate means, whereby when the supply voltage of the subset arrangement's voltage reaches a predetermined voltage level a voltage monitor signal is produced at the voltage monitor input means such that a first voltage state is produced at the output of the gate means thereby rendering the first switch means conducting to extend a reset signal to the reset input of the processor means.
12. An arrangement as claimed in any one of claims 3 to 11, wherein the pulse rate of the clock signal pulse is one pulse per minute.
13. An arrangement substantially as described herein with reference to Figures 1 and 2 of the drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| AUPM019793 | 1993-07-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9414749D0 GB9414749D0 (en) | 1994-09-07 |
| GB2280568A true GB2280568A (en) | 1995-02-01 |
Family
ID=3777094
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9414749A Withdrawn GB2280568A (en) | 1993-07-28 | 1994-07-21 | Timer circuit and method in or for a telephone subset |
Country Status (3)
| Country | Link |
|---|---|
| BE (1) | BE1009037A3 (en) |
| GB (1) | GB2280568A (en) |
| NZ (1) | NZ260962A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU672113B2 (en) * | 1993-07-28 | 1996-09-19 | Alcatel Australia Limited | Watchdog timer circuit for telephone subset |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57192159A (en) * | 1981-05-20 | 1982-11-26 | Fujitsu Ltd | Resetting system for push button telephone set circuit |
| US5008927A (en) * | 1988-05-05 | 1991-04-16 | Transaction Technology, Inc. | Computer and telephone apparatus with user friendly computer interface integrity features |
| JPH0360554A (en) * | 1989-07-28 | 1991-03-15 | Sharp Corp | Reset controller for telephone set having microcomputer |
| JP3035937B2 (en) * | 1989-11-27 | 2000-04-24 | 日本電気株式会社 | Multifunctional telephone |
| JPH03232024A (en) * | 1990-02-08 | 1991-10-16 | Zexel Corp | Watchdog timer circuit |
| FR2670644A1 (en) * | 1990-12-18 | 1992-06-19 | Lewiner Jacques | Device for reinitialising digital control units of apparatus connected to or installed in telephone systems |
-
1994
- 1994-07-08 NZ NZ26096294A patent/NZ260962A/en unknown
- 1994-07-18 BE BE9400674A patent/BE1009037A3/en not_active IP Right Cessation
- 1994-07-21 GB GB9414749A patent/GB2280568A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU672113B2 (en) * | 1993-07-28 | 1996-09-19 | Alcatel Australia Limited | Watchdog timer circuit for telephone subset |
Also Published As
| Publication number | Publication date |
|---|---|
| NZ260962A (en) | 1996-11-26 |
| BE1009037A3 (en) | 1996-11-05 |
| GB9414749D0 (en) | 1994-09-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4099033A (en) | Telephone security device | |
| US5333190A (en) | Telephone ring detection method and apparatus | |
| US5142569A (en) | Apparatus for selectively enabling subscriber device to respond to ringing signal in dependence upon ringing cadence | |
| US4520233A (en) | Telephone line security apparatus | |
| EP0067268A3 (en) | Hook flash actuated telephone control device | |
| US4324954A (en) | Dialing circuits and methods for electronic telephone sets | |
| US5471524A (en) | Toll call restrictor method and apparatus | |
| JPH09153970A (en) | Automatic control device for power supply to facsimile/modemto be installed on personal computer | |
| AU672113B2 (en) | Watchdog timer circuit for telephone subset | |
| GB2280568A (en) | Timer circuit and method in or for a telephone subset | |
| JPH0720748U (en) | Coin phone | |
| US3969591A (en) | Circuit for preventing impulse generation by operating a hook switch in a telephone set | |
| GB2169775A (en) | Ringing signal sending-out circuit | |
| US5031212A (en) | Dialer circuit | |
| US3702905A (en) | Multi-station shared automatic dialing apparatus | |
| US4096357A (en) | Toll-call restriction system | |
| US4145572A (en) | Power supply control circuit for subscriber carrier telephone system | |
| JPS6351627B2 (en) | ||
| US5317634A (en) | Telephone subset arrangement | |
| US6980634B1 (en) | Telephone circuit controller apparatus | |
| JPH0432580B2 (en) | ||
| KR0167836B1 (en) | Protection device of telephone locking system | |
| GB2229341A (en) | A telephone dialler provides automatic selection of VF dialling or loop disconnect dialling to match exchange requirements | |
| KR0181002B1 (en) | A telephone | |
| SU1584119A1 (en) | Device for inhibition of dialing unauthorized numbers |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |