NZ210217A - Phase lock loop:frequency dependent feedback delay to phase comparator - Google Patents

Description

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Patents Form No.5.

Patents Act 1953 ' COMPLETE SPECIFICATION "Phase-Locked Loops and Electrical Networks Incorporating Them" WE, BRITISH TELECOMMUNICATIONS, A British Corporation established by Statute of 2/12 Gresham Street, London EC2V, 7AG, -England, hereby delcare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the .following statement:- v 2 210217 DESCRIPTION This invention relates to phase-locked loops and to the synchronisation of a number of electrical oscillators contained in phase-locked loops.

The construction of phase-locked loops is well-known. When several phase-locked loops are required to be interconnected there may be variable delays. The delays cannot be compensated for in a simple manner.

Most systems in which oscillators are required to be synchronised are in one of two categories. In the first category the oscillators are remote from one another and each performs a unique non-redundant function. Such a synchronised system exists in some navigation aids. In the other type of system the oscillators are located in close proximity and the plurality of oscillators is provided for reliability enhancement.

The present invention may find application in either type of system. 210217 3 A method of synchronisation for either type of system is to nominate one oscillator as the master and to phase-lock the remainder to it as slaves. "Whilst the method is satisfactory in many applications it nevertheless suffers from the disadvantage that synchronism between the slave oscillators depends on the continuing operation of the master.

This disadvantage is most often a serious consideration in the second type of system mentioned above, since, if the desired reliability enhancement is to be achieved, some provision must be made to keep the remaining oscillators locked together if the master oscillator fails. This disadvantage may for example appear in automatic telephone exchanges where the oscillators are included as a source of clocking signals. One procedure for dealing with failure of the master oscillator that has been proposed is to use a hierarchical arrangement of masters and slaves; the first slave in the hierachy taking control if the master fails. To implement this technique fault ' 2102 1 7 k detection and .changeover mechanisms are required, and the reliability of such -mechanisms is crucial to the operation of the system.

Such an hierarchical arrangement is described in United States Patent Specification .3»9^2,115 in the context of a satellite communications system.

Another control scheme for synchronising the frequencies of geographically separate oscillators connected by communication links comprises the steps of averaging the phases received at each station from remote oscillators, comparing the result with the local phase, and applying the filtered error signal as a correction to the local oscillator. This technique is known as "mutual synchronisation", and is described, for example, by Gersho and Karafin in Bell Systems Technical Journal, December 1966, ppl689 - 1705.

Another method of synchronisation with some similarities to the mutual synchronisation scheme is referred to as 'majority voting'. Such a system is described by Hopkins et al in Proc IEEE Vol 66 No. 10, October 1978, ppl225 and 1231 - 1232. Control circuitry for an oscillator monitors the output from three other oscillators and all four are phase locked together. If one differs the control circuitry takes the majority signal .of the other two and phase locks to that.

The present invention provides a system for synchronising oscillators using the modified phase-locked loop in accordance with the invention in which like the master and slave systems relies on each oscillator synchronising to one other. There is however no master oscillator predetermined by the configuration and no hierarchy built into the configuration of the system. There is also no phase averaging or majority voting. Each oscillator in the system synchronises itself to one other, chosen at random from available inputs. Each oscillator receives inputs from the other oscillators and is controlled such that it repeatedly attempts to synchronise with another oscillator until the system as a whole is synchronised.

A very limited non-hierachical synchronisation system is described in the specification for United States Patent No. 3*662,277. ;Figure 1 of the accompanying drawings illustrates schematically the basis of the system in U.S. Patent No. 3*662,277 and in a fault-free state each oscillator and its control circuitry is connected by an incoming and outgoing path to each of the others. 6 2102 1 7 Figure 2 shews diagrammatically the possible combination of paths between the terminals A, B and C when fault conditions occur. A fault may result from a single or multiple failure of the paths. In Figure 2 (a) there are no fault conditions, all paths are available, and all terminals can synchronise.

Figure 2 (b) shows the case where one path is unavailable and there are six combinations of this condition, and again all terminals can synchronise as is readily apparent.

Figures 2 (c) to (f) show the four different arrangements that can occur when two paths are unavailable. In the case of the arrangements shown in (c), (d) and (e) there are three combinations of each of these arrangements. In the arrangement shown in Figure 2 (f) there are six combinations.

In each of these, all terminals may still synchronise. "When only three paths are available, as shown in Figures 2 (g) to (j), whether or not the terminals can synchronise depends on the particular configuration of the available paths. Figure (j) of which there are six combinations is an arrangement where synchronisation 2102 \y 7 can occur, whereas in Figure (h) (six combinations) and in Figure (i) (two combinations) it is not possible for the terminals to synchronise. In Figure (g) (six combinations) all the terminals can synchronise providing B is the master so that A locks to B; whereas if B is locked to A, C becomes isolated and therefore all three terminals cannot synchronise. In the final case where four paths are unavailable, the four possibilities are shown in 2 (k) to (n) and in only one, 2 (l) is synchronisation possible.

This system is characterised by being able to synchronise if and only if a direct path remains intact between one oscillator, which becomes the master, and each of the others which become the slaves.

The present invention seeks to provide a more fault tolerant system than the system illustrated in Figure 2. 2102 1 7 8 In the "following description of the invention and examples of its embodiments reference will be made to terminals. A terminal is herein defined as containing (i) an oscillator whose frequency can be controlled, (ii) a locking circuit capable of synchronising the oscillator with an incoming signal frequency, (iii) reconfiguration control means which monitors at least the incoming signals to the terminal, and on the basis of those signals can connect the locking circuit to any one of the number of input signals. .The reconfiguration control means may also in some cases be capable of disconnecting the oscillator from its outgoing links.

Reference will also be made to a path between two terminals which is defined as the serial connection of:- (a) an operating oscillator of one terminal (b) an intact link (i.e. the physical connection between the terminals including any buffers or filters); • .2102,17 ! r; r„ _ ; r ! - 9 - ; (c) an operating reconfiguration control of the second terminal capable of connecting to, or with a permanent connection to, the signal received from said link; (d) a functioning locking circuit of the second terminal.

Failure of a path will result from failure of any one of the above. In the case of reconfiguration control failure such that it is permanently connected to said link does not constitute failure of the path.

According to the present invention there is provided: a phase-locked loop including a variable delay element from the output of its oscillator to the input of its phase comparator, the delay caused by the delay element being controlled by the signal that controls the oscillator so that when the oscillator is made to increase in frequency the delay and is made to decrease/when the oscillator is made to decrease in frequency the delay is made to increase.

The invention also provides a pair of phase-locked loops as aforesaid characterised in that the output of each is connected to the input of the other.

The invention also provides a network of three or more phase-locked loops as aforesaid, each phase-locked loop being part of a terminal, and each 2 102 terminal being interconnected, each terminal further comprising reconfiguration control means operative to monitor the incoming signals to the terminal and to connect the phase locked loop to any one of the incoming signals, the terminals being interconnected such that each is linked to the output of at least one of the other terminals in the network to receive output signals from the respective oscillators in those terminals; and the reconfiguration control means being operative to connect the phase-locked loop to any one of the incoming signals, if any are present, and to reconnect the phase-locked loop if the local oscillator fails to lock to the incoming signal initially chosen, the output from each oscillator being continuously transmitted on its outgoing links, so that the plurality of terminals tends towards stable synchronisation provided that a forward path exists directly or indirectly from anyone terminal to the remainder.

Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings.

In the drawings: Figure 1 shows diagrammatically a system >2102 _ 11 containing three oscillators illustrating the operation of a known system; Figure 2 (a) -to (n) are diagrams of the three terminal system illustrating various fault conditions.

Figure 3 is a block diagram of a phase-locked loop; Figure 4 is a block diagram of a phase-locked loop with feedback delay; Figure 5 is a block diagram of a phase-locked loop with input delay and feedback delay; Figure 6 is a block diagram of a circuit similar to that shown in Figure 5, but including variable feedback delay; Figure 7 is a block circuit diagram of two interconnected phase-locked loops; Figure 8 is a graph showing frequency plotted against time, and illustrating compatible delay conditions for the circuit of Figure 7; Figure 9 is a schematic diagram of surmountable fault conditions in an embodiment of the invention; Figure 10 is a flow diagram of an algorithm controlling terminal reconfiguration.

Referring to Figure 3 in its basic form a phase-locked loop comprises an oscillator 1, the 2102 12 output freqency of which can be controlled by an input signal (usually a voltage). Variation in the input signal causes variation in the output frequency of the oscillator. Also included is a filter 2, the reason for. wich need not be considered here. The last of the three basic elements is a comparator 3 which produces an output signal proportional to the phase difference between the input signals constituted by the input signal to the device as a whole and a feedback signal from the output of the oscillator 1. 2102 1 7 13 In essence a phase-locked loop is a second order feedback, device where any difference in phase between the two input signals to the phase comparator 3 produces an error signal which alters the frequency of the oscillator 1 in a direction that reduces the phase difference. In steady conditions with a constant frequency input the input signals to the phase comparator will be in phase.

Referring to Figure k , if a delay element k is introduced into the feedback path then when the system has settled there will still be no phase error between the two inputs to the phase comparator. The output of the oscillator 1 will, however, be phased advanced from the input to the comparator by the delay caused by the element 4 in the feedback path. Use of this principle will now be described in a system which compensates for unwanted delay in the input path. If the unwanted delay is A t^ then theoutput of the phase-locked loop is compensated if the delay element in the feedback path presents a delay A t^ which is equal to -A t^. 2102 17 ik Referring now to Figure 5 > the circuit shown includes a connection from the output terminal of the oscillator 1 back to the input side of the element which introduces the unwanted delay /X t^. It is not possible for the two delays A and A t^ to be exactly equal and since the input signals to the circuit elements which cause these delays come from exactly the same source there will inevitably always be a small phase delay between the input signals to the phase comparator J>. The comparator will unsuccessfully attempt to alter the frequency of the oscillator i to reduce this differential, and the oscillator 1 will drift to an extreme of its range.

The direction of the drift and therefore to which extreme the oscillator drifts depends on whether A t^ is greater than A t^ or vice versa. Thus if A t2 is greater than A. then the comparator 3 will continuously attempt to increase the frequency of the oscillator i in a vain effort to correct the error.

Referring now to Figure 6 the delay element k is variable one that is supplied with, and controlled by, the signal from the comparator 3 so that the delayAtg decreases as the oscillator frequency 210217 increases. As the comparator 3 increases the oscillator frequency to correct the disparity at its input, A t2 is decreased until A % becomes equal to A t^. Any further increase in the frequency of the oscillator will create an error in the opposite direction and the comparator will then reduce the frequency of the oscillator. Thus the arrangement shown in Figure 6 can be made to stabilise with A t^ equal to A ± Referring now to Figure 7 this diagram shows two phase-lock loops of the kind shown in Figure 6, each including input circuitry which gives an unwanted delay A t^ and At^ respectively. Unlike the circuit in Figure '6 , the output of each phase- lock, loop is connected to the input circuitry of the other. Designating the upper phase-lock loop as A and the lower as B, and defining the particular instance of the input signal to the circuit B as a reference time T then the output of the input circuitry to circuit B will be T + A ± Assuming that the system is stable then the other input to the comparator 3 in the circuit B will be exactly in phase with the input from its input circuitry i.e. also timed at T + A t^. Since the other input to the phase comparator of circuit 2102,17 B comes from its delay element k vhich gives a delay At^ then the input to this delay element i.e. the output of the oscillator 1 of the circuit B must be timed at T + A - A t^. The output of the oscillator 1 in circuit B is the input to the input circuitry of the circuit A. If the same reasoning is applied, the output of the oscillator i in circuit A must be T + (A t^ - Atg) + ( A t, - At^). But, this is also the input to the input circuitry of circuit B which we defined, as being timed at time T. Thus, T = T + ( A t± - A t2) + ( A t3 - A t4) (A t± - A t2) = - (A t3 - A t^) The further condition for stability of the circuit is that the two oscillators in the circuits A and B must give outputs of identical frequency. Since A t^ and A t^ are functions of frequency, then the frequency at which A t.^ - A t equals A t^ - A is the stable frequency. An analytic solution is possible for illustration Figure 10 shows a possible graph of the values of A t1 - A tg and A t - A at varying frequencies. 210217 Ideally, t^- and should be close to zero at the. stable frequency since this would minimise the phase error between the outputs of the oscillators in each circuit. It would also be ideal for the two curves of the graph to coincide.

The arrangements of the two phase-lock loops as described may be extended to a full system including N phase-locked loops. Some examples of connections where synchronisation is possible are shown in Figure 9. The loops need not be connected as a ring but may for example have two linked in a ring and one in a spur, or other combinations. Despite all the possible combinations of rings and spurs the phase delays between the oscilltor outputs of the phase-locked loops will still be minimal. This is because on the spur terminals the feedback delay will compensate for the input delay.

The combination of such phase-locked loops may be applied to a network of oscillators that are required to be synchronised. Each oscillator is part of a phase-locked loop in accordance with the invention included within a terminal as hereinbefore defined and each is connected to each of the other N-l terminals. To enable synchronisation to be - IS - 210217 achieved the reconfiguration unit in the terminal must execute an algorithm enabling the terminals to mutually synchronise. Figure 10 illustrates a suitable algorithm. The reconfiguration unit detects whether there are signals on two or more inputs, if there are then the phase-locked loop circuit is connected to one of them. If in a preset time the circuit has not locked to the input it is reconnected to another input. If the circuit has locked it returns to the beginning of the cycle, and will attempt to lock to another input, if there is one. In this way the N terminals will tend towards synchronisation to one frequency.

The system is highly fault-tolerant and all oscillators will remain in synchronism provided that there remains a path either directly or indirectly from any one phase-locked loop to the other N-l. The system offers the further advantage that each oscillator remains connected continuously to the other terminals.

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Claims (4)

WHAT WE CLAIM IS: ' ' ™':

1. A phase-locked loop characterised by the inclusion of a variable delay element from the output of its oscillator to the input of its phase comparator, the delay caused by the delay element being controlled by the signal that controls the oscillator so that when the oscillator is made to increase in frequency the delay is made to decrease and when the oscillator is made to decrease in frequency the delay is made to increase.

2. A pair of phase-locked loops as claimed in Claim 1 characterised in that the output of each is connected to the input of the other.

3. A network of three or more phase-locked loops as claimed in Claim 1, each phase-locked loop being part of a terminal, and each terminal being interconnected,each terminal further comprising reconfiguration control means operative to monitor the incoming signals to the terminal and to connect 20 210217 the phase-locked loop to any one of the incoming signals, the terminals being interconnected such that each is linked to the output of at least one of the other terminals in the network to receive output signals from the respective oscillators of the phase-lock loops in those terminals; and the reconfiguration control means being operative to connect the phase-locked loop to any one of the incoming signals, if any are present, and to reconnect the phase-locked loop to another incoming signal if the local associated oscillator fails to lock to the incoming signal initially chosen, the output from each oscillator being continuously transmitted on its respective terminal outgoing links, so that the plurality of terminals tends towards stable synchronisation provided that a forward path exists directly or indirectly from anyone terminal to the remainder.

4. A system of interconnected phase-locked loops substantially as hereinbefore described with reference to, and as illustrated in, Figures 6 to 10 of the accompanying drawings. BRITISH TELECOMMUNICATIONS by their authorised agents P.L. BERRY & ASSOCIATES per: