JPH03106147A - Phase locked loop oscillator - Google Patents

Phase locked loop oscillator

Info

Publication number
JPH03106147A
JPH03106147A JP1244038A JP24403889A JPH03106147A JP H03106147 A JPH03106147 A JP H03106147A JP 1244038 A JP1244038 A JP 1244038A JP 24403889 A JP24403889 A JP 24403889A JP H03106147 A JPH03106147 A JP H03106147A
Authority
JP
Japan
Prior art keywords
clock
station
frequency
signal
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1244038A
Other languages
Japanese (ja)
Inventor
Minoru Hoshiki
星敷 実
Tomoo Kokkyo
国京 知雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP1244038A priority Critical patent/JPH03106147A/en
Publication of JPH03106147A publication Critical patent/JPH03106147A/en
Pending legal-status Critical Current

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  • Small-Scale Networks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To improve the communication quality between stations by providing a voltage control means to an input of a voltage controlled oscillator so as to avoid disabled clock extraction by each station thereby preventing disabled communication between stations. CONSTITUTION:When a frequency of a reference clock signal is largely fluctuated and a signal (a) is inputted from a low pass filter 11, A voltage limit circuit 15 limits a voltage and outputs a signal (b) to a voltage controlled oscillator 12. As a result, the frequency fluctuation of the voltage controlled oscillator 12 is suppressed. That is, even when the reference clock signal (output clock from a private branch of exchange) is subjected to faulty frequency, the frequency fluctuation of the output clock of a phase locked loop oscillator of a master station is suppressed small and disabled clock extraction by each station is avoided. Thus, the communication quality between stations is improved.

Description

【発明の詳細な説明】 [発明の目的] (産業上のfリ用分野〉 本発明は、ローカルエリアネットワーク(LAN)等に
用いられる位相同期発振器に関する。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial field) The present invention relates to a phase synchronized oscillator used in a local area network (LAN) or the like.

(従来の技術) ローカルエリアネットワークの一種としてのループネッ
トワークシステムでは、複数の局を伝送路を介してルー
プ状に接続し、各局間で通信を行う。
(Prior Art) In a loop network system as a type of local area network, a plurality of stations are connected in a loop via transmission paths, and communication is performed between each station.

第3図はこのようなループネットワークシステムの構成
を示す図であり、マスタ局1と複数の局2−1〜2−n
とが伝送路3によってループ状に接続される。複数の局
2−1〜2−n間で通信を行う場合には、マスタ局1が
クロック信号を生威し、他の局2−1〜2−nはループ
中のビット列よりクロック信号を抽出し、これをもとに
局内の論理回路が動作する。
FIG. 3 is a diagram showing the configuration of such a loop network system, in which a master station 1 and multiple stations 2-1 to 2-n
are connected in a loop by a transmission line 3. When communicating between multiple stations 2-1 to 2-n, the master station 1 generates the clock signal, and the other stations 2-1 to 2-n extract the clock signal from the bit string in the loop. Based on this, the logic circuit within the station operates.

また、同図に示されるようにかかるループネットワーク
システムを構内交換機(PBX)4を介して広域網5に
接続することもある。このような場合、マスタ局1は広
域網5から送られる基準クロック信号に基づき第2図に
示す位相同期発振姦を用いてクロック信号を生成する。
Further, as shown in the figure, such a loop network system may be connected to a wide area network 5 via a private branch exchange (PBX) 4. In such a case, the master station 1 generates a clock signal using the phase synchronized oscillation shown in FIG. 2 based on the reference clock signal sent from the wide area network 5.

この従来の位相向明発振器は、基準クロック信号(構内
交@機の出力クロック)と分周器13からの出力信号の
位相を比較し位相差に応じた信号を低域フィルタ11に
送る位相比較器10と、所定の低域周波数の信号のみを
出力する低域フィルタ11と、低域フィルタ11から送
られる信号に応じてパルス信号を発振し出力端子及び分
周器13へ送る電圧制御発振器12と、電圧制御発振器
12の出力したパルス信号を分周し位相比較器10に送
る分周器13とで構成されている。
This conventional phase-directed oscillator compares the phase of the reference clock signal (output clock of the local exchange machine) and the output signal from the frequency divider 13, and sends a signal according to the phase difference to the low-pass filter 11. a low-pass filter 11 that outputs only a signal with a predetermined low frequency, and a voltage-controlled oscillator 12 that oscillates a pulse signal according to the signal sent from the low-pass filter 11 and sends it to an output terminal and a frequency divider 13. and a frequency divider 13 that divides the frequency of the pulse signal output from the voltage controlled oscillator 12 and sends it to the phase comparator 10.

しかしながら、この場合、構内交換機4の基準クロック
信号(出力クロック)が広域網4と同期していないと、
穴常周波数のクロックがマスタ局1に供給されて、マス
タ局1の位相同期発振器の出力周波数も叉常となり、各
局のクロツク抽出ができる周波数範囲を越えてしまい各
局間の通信が不可能になる場合があった。
However, in this case, if the reference clock signal (output clock) of the private branch exchange 4 is not synchronized with the wide area network 4,
A clock with a normal frequency is supplied to master station 1, and the output frequency of the phase synchronized oscillator of master station 1 also becomes abnormal, exceeding the frequency range in which each station's clock can be extracted, making communication between each station impossible. There was a case.

(発明が解決しようとする課題) 上述したように従来のループ式通信方式では、構内交換
機の出力クロック周波数が大きく変動すると、各局のク
ロック抽出ができなくなるという問題があった。
(Problems to be Solved by the Invention) As described above, in the conventional loop communication system, there is a problem in that when the output clock frequency of the private branch exchange greatly fluctuates, it becomes impossible to extract the clock of each station.

本発明は、上記のような問題を解決するためになされた
ものであり、構内交換機の出力クロツク周波数が大きく
変動しても、マスタ局の発生するクロックは周波数変動
が小さくて各局間の通信が可能となる位相同期発振器を
提供することを目的とする。
The present invention was made in order to solve the above-mentioned problems, and even if the output clock frequency of the private branch exchange varies greatly, the frequency variation of the clock generated by the master station is small, and communication between each station is maintained. The purpose of this invention is to provide a phase-locked oscillator.

[発明の構成コ (課題を解決するための手段) 上記従来の目的を達或する本発明は、複数の局が伝送路
によってループ状に結合され、マスタ局は網クロックに
同期したクロックを発生し、各局は受信信号よりクロッ
クを抽出し、各局間で通信を行う時分割多重方式のルー
プ式通信システムの前記マスタ局に備えられ前記クロッ
クを発生する位相同期発振器において、電圧制御発振器
の人力側に電圧制限手段を備え、前記各局がクロツク抽
出ができなくなり、各局間の通信不能を防止することを
特徴とする。
[Structure of the Invention (Means for Solving the Problems) The present invention achieves the above-mentioned conventional objects by connecting a plurality of stations in a loop through a transmission path, and a master station generates a clock synchronized with a network clock. Each station extracts a clock from the received signal, and in the phase synchronized oscillator that generates the clock and is installed in the master station of the time division multiplex loop communication system in which each station communicates, the human power side of the voltage controlled oscillator is The present invention is characterized in that a voltage limiting means is provided to prevent each station from extracting a clock, thereby preventing communication between the stations.

(作 用) 本発明では、構内交換機の出力クロツク周波数が大きく
変動しても、電圧制御発振器の入力電圧が一定以上大き
く変動しないので、マスタ局の発生するクロックの周波
数変動は防止される。
(Function) In the present invention, even if the output clock frequency of the private branch exchange greatly fluctuates, the input voltage of the voltage controlled oscillator does not fluctuate more than a certain level, so that fluctuations in the frequency of the clock generated by the master station are prevented.

(実施例) 以下、本発明の一実施例について図面を参照して詳細に
説明する。
(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

第1図は本発明の一実施例に係る位相同期発振器の構威
を示すブロック図である。
FIG. 1 is a block diagram showing the structure of a phase-locked oscillator according to an embodiment of the present invention.

同図に示す実施例の位相同期発振器は、位相比較器10
、低域フィルタ11、電圧制限回路15、電圧制御発振
W12、分周器13から構成されている。
The phase synchronized oscillator of the embodiment shown in the figure has a phase comparator 10.
, a low-pass filter 11, a voltage limiting circuit 15, a voltage controlled oscillation W12, and a frequency divider 13.

位相比較器10は、入力端子21から入力される話準ク
ロックf=号St(構内交換機の出力クロック)と分周
器13からの出力信号の位相を比較し、位相差に応じた
信号を低域フィルタ11に送る。低域フィルタ11は、
所定の低域周波数の信号のみを電圧制限回路15に送る
。電圧制限回路15は、低域フィルタ11から送られる
信号を電圧1:リ御発振器12へ供給する。この場合、
基準クロック信号の周波数が大きく嚢動し、第4図(a
)に示すような信号が低域フィルタ11から入力される
と、電圧制限回路15は電圧制限をして第4図(b)に
示すような信号を電圧制御発振器12へ出力する。この
結果、第4図(c)のように電圧制御発振器12の周波
数変動が抑えられる。
The phase comparator 10 compares the phase of the standard clock f=signal St (private branch exchange output clock) input from the input terminal 21 with the output signal from the frequency divider 13, and lowers the signal according to the phase difference. It is sent to the bandpass filter 11. The low-pass filter 11 is
Only signals of a predetermined low frequency are sent to the voltage limiting circuit 15. Voltage limiting circuit 15 supplies the signal sent from low-pass filter 11 to voltage 1:restricted oscillator 12 . in this case,
The frequency of the reference clock signal fluctuates greatly, as shown in Fig. 4 (a).
) is input from the low-pass filter 11, the voltage limiting circuit 15 limits the voltage and outputs a signal as shown in FIG. 4(b) to the voltage controlled oscillator 12. As a result, the frequency fluctuation of the voltage controlled oscillator 12 is suppressed as shown in FIG. 4(c).

電圧制御発振器12は、パルス信号を出力端子22及び
分周器13へ送る。分周器13は、電圧制御発振器12
の出力したパルス信号を分周し、位相比較器10に送る
Voltage controlled oscillator 12 sends a pulse signal to output terminal 22 and frequency divider 13 . The frequency divider 13 is a voltage controlled oscillator 12
The output pulse signal is frequency-divided and sent to the phase comparator 10.

これにより、本実施例では、基準クロック信号(構内交
換機の出力クロック)が異常周波数になっても、マスタ
局の泣相同期発振器の出力クロックの周波数変動は小さ
く抑えられるので、各局のクロツク抽出ができなくなる
ことがなくなり、局間の通信品質が大福に向上できる。
As a result, in this embodiment, even if the reference clock signal (output clock of the private branch exchange) becomes an abnormal frequency, the frequency fluctuation of the output clock of the phase synchronized oscillator of the master station is suppressed to a small level, so that the clock extraction of each station is Communication quality between stations can be greatly improved.

[発明−の効果] 以上説明したように本発明によれば、越準クロック信号
が異常周波数になってもマスタ局の出力周波数食動が小
さく抑えられるようになり、各局のクロック抽出ができ
なくなることがなくなる。
[Effects of the Invention] As explained above, according to the present invention, even if the over-standard clock signal becomes an abnormal frequency, the output frequency deviation of the master station can be suppressed to a small level, making it impossible to extract the clock of each station. Things will disappear.

この粘果、局間の通信品質が大幅に向上する。As a result of this, the quality of communication between stations is greatly improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例にかかる位相同期発振器の構
或を示すブロック図、第2図は従来の位f目同期発振器
の4++7成を示すブロック図、第3図はループネット
ワークシステムの概略構成図、第4図(a)から(c)
は第1図の電圧制限回路の動作説明図である。 1・・・マスタ局、2−1〜2−n・・・局、3・・・
伝送路、4・・・構内交換機、5・・・広域網、10・
・・位相比較器、]1・・・低域フィルタ、12・・・
電圧制御発振器、13・・・分周器、15・・・電圧制
限回路、21・・・人力端子、22・・・出力端子。
FIG. 1 is a block diagram showing the configuration of a phase-locked oscillator according to an embodiment of the present invention, FIG. 2 is a block diagram showing a 4++7 configuration of a conventional f-th synchronous oscillator, and FIG. 3 is a block diagram showing a 4++7 configuration of a conventional f-th synchronous oscillator. Schematic configuration diagram, Figure 4 (a) to (c)
2 is an explanatory diagram of the operation of the voltage limiting circuit shown in FIG. 1. FIG. 1... Master station, 2-1 to 2-n... Station, 3...
Transmission line, 4...Private branch exchange, 5...Wide area network, 10.
... Phase comparator, ]1 ... Low-pass filter, 12 ...
Voltage controlled oscillator, 13... Frequency divider, 15... Voltage limiting circuit, 21... Human power terminal, 22... Output terminal.

Claims (1)

【特許請求の範囲】 複数の局が伝送路によってループ状に結合され、マスタ
局は網クロックに同期したクロックを発生し、各局は受
信信号よりクロックを抽出し、各局間で通信を行う時分
割多重方式のループ式通信システムの前記マスタ局に備
えられ前記クロックを発生する位相同期発振器において
、 電圧制御発振器の入力側に電圧制限手段を備え、前記各
局がクロック抽出ができなくなり、各局間の通信不能を
防止することを特徴とする位相同期発振器。
[Claims] A time-sharing system in which multiple stations are connected in a loop through a transmission path, the master station generates a clock synchronized with the network clock, each station extracts the clock from the received signal, and each station communicates. In the phase synchronized oscillator that is provided in the master station of the multiplexed loop communication system and generates the clock, voltage limiting means is provided on the input side of the voltage controlled oscillator, so that each station is unable to extract the clock, and communication between each station is prevented. A phase-locked oscillator characterized by preventing failure.
JP1244038A 1989-09-19 1989-09-19 Phase locked loop oscillator Pending JPH03106147A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1244038A JPH03106147A (en) 1989-09-19 1989-09-19 Phase locked loop oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1244038A JPH03106147A (en) 1989-09-19 1989-09-19 Phase locked loop oscillator

Publications (1)

Publication Number Publication Date
JPH03106147A true JPH03106147A (en) 1991-05-02

Family

ID=17112789

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1244038A Pending JPH03106147A (en) 1989-09-19 1989-09-19 Phase locked loop oscillator

Country Status (1)

Country Link
JP (1) JPH03106147A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001093492A1 (en) * 2000-05-31 2001-12-06 Mitsubishi Denki Kabushiki Kaisha Clock

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001093492A1 (en) * 2000-05-31 2001-12-06 Mitsubishi Denki Kabushiki Kaisha Clock

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