NO931566L - Faselaasekrets for reduksjon av dirring i et digitalt multipleks system - Google Patents

Faselaasekrets for reduksjon av dirring i et digitalt multipleks system

Info

Publication number
NO931566L
NO931566L NO93931566A NO931566A NO931566L NO 931566 L NO931566 L NO 931566L NO 93931566 A NO93931566 A NO 93931566A NO 931566 A NO931566 A NO 931566A NO 931566 L NO931566 L NO 931566L
Authority
NO
Norway
Prior art keywords
circuit
multiplex system
phaselas
diring
reducing
Prior art date
Application number
NO93931566A
Other languages
English (en)
Other versions
NO931566D0 (no
Inventor
Mats Bladh
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of NO931566L publication Critical patent/NO931566L/no
Publication of NO931566D0 publication Critical patent/NO931566D0/no

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Amplifiers (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Networks Using Active Elements (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

En faselåsekrets for reduksjon av dirring i et digitalt multiplekssystem omfatter en tilbakekoblet operasjonsforsterker (OP). To anti-parallelt koblede dioder (DI, 02) er anordnet på den ene inngang til forsterkeren for oppnåelse av auto- matisk forsterkningsstyring, samtidig som den andre inngang til forsterkeren er forbundet med en referansespenning (Ref).
NO931566A 1990-07-10 1993-04-29 Faselaasekrets for reduksjon av dirring i et digitalt multipleks system NO931566D0 (no)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9002408A SE466474B (sv) 1990-07-10 1990-07-10 Faslaasningskrets foer jitterreducering i digitalt multiplexsystem
PCT/SE1991/000487 WO1992001344A1 (en) 1990-07-10 1991-07-09 Phase locking circuit for jitter reduction in a digital multiplex system

Publications (2)

Publication Number Publication Date
NO931566L true NO931566L (no) 1993-04-29
NO931566D0 NO931566D0 (no) 1993-04-29

Family

ID=20379985

Family Applications (1)

Application Number Title Priority Date Filing Date
NO931566A NO931566D0 (no) 1990-07-10 1993-04-29 Faselaasekrets for reduksjon av dirring i et digitalt multipleks system

Country Status (13)

Country Link
EP (1) EP0549591B1 (no)
AU (1) AU660933B2 (no)
CA (1) CA2095350C (no)
DE (1) DE69128632T2 (no)
DK (1) DK0549591T3 (no)
ES (1) ES2110994T3 (no)
FI (1) FI932330A0 (no)
GR (1) GR3026036T3 (no)
IE (1) IE80859B1 (no)
MX (1) MX9100088A (no)
NO (1) NO931566D0 (no)
SE (1) SE466474B (no)
WO (1) WO1992001344A1 (no)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES2102938B1 (es) * 1994-03-28 1998-04-16 Alcatel Standard Electrica Sistema de reduccion de fluctuaciones de fase en demultiplexores digitales.
US6064273A (en) * 1998-06-04 2000-05-16 Adc Telecommunications Phase-locked loop having filter with wide and narrow bandwidth modes

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3420956A (en) * 1966-01-04 1969-01-07 Bell Telephone Labor Inc Jitter reduction in pulse multiplexing systems employing pulse stuffing
DE2247666C2 (de) * 1972-09-28 1975-02-20 Siemens Ag, 1000 Berlin Und 8000 Muenchen Schaltungsanordnung zur gegenseitigen Synchronisierung der In den Vermittlungsstellen eines PCM-Zeitmultlplex-FernmeMenetzes vorgesehenen Amtstaktoszillatoren
US3830981A (en) * 1973-04-02 1974-08-20 Bell Northern Research Ltd Pulse stuffing control circuit for reducing jitter in tdm system
DE2931401A1 (de) * 1979-07-31 1981-02-19 Siemens Ag Sinus-rechteckwandler
ATE10320T1 (de) * 1980-06-16 1984-11-15 The Post Office Digitale uebertragungssysteme.
US4397017A (en) * 1981-03-02 1983-08-02 Nippon Electric Co., Ltd. Stuff synchronization device with reduced sampling jitter
DE3227849A1 (de) * 1982-07-26 1984-01-26 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zur takterzeugung in fernmeldeanlagen, insbesondere zeitmultiplex-digital-vermittlungsanlagen
CN85100049B (zh) * 1985-04-01 1987-11-25 清华大学 模型法码速调整方法及调整装置
FR2583180B1 (fr) * 1985-06-10 1987-08-07 Cit Alcatel Procede et dispositif de reduction de gigue d'un train numerique synchrone en vue de la recuperation de son rythme
FR2593337A1 (fr) * 1986-01-23 1987-07-24 Berlinet Denis Dispositif de synchronisation d'un signal binaire avec elimination de gigue
FR2597689B1 (fr) * 1986-04-22 1988-06-10 Trt Telecom Radio Electr Dispositif pour la recuperation de rythme convenant notamment pour un systeme de transmission d'informations utilisant dans un sens de transmission le principe dit d'a.m.r.t.
US4820994A (en) * 1986-10-20 1989-04-11 Siemens Aktiengesellschaft Phase regulating circuit

Also Published As

Publication number Publication date
IE80859B1 (en) 1999-04-21
EP0549591B1 (en) 1998-01-07
AU660933B2 (en) 1995-07-13
FI932330A (fi) 1993-05-21
CA2095350C (en) 1999-02-02
GR3026036T3 (en) 1998-04-30
MX9100088A (es) 1992-02-28
DE69128632D1 (de) 1998-02-12
NO931566D0 (no) 1993-04-29
SE9002408D0 (sv) 1990-07-10
CA2095350A1 (en) 1992-01-11
IE912099A1 (en) 1992-01-15
DK0549591T3 (da) 1998-09-07
SE9002408L (sv) 1992-01-11
EP0549591A1 (en) 1993-07-07
AU8234391A (en) 1992-02-04
WO1992001344A1 (en) 1992-01-23
ES2110994T3 (es) 1998-03-01
SE466474B (sv) 1992-02-17
DE69128632T2 (de) 1998-05-20
FI932330A0 (fi) 1993-05-21

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