NO830379L - SYSTEM FOR TRANSMISSION OF DIGITAL SIGNAL PULSES ON AN AC AC DISTRIBUTION NETWORK - Google Patents

Description

The invention relates to a system for the transmission of digital signal pulses over the wires of an alternating current distribution network, largely opposite to the flow direction of the network energy using a "Chirp" frequency modulation and the frequency multiplex method as well as a synchronization of the signal generation in a transmitter and the signal processing in a receiver using the frequency of the mains AC voltage.

Such a system is known from DE-AS 2727263. In this specification, temporally ideal "Chirp" modulation with constant amplitude is described, which, however, has the disadvantage of an excessively large frequency spectrum, which makes it difficult to reduce the noise frequency. In addition, this explanatory document describes a frequency multiplex method with non-overlapping frequency ranges for adjacent transmitters. With a given bandwidth, this method thus enables only simultaneous operation of a relatively limited number of transmission channels on the same transmission path for the transmission path as well as for the transmission signal.

The invention has the task of providing a modulation type as well as transmitting and receiving means for increasing the information density on the transmission path and to overcome special transmission conditions, which usually prevail on this transmission path. This can e.g. be: Excessively high line and transformer attenuation.

Powerful phase and frequency shift.

Large propagation time.

Different powerful and diverse types of noise, e.g.

mains harmonics, different long switching pulses, trawl noise and not white noise.

According to the invention, the above-mentioned task is solved with the help of the features specified in the characteristics of claims.

An embodiment of the invention shall be described in more detail with reference to the drawings, where:

Fig. 1 shows a block diagram of a transmission system.

Fig. 2 shows a block diagram of a provisioning circuit.

Fig. 3 shows a circuit diagram of an analogue/digital converter.

Fig. 4 shows a block diagram of a control circuit.

Fig. 5 shows a block diagram of a remote control transmitter. Fig. 6 shows the relationship between a "Chirp" modulation with

constant and non-constant amplitude.

Fig. 7 shows the frequency division of the transmission channels.

Fig. 8 shows the signal ratio on the transmission path..

Fig. 9 shows a block diagram of a remote control receiver. Fig. 10 shows a block diagram of a receiver signal preparation circuit.

Fig. 11 shows the block diagram of a demodulator.

The same reference numbers denote the same parts in all the figures in the drawings. All components marked with 74LS... in the description originate from the company Texas Instruments, Dallas, Texas. All components marked with MC... originate from the company Motorola, Phenix, Arizona and all components with the designation LM... or LF... originate from the company National Semiconductor, Santa Clara, California.

That in fig. 1 block diagram of a transmission system shows a three-phase alternating current distribution network, a central 1

and at least one subordinate location 2. First, a high voltage 3 is supplied from e.g. 50 kV and a frequency of 50 or 60

Hz over a high-voltage switch 4 and a first transformer

5 to an upper, likewise three-phase intermediate voltage level 6

with a voltage from 16.5 kV. This intermediate voltage level

6 divides into several, e.g. three. three-phase feeders" 7a, 7b and 7c, each of these "feeders" having a separate three-pole intermediate voltage switch 8a, 8b and 8c respectively and a separate, e.g. each of three single-phase converters consisting of measuring converters 9a, 9b and 9c These measuring converters can be current or voltage converters. In Fig. 1 it was assumed that it was a current converter.

The secondary winding of the three single-phase converters feeds one off

the three measuring transducers 9å, 9b respectively. 9c respectively. a measuring circuit consisting of a measuring device, e.g. an ammeter and one of the primary windings of a three-phase tap-in converter. Each "modes" 7a, 7b respectively. 7c is arranged such a three-phase, - e.g. also of three single-phase converters consisting of a connection converter which can be both a current and a voltage converter. It was also assumed here that it was a current converter, whose primary circuit is thus connected in series with the associated measuring device. The "feeder" 7a is e.g. assigned to the connection transformer 10 and the ammeter 11. In fig. 1 only one is shown, namely the measuring circuit fed from the "feeder" 7a.

To the three secondary windings of the three-phase connection converter 10. is the input to the central 1.

The "feeder" of the intermediate voltage level 6 is often connected via their intermediate voltage switches 8a, 8b respectively. 8c the primary circuit of their as current converter arranged measuring converters 9a, 9b respectively. 9c and respective second transformer,

e.g. in the "feeder" 7a above the second transformer 12 with a lower likewise three-phase intermediate voltage level, e.g. the intermediate voltage level 13 in the case of the "feeder" 7a. This lower intermediate voltage level 13 f is for example ... a voltage of 4 kV. In parallel with every other transformer, an isolation amplifier is respectively connected opposite the direction of energy flow to the alternating current distribution network, e.g. in parallel with respect to the second transformer 12 of the isolation amplifier 14.

The lower intermediate voltage level 13 of the "feeder" 7a feeds via a third transformer 15 a low-voltage network 16 on

e.g. 220 V. In the latter case, fig. 1 the subordinate place 2 connected. However, this can also be connected via a voltage converter, not shown, to the intermediate voltage level 13.

The central unit 1 contains a known sound frequency energy control center 13, which controls an equally known sound frequency energy control transmitter 18, over a "feeder" to the upper intermediate voltage level 6, e.g. above the "feeder" 7a, the lower intermediate voltage level 13 and the low voltage network 16 a known sound frequency energy control receiver 19 in the subordinate location 2. The aforementioned control devices form a known sound frequency energy control system, which is not subject to the requirements and therefore not described in more detail. It serves here exclusively for the transmission of call commands from the exchange 1 to the subordinate location 2. Therefore, the only one in fig. 1 showed the output of the audio frequency energy control receiver 19 - it was assumed the presence of a relay contact output - at the call input 20 of a remote control transmitter 21.

The input of the audio frequency energy control receiver 19 and the output of the f iron control transmitter 21 are connected to each other in the subordinate location 2 and to the intermediate voltage network 16. The output signal of the remote control transmitter 21 reaches over the low voltage network 16, the lower intermediate voltage level 13, the "feeder" 7a, the measuring converter 9a and the connection converter 10 the input to the central 1, which is also the input to a remote control receiver 22, whose output in turn controls the input to a remote control evaluation device 23...

Incidentally, the subordinate location has a control circuit 24, a preparation circuit 25, a measured value input bus 26, a numerical value input bus 27, a command input bus 27 and a reset circuit 29. Furthermore, among other things, a system clock output 30 and a system clock input 31 are indicated.

A block diagram of the preparation circuit 25 is shown in FIG. 2.

The system input 31 to the preparation circuit 25 is fed by the aforementioned system clock output 30 to the control circuit 24 with a system clock frequency of 2 MHz and is at the same time the input to a frequency divider 32 which divides this frequency by four. Frequency divider 32 is built using a cascade circuit of two flip-flops 32a and 32b, e.g. of type 74LS74 and has two 90° phase-shifted 500 kHz outputs.

The two interconnected clock inputs to these

the two flip-flops form the input to the frequency divider and the Q output of the first flip-flop 32a controls the D input of the subsequent number of flip-flops 32b while the Q output is in turn fed back to the D input of the first flip-flop 32a. An output signal in phase with the input signal to the frequency divider 32 appears at the Q output of the first flip-flop 32a and is located at the clock input T of a number chain 33 and that about it 90°

the phase-shifted signal at the Q~ output of the second flip-flop 32b feeds a ramp input R to a first transformer circuit 34". The system clock frequency of 2 MHz likewise reaches across a first input to a two-input AND gate 35,

e.g. of type 74LS08, the clock input of a Johnson counter 36, e.g. constructed using a shift register of the type 74LS164 and whose parallel outputs feed a decoder 37. The

the last bit of the Johnson counter 36 is fed back on this data input. The decoder 37 is constructed using several AND gates, e.g. of type 74LS08 and inverters, e.g. of type 74LS04. The first output of the decoder 37 blocks this second output AND gate 35, while a second output is connected to the clock inputs of a first and second buffer storage 38 and 39 and a third output is connected to the control input of a current source 40. At these three outputs to the decoder 3 7 appears respectively at the correct, with the help of the Johnson counter 36 specified moment, a blocking signal (first output) or an opening signal (second and third exits).

The subordinate site 2 (fig. 1) serves to record and transmit the remote control information preferably in the opposite direction of the energy flow to the alternating current tor distribution network. One or more subordinate sites can be operated with a transmission channel.

The following information must be transferred:

a) Spontaneous messages within seconds as well as repetitions, e.g. every second, but without receipt.

b) ; Cyclic measurement values every 1 to 5 minutes.

c) Cyclic number values every 5 to 30 minutes, with a fixed "freeze cycle", which is independent and significantly longer than the transfer cycle, so that in each "freeze period" several transfers of the same counter value are possible. No non-losable numerical value storage takes place.

Each telegram contains all the information.

The measured value, counter value and message input buses 26, 27 and 28 are simultaneously bus inputs with the same name for preparation

the circuit 25 (fig. 2). Advantageously, each entrance bus has 26,

27 and 28 an equal number, e.g. eight wires. In this case, there can be eight measured values, eight numerical values and eight messages. transfered.

Each wire to the measured value input bus 26 is coated with

an analog measurement value. The level of one of these measurement values, e.g. from 22 to 100 V or from 1 VA to 50 VA is limited in an associated level matching circuit 41a to 41g, consisting of a respective resistance network with built-in potentiometer to a voltage range adapted to the following circuit from e.g. +2 to — 2 V and finally supplied via a respective first order RC filter 42a to 42g which serves to eliminate bromine interference > 50 Hz, to the signal inputs of an analog multiplexer 43a. The measured value input signal is bi- or unipolar direct currents or direct voltages.

The address inputs to the multiplexer 43a, controlled by a control bus 43b, during the time reserved for the measurement value assessment in the time multiplex method, select the individual signal inputs of the multiplexer 43a one after the other in time and connect the analog measured values prepared there in time one after the other through to the input of the subsequent buffer amplifier 44 , which works as an impedance converter and which e.g. is a non-inverting amplifier built using an operational amplifier LM 30IA with an amplification factor of 1. Through its high-ohmic input impedance, the load on the input circuit is kept low.

The output of the buffer amplifier 44 is located at a first input to a summing amplifier 45 constructed with the help of an operational amplifier LM 301A, whose output in turn controls the input to a voltage/time converter 46, e.g. of type MC1405. This voltage/time converter 46 contains e.g. a voltage reference source, the output of which feeds a second input to the summing amplifier 45, so that the zero voltage of the circuit is shifted by means of a non-shown potentiometer within the set reference voltage of the summing amplifier 45. The potentiometer is part of the summing amplifier 45 and the output voltage of the latter amounts to e.g. to 0 V to 2 V. The output of the voltage/time converter 46 feeds the number chain 33, which e.g. contains, among other things, a cascade circuit 47 of several binary counters of the type MC 40161 over a second transformer circuit 48 serving as galvanic decoupling. the time converter 46, the number chain 33 and both transformer circuits 34 and 48 together form an analog/digital converter 49, which works according to the known "dual-slope" principle. The circuit structure in the blocks 33, 34 and 48 will be later with the help of fig. 3 described in more detail.

A start signal delivered from the control bus 43b closes all the binary numbers of the cascade circuit 47 in the counter chain 33 so

as well as a "ramp" flip-flop 50 to zero. The latter blocks above a first input an opening gate 51 with two inputs that at its second input, which is at the same time the ramp clock input R of the first transformer circuit 34, standing 500 kHz ramp clock frequency so that at the ramp input of the voltage/time converter 4 6 is the logical value "0".

In the voltage/time converter 46, a "ramp controller" switch then supplies a current proportional to the input voltage to the input of the integrator, whose output voltage then rises continuously from 0 until it reaches the threshold value of a downstream comparator. From this moment, from the output of the comparator, which is also the output of the voltage/time converter 46, via the second transformer circuit 48

in the number chain "33, an opening flip-flop 52 is switched so that with the help of the cascade circuit 47 of the number chain 33, a fixed integration time is calculated by counting 500 kHz clock pulses, which are supplied from the frequency divider 32 via the clock input T to the number chain 33 to the clock input for

the binary counter of the cascade circuit 47.

The ramp clock input R of the first transformer circuit 34 is connected to a first input and the clock input T of the counter chain 33 with a second input to a NOG gate 53 with two inputs, which serves as a pulse shaper and whose output controls the read input of the second transformer circuit 48 and the clock input of the opening flip-flop 52 for the counting chain 33.

A third to tenth parallel output for the cascade circuit

47 to the counting chain 33 form a digital 8-bit data bus,

which via a first of the control buses 43b controlled "three-state" data selector 54 is connected with a measured value output bus 55 to the preparation circuit.25.

The count value and signal switch circuit of the provisioning circuit

25 is then identically structured at each wire to the count value and the signal input bus 27 respectively. 28 is the logical value "1" or "0". In the event that the count value is this digital impulse train, whose frequency is proportional to the count value and in the case of a message, it is a question of digital, continuous signals.

The count value input bus 27 feeds the first filter group 56, whose outputs control the inputs to a first transformer group 57 and whose outputs in turn control the inputs to a first detector group 58. The individual pulses of any: pulse train at the output of the detector group 58 are finally briefly stored in the first buffer storage 38 and then supplied via a second "three-state" data selector 59 controlled likewise by the control bus 43b to a count value output bus 60 for the preparation circuit 25.

The message input bus 28 again feeds in the specified order over a second filter group 61, a second transformer group 62, a second detector group 63, the second buffer storage 39 and a third, also controlled by the control bus 43b, "three-state" data selector 64 to a message output bus 68 for the preparation circuit 25.

All three data selectors .54, 59 and 64 are e.g. of type 74LS257. Instead of this, the "ports" of a write/read storage can also be used.

The third output of the decoder .37 controls at the correct moments indicated by the Johnson counter 36 the control input of the power source 40, whose outputs in turn feed the first and the second transformer groups 57 and 62. The second output of the decoder 37 likewise controls at the correct times, by the Johnson- the counter 36, indicated instants of the clock inputs to the first and second buffer storage 38 and 39.

As already mentioned, the control bus 4 3b acts on the control inputs of the three data selectors 54, 59 and 64 and takes these data selectors at given moments in time one after the other in operation and then so that respectively only one of these data selectors is connected.

Each of both filter groups 56 and 61 to both transformer groups 57 and 62 and both detector groups 58 and 63

has for each leader a count value or to signal input buses, connections 27 and 28 have a respective filter and for each pair of conductors a transformer or a detector. The current source 40 also has a bipolar transistor for each pair of conductors to one of each of the two input bus connections 27 and 28. All these transistors are controlled within the current source 40

of a common, not shown additional power source. The effect of two wires within the count value - or the signal preparation circuit with the associated power source is also shown in more detail in German patent no. 25 33 483 and is therefore not further described here.

In fig. 3 shows a circuit diagram of the analog/digital converter 49 which, as previously mentioned, consists of the voltage/time converter 46, the first transformer circuit 34, the second transformer circuit 48 and the counting chain 33.

In the second transformer circuit 48 is the first

the pole of the primary winding of a second transformer 69 across a first resistor 70 to ground and the other pole across the collector-emitter path of a bipolar transistor 71 to the positive pole of the DC voltage source V . The basis

CG

until the transistor 71 is connected via a base resistor 72 with the read input of the second transformer circuit 48

and simultaneously with the clock input to the opening flip-flop 52 for the counting chain 33 is keyed from the output of the NOG gate 53 with its 500 kHz output signal. If at the moment of the positive-going edge of this output signal there is a logical "0" at the output of the voltage/time converter 46, then the secondary winding of the second isolating transformer 6 9 is short-circuited across a first diode 7 3 in the through-flow direction and a low-resistance series resistance 74, i.e. .this sec-sub circuit is low-resistance. It thus flows in it and therefore also in the associated primary circuit, whose transistor 71 due to the 500 kHz output signal of the NOG gate 53 is conducting, in the short term a larger current, which produces in the first resistor 70 a voltage drop,

whose magnitude corresponds to a logical "1" and which, being at the D input of the opening flip-flop 52, is slightly stored therein. If, on the other hand, there is a logic "1" at the output of the voltage/time converter 46, then the secondary circuit is blocked due to the polarity of the diode, i.e. high-resistive and therefore no significant current can flow. Therefore, also in the case of conducting transistor 71 in the primary circuit of the second isolating transformer 69, no current flows and a logical "0" is stored in the opening flip-flop 52 of the counting chain 33. In parallel with the series circuit of the secondary winding of the second transformer 69 and the first diode 73 is a capacitor 75 for short-circuiting the switch voltage tip. Between the positive pole of the supply voltage

A resistor 76 is connected to Vcc and the base of the transistor 71. In the first transformer circuit 34, a first pole of the primary winding of a first transformer 77 is located above a low-resistance feed resistor 78 connected to the positive pole of the DC voltage Vcc and the other pole receives from the output of the opening gate 51 a 500 kHz clock signal, as an input to this opening gate 51, as already mentioned, is released by the output of the "ramp" flip-flop 50. If this has the logical value "1" then flows in the primary circuit and thus also in the secondary circuit to the first isolation transformer 77 quickly a current, which flows over one with the secondary winding of this, first isolation transformer 77 in the conduction direction in the series-connected second diode 79 a load, which consists of an R/C parallel circuit 80. In this load a voltage drop thus occurs, which corresponds to a logic "1" and which is located at the "ramp" input of the voltage/time converter 46. In this case, as already mentioned, "ramp controller" switches a switched. In parallel with the series circuit of the primary winding for the first isolation transformer 77 and the feed resistor 78 is a third diode 81,. whose cathode is connected to the positive pole of the DC voltage Vcc. The non-diode connected pole of the secondary winding of the first and second isolating transformers 77 and 69 is connected to each other and to the ground point of the voltage/time shaper 46.

The Q output of the opening flip-flop 52 is connected to the opening input of the cascade circuit 47. That of a single line-reduced control bus 43b is connected to the erase input of the latter and the "ramp" flip-flop 50. At the e.g. the twelve parallel inputs of the cascade circuit 47 are located e.g. the binary word "000000011110" and its load input are controlled by a first control gate 82, the first input of which is connected to the Q output of the "ramp" flip-flop 50.

Both the lowest bits of the 12-bit counting chain 33 are not used. It only serves to keep the input coupling error to the output signal of the voltage/time converter 46 small. The following eight bits contain the measured value. The eleventh bit constitutes the sign of the measured value and the twelfth bit is e.g. a control bit....

Appears at the output of the eleventh bit a logic

"1", which happens after 1024 clock pulses or approx. 2 ms, the load input of the binary counter for the cascade circuit 4 7 is activated via a second input to the first control port

82 so that with the next positive edge of the binary counter clock frequency, the cascade circuit 47 is loaded with e.g. the value 1920. With this value, the forward current for producing a minimal ramp in the voltage/time converter 46 is compensated. This value is chosen so that after 128 clock pulses the cascade circuit 47 moves with a position 2048

in the initial position, which corresponds to the zero point of the analogue/digital converter 49. This state constitutes the negative measured value at the end of the range. The corresponding digital value consists throughout of "0" and the sign is "1". Simultaneously with the charging of the binary counter of the cascade circuit

47 sets the output of the eleventh bit above a first input to a second control gate 83 and its clock input also the "ramp" flip-flop 50, which releases the opening gate 51 by means of the Q output so that the ramp clock frequency reaches the first transformer 34 and above this a logic "1" appears at the "ramp" input of the voltage/time converter 4 6 so that its ramp control switching is 'affected' and thus the input to this converter is separated from the input signal and a constant reference current with reversed sign is supplied to the integrator. The integrator output voltage , which until then had a rising course, now falls towards zero and after the fall time reaches the comparator threshold value. With the next positive edge of the counter clock frequency, the opening flip-flop 52 is reset and blocks the number chain. Then the maximum voltage, which reaches the integrator after an integration time t^ , is dependent on the measured value and the slope until the falling ramp is constant is the sinking time t ? proportional to the measured value at the input of the voltage/time converter 46. The measurement of the settling time by means of the counting chain 33 and its 500 kHz clock frequency gives a digital value which shows the analog measured value. Since the same counting chain t is used for the measurement of both times t^ and t_, the advantage is provided that the clock frequency does not have to be absolutely accurate. It must only be constant during the measurement period (t^+ t^)

The described analogue/digital converter delivers e.g. following conditions:

This corresponds to a two's complementary binary code.

All the flip-flops of the counter chain 33 are e.g. of type 74LS74 and all their control ports NOG ports of type 74LS00.

The ramp clock input R of the first transformer circuit

34 is connected via an inverter 84, e.g. of type 74LS06, at the second input of the two-input control gate 83 and has a logical "1" at the D input of the "ramp" flip-flop 50.. In fig. 4 shows the control circuit 24 (from fig. 1), which consists of a microprocessor 85, e.g. of the type 8085 from the company Intel, Santa Clara, California and a control/storage circuit 86. The measured value, count value^ and message output buses 55, 60 and 68 of the preparation circuit 25 (according to Fig. 2) feed the control/storage circuit 86 and are all within this the circuit connected to a common data bus 87. Also the data outputs of a fixed value store 88 and a programmable fixed value store 89 as well as the data connection to a write/read store 90 are at this common data bus 87, which feeds over the data buffer store 91 to the microprocessor 85 the internal bus 92 to latter. The internal bus 92 is in the microprocessor 85

by means of the bus connection connected in the specified order over an address register 93 and an address buffer storage 94 with the address output of the microprocessor 85. The latter controls by means of the bus connection the address inputs to the fixed value storage 88, to the programmable fixed value storage 89, to the write/read storage 90 and to a address decoders 95. These stores and this decoder together form the control/storage circuit 86. Within the microprocessor 85, the internal bus 92 also still controls in the specified order by means of the bus connection over an instruction register 96 and an instruction decoder 97 a control system 98 , whose clock input is at the output of a system oscillator 99 for the microprocessor 85. The control system 98 feeds by means of a bus connection the instruction connection of the address decoder 95, whose bus output on one side controls the control input of the fixed value memory 88, to the programmable fixed value memory 89 and a write /reading warehouse 90 arranged clocks and on the other side the control bus 43b to the preparation circuit 25. The output of the reset circuit 29 is at the reset input 100 of the control system 98 and its clock output at the system clock output 30 and a clock input to the clock of the write/read storage 90. The internal bus 92 of the microprocessor 85 supplies

across a series output circuit. 101 its telegram output 102, which again, as can be seen from fig. 1, a telegram input 10 3 is connected to the remote control transmitter 21. Its baud rate output 104 (fig. 1) is connected to a rate input 105 to the serial output circuit 101.

The serial output circuit 101 contains, among other things, a sample bit encoder for generating parity bits. The internal bus 92 also lies above a bus connection at the data connection to an arithmetic logic unit (ALU) 106 which, among other things, contains an accumulator not shown.

The write/read storage 90 is e.g. of type 81.56 from the company Intel, the fixed value storage 88 e.g. etEPROM 2732 from the same company, the programmable fixed value memory 89 is e.g. built up using a "Dual in line" switch and bus line driver of the type 74LS368 and the address encoder 95 is built up using gates of the "Low Power Schottky" series of the type 74LS.... As serial output circuit 101 can also be used besides the microprocessor 85 a USART, e.g. of type 8251

from the company Intel.

The microprocessor 85 and the storage of the control/storage circuit 86 form a microcomputer, which works as a central control unit for all functions of the subordinate location 2.

In the fixed-value memory 88 is stored the progress program for the microcomputer and in the field-programmable fixed-value memory 89 are stored station-specific values, such as e.g. station number, baud rate, transmission time window, etc. In the write/read storage 90, all digital measurement values, messages and count values are intermediately stored over corresponding input bus connections to the control circuit 24 and the common data bus 87. The latter, as it acts as a train of pulses whose frequency is proportional to the count value, is only buffered after it has been continuously summed up in the accumulator of the arithmetic logic unit 106, i.e. is counted during a specific recording period. After this it will be like this

the supplied frequency stored as a digital value in the write/read memory. 90. -

For safe operation, the microcomputer must have a supply voltage V cc between 4.75 V and ^ 5.25 V. In order to prevent possible incorrect operations at undervoltages, the reset circuit 29 blocks the microcomputer at a supply voltage V < 4.75 V. This reset circuit 29 is not the subject of a patent claim and is therefore not described in more detail.

The digital/data stored in the write/read storage 90 are called up one after the other temporally in the correct time window by means of the microprocessor 85, the serial output circuit 101 arranging the individual bits of the individual data values temporally serially one after the other and adding additional parity bits for testing purposes in a known manner. The individual bits thus reach the telegram output 102 of the control circuit 24 serially in time one after the other. The resulting data telegram is usually arranged in front of the pre-telegram which also consists of a serial bit called from the programmable fixed value storage'89. This contains e.g. indication of the subordinate location and type of the subsequent data. The telegrams to the various subordinate locations 2 are stacked one after the other in time and sent in time multiplex. For this purpose, each transmitter is assigned a time window and programmed into the programmable fixed value store 89. The transmission takes place as a result of the network-synchronous baud rate at the clock input 105 of the serial output circuit 101 network-synchronously.

In fig. 5, the remote control transmitter 21 is shown. Its telegram input 103 controls over an error correction encoder 107 the control input of a logic multiplexer 108 thereby coupling at logic "0" a "0-chirp" signal and at logic "1" a "1-chirp" signal to its data output bus, which is connected via a "chirp" buffer store 109 to the digital input of a digital/analog converter 110.

The output of the remote control transmitter 21 is located at the entrance

to its mains filter 111 and at the same time at the low-voltage mains 16. The mains filter 111 is e.g. a highly selective two-stage active bandpass filter, which is built up using operational amplifiers, e.g. of type LM358. It eliminates all audio frequency energy and remote control signals as well

all disturbances present in the low-voltage network 16 so that at its output and thus the input to a comparator 112 connected to it, e.g. of the type LM311, pure 50 Hz AC voltage appears. The comparator 112 transforms the sine voltage into a square voltage, the frequency of which is increased in the connected frequency doubler 113 to 100 Hz. This,

e.g. built up using two monostable multivibrators of the type 74LS221 and an OR gate 74LS32, feeds a signal input to a phase shifter 114 with e.g. 4 us long square pulses. The output frequency of this phase shifter 114 is, by means of a successive first divider chain consisting in the specified order of a first divider 115,

a second part 116 and a third part 117 divided into two, four respectively. eight so that at the output of the phase shifter 114 to the first divider 115, the second divider 116 and a third divider 117, the bit clock frequencies 100 Hz, 50 Hz and 12.5 Hz appear in the indicated order. One of these bit rate frequencies is selected by means of a first wire bridge 118 soldered to it and supplied to the baud rate output 104, which e.g. is an open collector output. This first chain of parts consists, for example, of of a counter divided by N MC14018.

A first local oscillator 119 with an output frequency of e.g. 204.8 Hz feeds a clock input to the phase shifter 114 as well as the clock input to an address counter 120 and the input to a delay element 121.

The local oscillator 119 is built according to a known electrical circuit using a 4.9152 MHz quartz and several NOG gates, e.g. of the type 74LS04, as the thus generated frequency of 4.9152 MHz is divided into a connected, not shown part, which consists, for example, of a cascade circuit of a split metal counter of the type 74LS92 and a flip-flop 74LS74, with 24 and the the output frequency 204.8 kHz is thus provided.

A binary counter programmable by means of a switch not shown, e.g. of the type 74LS193, counts in the phase shifter 114 a programmed number of periods of this output frequency after this has been previously divided, e.g. in the case of a 50 Hz mains voltage in 341 using a 12-bit binary counter, e.g. of type MC14040. One period of the thus produced 600 Hz frequency corresponds to one twelfth of the 50 Hz mains frequency, i.e. 30°.

After the provision of the programmed number of 600 Hz periods, an output flip-flop is set in the phase shifter 114, e.g. of the 74LS74 type, whose Q output is the output of the phase shifter 114. This output flip-flop is finally reset by the 204.8 kHz output signal of the first local oscillator 119. The 100 Hz input signal of the phase shifter 114 thus appears at its output with a multiple displacement of $ = 30°. Simultaneously with the appearance of this output signal, the input to the phase shifter 114 by means of an internal opening flip-

flop blocked for so long that this is again released by a new positive edge to the 100 Hz input signal. All other components of the phase shifter 114 are reset to their output signal upon the appearance of an output signal. Naturally, the smallest possible phase shift of <p = 30° can be changed to any arbitrary value by choosing a suitable ratio in the first local oscillator 119 and/or in the phase shifter 114.

The output of the phase shifter 114 also feeds a reset input to the address counter 120 and a reset input to a fourth divider 122, which divides the output frequency by e.g. 12.8 kHz in the case of a 50 Hz mains voltage to a second local oscillator 123 with 2 9 = 512 so that the output frequency is 25 Hz. The second local oscillator 123 is e.g. constructed using a 12.8 kHz quartz and several NOG gates of the type 74LS04 according to a known digital engineering circuit. The fourth divider 122 is e.g. a cascade circuit for a 12-bit binary counter of the type MC14040 and a binary flip-flop of the type MC14013.

The 25 Hz output frequency is divided in a downstream second divider circuit chain, which consists in the indicated order of a fifth divider 124, a sixth divider 125, a seventh divider 126

and an eighth divides 127. The fifth divisor. dividing its input frequency of 25 Hz by 1500 so that its output frequency corresponds to a period of 1500/25 = 60 sec = 1 minute. This output frequency is divided by 5 in the sixth divider 125 so that the output period is 5 minutes. The connected seventh divider 126 divides the output frequency of the sixth divider 125 by three so that its output period is 15 minutes and the eighth divider 127 connected after the seventh divider 126 divides the output frequency by two so that an output period of 30 minutes occurs. By means of a soldered-in second wire bridge 128, one of the outputs of the fifth to eighth dividers 124 to 127 is selected and connected via a base resistor 129 with the base of the switching transistor 130 and serves for cyclic calling of the remote control transmitter 21. The fifth divider 124 consists of e.g. e.g. of a cascade circuit of three binary counters of the MC14161 type and the sixth to eighth dividers 125 to 127 of e.g. a respective such binary counter MC14161.

The parallel outputs of the address counter 120 are connected via the bus connection to the address input of a "chirp" fixed value store 131. The output of the delay element 121 is connected to the clock input of the "chirp" buffer store 109

and the digital output value of the logic multiplexer 108 is there delayed short-term stored. In the "chirp" fixed value storage 131, both the "0-chirp" and the "1-chirp" signal are stored and continuously reach a first and a second data input respectively over the respective separated bus connection. the logic multiplexer 108.

The analog output of the digital/analog converter 110 controls the output of the remote control transmitter 21 over a first transmission filter 132, which serves to eliminate the digitizing harmonic wave, a voltage amplification serving driver 133, a power amplifier 134 and a second transmission filter 135 for maintaining the radio interference regulations. The output of the remote control transmitter 21 is connected via a relay contact 136a to the alternating voltage input of a feed device 137, the latter being at the same time at the call input 20 of the remote control transmitter 21. The direct voltage output of the feed device 137 supplies the power amplifier 134 with its feed voltage.

The emitter of the switching transistor 130 is connected to ground and its collector is connected across the relay coil 136b belonging to the relay contact 136a to the positive pole of the DC supply voltage Vcc.

Either the relay contact output signal of the audio frequency energy control receiver 19 over the call input 20 causes the remote control transmitter 21 or the cyclic call signal with periods 1, 5, 15 respectively. 30 minutes at the base of the switch transistor 130 above the relay contact 136a the connection of the feeder 137 and thus the start-up of the power amplifier 134 and the remote control transmitter 21.

The address counter 120 is e.g. of type MC14040, the "chi-rp" fixed value storage 131 of e.g. the type 2716 from the company Intel, and the "chirp" buffer storage 109 e.g. a latch of the type 74LS75. The delay element 121 consists of e.g. two monostable multivibrators of the type 74LS221 and the logic multiplexer 108 of AND gates e.g. of type 74LS08. Both transmission filters 132 and 135 and the digital/analog converter 110 are e.g. constructed using the operational amplifiers of the type LF353. The driver 133 and the power amplifier 134 are built up using bipolar transistors and consist of known circuits from electronics.

The use of the error correction encoder 107 is optional.

It produces e.g. a folding code of class (2,1), i.e.

from each uncoded bit a coded double bit is produced

brought. This is done in a known way and most easily with the help of a shift register. A certain number of these parallel outputs produce, by means of a first exclusive OR gate, the first bit of the double bit and a certain number of other parallel outputs produce, by means of a second exclusive OR gate, the second bit of the double bit.

The transfer allows the following modes of operation:

Normal operation when there are no spontaneous events.

Cyclic telegrams are sent with different repetition times for each transmission channel, thereby avoiding two transmission channels accidentally always sending at the same time. For each telegram a certain probability of collision with other telegrams must be calculated.

General interrogation using an audio frequency energy control call, which also serves as a synchronization signal for transmission channels. Each sender sends their telegram in the time window allocated to them. After such a general inquiry, the transmission channel returns to cyclical normal operation. The latter can be suppressed by corresponding programming and in this case is exclusively transmitted by a general interrogation possibly with further spontaneous transmission.

Spontaneous transfer triggered by a change in the report state. The spontaneous telegram is followed by further telegrams at increasingly large intervals until the transmitter finally switches back to normal operation. Each telegram thereby constantly receives the latest state of the message input signal' and this is not acknowledged.

Synchronous operation. In the case of a system with general polling, the repetition period of all transmitters can be equally programmed. This creates a synchronous cyclic operation. The time control is then online synchronized.

The telegram that forms the electrical signal is on the one hand strongly attenuated in the transmission channel, also in the case of alternating current power supply networks, e.g. by losses in the transverse branches and in the series impedance and above all in the third transformer 15 and on the other hand strongly disturbed by disturbance frequencies, e.g. grid harmonics and/or disturbance-time impulses so that voltage, frequency and/or phase distortions or holes can occur.

This leads overall to relatively poor noise distances (S/N ratio) and conditions for its improvement special measures, e.g. among other things the use of the known "chirp" frequency modulation. This is a frequency modulation whose amplitude envelope is constant during the pulse duration and whose frequency changes according to an arbitrary mathematical function during the duration of the signal pulse. In the following, for the sake of simplicity, it is assumed without limiting the description that this mathematical function is linear. The signal pulse shows e.g. both the logical values "1" and "0" and usually have the same frequency variations. They differ from the classic "chirp" modulation only in that the frequency variation range for both logic values is different and not overlapping and that for one logic value an increasing and for the other a decreasing mathematical function is used. Both logical signal pulses have - as was to be expected with frequency modulation - a very large, theoretically infinite bandwidth. This prevents the operation of several transmitters in the frequency multiplex method on the same transmission path.

An improvement is provided by the use of a modified "chirp" modulation, whose amplitude envelope during a pulse period is no longer constant, but whose working and trailing edges rise and fall continuously, e.g. according to a cosine function. The duration of the flank is e.g. respectively 15% of the period of the signal pulse, as the amplitude envelope becomes constant and has a maximum value for the other 70% of the pulse period. The flank period can e.g. also be 50% of the signal pulse period, the period of the constant maximum amplitude envelope being equal to zero. The last "chirp" modulation is in fig. 6a to fig. 6c compared to the classic 'chirp' modulation. This value for the amplitude envelope of both "chirp" signal pulses "1"

and "0" of a transmission channel is stored in the "chirp" fixed value memory 131.

In fig. 6a is a normalized amplitude envelope U mai, like a classic "chirp" signal pulse A and a modified "chirp" signal pulse B, the latter being shown with respective 50% entry and exit times as a function of time t. In fig. 6b shows the only weakly attenuated, very broadband frequency spectrum D^ of the classic "chirp" signal pulse A as a function of the frequency f. Fig. 6c likewise shows as a function of the frequency f the strongly attenuated and therefore less broadband f frequency spectrum D_, to the changed the "chirp" signal pulse

B.

Transmission channels in the frequency multiplex method that are operated on the same transmission path can be elevated by using overlapping frequency variations for frequency-adjacent single channels on the one hand and on the other hand for both frequency-adjacent logical "1" and "0". This is possible under the assumption that

the mathematical function of both logic values and all transmission channels are either all increasing or all decreasing functions with time,

the transmitted "chirp" signal pulse is network synchronized and suitable demodulators are used in the receiver.

In fig. 7 is shown on the left frequency non-overlapping and on the right overlapping frequency/time diagram of "chirp" signal pulses. The mathematical functions are thereby all assumed to be linearly increasing and the frequency variation AF all e.g. equal to 2 kHz. Two consecutive characteristics form a transmission channel, with the bottom characteristic of a pair of characteristics showing e.g. respectively the "l"-"chirp"- and the upper "0"-"chirp" signal pulse. The "chirp" signal pulse is sent simultaneously starting at the instant t^ and ending at the instant t»

The frequency range f^= 5 kHz to f2= 20 kHz is particularly favorable for the transmission of information over a greater distance in alternating current transmission networks. In this frequency range, with non-overlapping frequency variations, only seven characteristics can be arranged, i.e. 3 1/2 "1/0" channels, but with overlapping frequency variations, on the other hand, fourteen can be arranged, i.e. seven "1/0" channels below the the assumption that the overlap is Af/2 = 1 kHz.

In fig. 8 is shown with curves 8a to 8e the signal ratio

on the transmission path as a function of time t, rightly for the sake of simplicity under the assumption that classic "chirp" signal pulses with steep flanks and constant amplitude envelopes, but with overlapping frequency variation, are used. The baud rate for these curves was chosen equal to 100 Bd. In Europe, however, 50 baud, 25 baud, 12.5 baud and in the USA 120 baud, 60 baud, 30 baud and 15 baud are possible. In fig. 8a shows a clean, noise-free 50 Hz voltage uN to an alternating current grid. Fig. 8b shows the unnoised instantaneous voltage value uT of a "chirp" telegram, which consists of e.g. of a double bit "10". Each bit start is synchronized with zero crossings

to the 50 Hz voltage uN and each has, in the case of a 100 baud clock frequency, the duration of half a period of the 50 Hz voltage uN, i.e. 10 ms. In fig. 8c, the unnoised "chirp" telegram is shown once again, but this time as an instantaneous value f as a function of time.t.

The first bit of logic "1" begins with the frequency f 1 ^ and rises linearly within 10 ms to the frequency f1 . The second bit with logic "0" begins with the frequency f and ends after 10 ms with the frequency f 4/ idet<f>'^<<><f>'2<<><f1>^<<>f4*The frequency variation for both pieces were chosen to be the same size so that the following applies ;<f>'^<_><=><f>'4- f'2*Fig. 8d shows possible highly noisy instantaneous voltage values u Rog fig. 8e possible highly noisy instantaneous frequency values f for the "chirp" telegram, such as those e.g. can appear at the entrance to the remote control receiver 22. In fig. 8d strong noise time pulses are active at location a and strong noise time pulse loops are active at location b. In the bit "1" in fig. 8e, at location c a strong .støyf frequency pulse is active.

In fig. 9 shows details of the one in fig. 1 indicated the remote control receiver 22. The switching converter 10 feeds across the input to this receiver directly the input from its receiver signal preparation circuit 138, the output of which on

in turn controls the signal input of the quadrature demodulator 139. The output of this demodulator 139 is connected directly to the input of a PBF determination circuit 140

(P = energy, B = bandwidth, F = frequency) and whose output is again connected to the signal of a sample and hold circuit 141. The output of the latter directly feeds the analog input of an analog to digital converter 142, whose status output controls the sample and hold switching input of the sample and hold circuit 141 and whose digital output is connected directly via a signal input bus 143 to the signal input of a receiver control circuit 144. The sample and hold circuit 141 is e.g. of type LF398 and the analogue/digital converter 142 of e.g. type AD ADC 80-12 for the company Analog. Devices, Norwood, Massachu-setts, USA. The receiver control circuit 144 controls via a receiver control bus 145 a first control input to the analog/digital converter 14 2 and via a receiver system clock output 14 6 unipolar directly feeds a control input to the demodulator 139. A receiver reset circuit 147 is constructed as the reset circuit 29 to the subordinate location 2 ( fig. 1),

performs the same function and single-pole directly controls a receiver reset input 148 for the receiver control circuit 144.

A 50 Hz resp. 60 Hz low voltage. at the site, to the exchange

1 feeds across an impedance converter 149 with a high-impedance input a sine/square converter 150, whose square-shaped output signal lies directly at the input of an adjustable receiver phase shifter 151. A first output of the latter is connected to a bit synchronization input of the demodulator 139 and a second output to the input of a binary counter 152, whose four parallel outputs feed a counting encoder 153. The output of the latter is connected to a second control input of the analog/digital converter 14 2. The signal output of the receiver control circuit 144 feeds in the specified order over an error correction decoder 155, a sample bit decoder 156 and a receiver buffer store 157 the output of the remote control receiver 22, its "level good" output 158 controls respective first control inputs and its clock output 159 controls respective second control inputs of the error correction decoder 155, the sample bit decoder 156 and the receiver buffer 157.

In fig. 10 is the one in fig. 9. implied receiver signal preparation signal 138 shown in more detail. It consists in the specified order of a cascade circuit to a summing or difference amplifier 161, bandpass filter 162, a signal amplifier 163, a limiting stage 164, a pre-equalizer 165, a fine equalizer 16 6 and an automatic volume control circuit 16 7, the output of the latter being at the same time the output of the receiver signal preparation circuit 138.

The latter has the task of clarifying the reception signals standing at its entrance, possibly very noisy, according to fig. 8d and fig.. 8e so that the signal deformations caused by noise and non-ideal transmission characteristics of the transmission path can be completely or at least partially cancelled. Summing up or the difference amplifier 161 ar works on the one hand as a current/voltage converter and on the other hand forms the sum or the difference of the output voltage or - the current e.g. of several phases to the output signals from the switching converter 10 by means of an operational amplifier, e.g. of type LE353 connected in a known way as summing or differential amplifier. The bandpass filter 162 is e.g.

a multi-stage, similarly known narrowband filter, which can be constructed using several operational amplifiers,

e.g. of the type LF353 and which eliminates all frequency components of the noise that lie outside the bandwidth of the non-noise covered receiver signal.

After an amplification in the preamplifier 163, the receiver signal finally reaches the limiter stage 164. This also consists of an operational amplifier and constitutes an inverting amplifier, whose amplification factor is normally 10, but which can however be reduced to three in a known manner by means of diodes when its input signal is too large, whereby an override of the subsequent circuits is avoided.

The output signal of the limiter stage 164 reaches a spatial distance of e.g. 100 m the first four blocks of the receiver signal preparation circuit 138 from the rest of the plant over a coaxial cable the input to the pre-equalizer 165 connected thereto, whose task is to at least roughly cancel the distortions caused by the transmission path, primarily phase and/or frequency -distortions to the individual frequencies of the transmitted signal as well as resonance peaks or -hole. At the same time as phase hhn. frequency distortion appears as an amplitude distortion, which in turn has a favorable effect on the signal/noise ratio. The pre-distorter has adaptive capabilities, as the remote control transmitter 21 cannot be placed in different places in the alternating current supply network, but also continuously over time this network and its topology can change. For this purpose, each telegram is sent in advance in a series of e.g. ten "1" and "0".

The subsequent fine equalizer 166, e.g. a "linear prediction filter", serves to eliminate all predictable i.e. repetitive noise components, i.e. in particular all periodic noise time pulses ("spikes") as well as grid harmonics. This fine equalizer 166 is only necessary for very strong noise.

It is preferably built up by means of an adaptively controlled analog transversal tilter based on a "charged coupled device" (CCD). The connected automatic volume control circuit 16 7 regulates its input signal with a control constant of e.g. 1 to 10 seconds at a constant level and constitutes a regulator such as is constructed using operational amplifiers of the type LS353.

In fig. 11 shows the quadrature demodulator 139 (Fig. 9)

whose input signal is equal to the preparation receiver signal at the output of the receiver preparation circuit 138 and which is applied to the respective input of first mixer 168,

a second mixer 169, a third mixer 170 and a fourth mixer 171. An auxiliary oscillator 172 is connected to a first reference generator 173 and a second reference generator 174. The first produces e.g. in the same way as the spring control transmitter 21's "chirp" signal pulse, an "1" reference "chirp" signal pulse and the latter a "0" reference "chirp" signal pulse feeding in the specified order a respective first respectively other phase shifters 175 or 176. Each of these 90° phase shifters 175 and 176 has two outputs: the first produces a phase-shifted output signal about 0° and the second one about 90° in relation to the input signal. These four output signals respectively feed the second input to the four mixers and then the 0° phase-shifted output signal of the first phase shifter 175 for the first mixer 168, the 90° phase-shifted output signal of the second mixer 169", the 0° phase-shifted output signal of the second the phase shifter 176 for the third mixer 170 and the 90° phase-shifted output signal for the fourth mixer 171. The output of the first mixer 178 feeds a first input over a first low-pass filter 177, the output of the second mixer 169 feeds a second low-pass filter 178

a second input, the output of the third mixer 170 over a third low-pass filter 179 a third input and the output of the fourth mixer 171 over a fourth low-pass filter 180 a fourth input to an analog demodulator multiplexer 181, the output of which is again connected by a calculation circuit 182 with the output to the demodulator 139. The bit synchronization input of the demodulator 139 is located at respective synchronization inputs for both reference generators 173 and 174.

The analog demodulator multiplexer 181 is bipolar and has two settings: in the first position the first and second inputs are connected to the bipolar output and in the second position the third and fourth inputs are connected to its bipolar output. The control of the position of the demodulator multiplexer 181 takes place via its control input.

At the four mixers 168 to 171, e.g. of the type MC14066, both the respective input signals, i.e. the prepared receiver signal and one of the four reference "chirp" signals are multiplied with each other and the resulting higher frequencies are eliminated by means of the subsequent low-pass filters 177, 178, 179 respectively. 180. The described demodulation is a quadrature detection and uses two separate demodulations, one for the received "1"-"chirp" signal and one for the received "0"-"chrip" signal and for each of the two demodulations two reference signals phase-shifted by 90°. The two resulting demodulation signals show the amplitude of the receiver signal and also its phase position in relation to the reference signal (vectors). At the output of the first and second low-pass filters 177 and 178, the components and 3-^ appear and at the outputs of the third and fourth low-pass filters 179 and 180, the components etg and 3q appear for the vectors. Is the receiver signal a "l"-"chirp" signal then the components and 3-^ dominate, but if, on the other hand, the receiver signal is a "0"-"chirp" signal, then the components ag and (3q have the weight. The value of the vector is thus:

The demodulator multiplexer 181, e.g. of the type LF3201, leads the value pairs (a^, (3^) and (aQ, 3 ) one after the other in time to the calculation circuit 182 which calculates the following value of this:

The calculation circuit 182 is e.g. of type BB4302 from the company Burr-Brown, Tucson, Arizona, USA. At the output of the demodulator 139, demodulated analogue values of the receiver signal are thus produced. Based on these analogue values (see fig.

9) in the following PBF determination circuit 140 at least one of the three parameters power, bandwidth and frequency determined in the form of proportional electrical voltages. These are sensed in the subsequent sample and holding circuit 141 and, during the holding time, are transformed by means of the analog/digital converter 142 into digital values and supplied via the signal input bus 143 to the receiver control circuit 144. The latter is identically constructed to the control circuit 24> for the subordinate site 2 (fig. 2), but here only a single input bus 143 is present instead of its three (55, 60, 68). The receiver control bus 145 thereby corresponds to the control bus 43b (Fig. 1), to the receiver system clock output 146, the system clock output 30 and the receiver reset input 148 for the reset input 100-(Fig. 4). The input corresponding to the clock input 105 of the control circuit 24 is not used here. The digitized receiver value for the signal input bus 14 3 is stored in the write/read memory of the receiver circuit 144

and its microprocessor checks for each bit whether the "1" or "0" "chirp" signal dominates and accordingly stores in a specific cell of this write/read memory a

logical "1" or "0". These logical values are finally read out temporally and serially one after the other and supplied to the signal output of the receiver control circuit 144. At the same time, in contrast to the control circuit 24, a "level good" signal is supplied via the "level good" output 158 and a clock signal via the second clock output 159 to the subsequent circuit and this releases on the one hand the first signal and on the other hand supplies the second signal with a clock frequency. Both signals are produced in the control system for the receiver circuit 144 respectively. prepared.

At the error correction decoder 155, the folding code (2, 1) is decoded and possibly corrected using a known viterbi decoder. Finally, a telegram is thus provided subject in the sample bit decoder 156 to a known parity bit check and, if necessary, corrected to finally be buffered in the receiver buffer storage 157 for further evaluation.

The impedance converter 149 is a non-inverting, e.g. an amplifier built using an operational amplifier LM301 with a gain factor of 1 and a high input impedance. The sine/square converter 150 is a comparator, e.g. of type LM311. The adjustable receiver phase shifter 151 is e.g. structured similarly to the phase shifter 114 for the subordinate site 2, with the difference that a further clock signal is connected via a second output to the clock input of the binary counter 152, which counts its pulses. The count value is then decoded in the count decoder 153 so that the then connected analog/digital converter 142 is released at the right moment.

Claims (11)

1. System for the transmission of digital signal impulses over the wires of an alternating current energy distribution network, predominantly opposite to the direction of flow of cap energy using a "chirp" frequency modulation and the frequency multiplex method as well as a synchronization of the signal generation in a transmitter and the signal processing in a receiver using the frequency of the network alternating voltage characterized in that the frequency variation of frequency-related "chirp" signal pulses partially overlaps. 2. System according to claim 1, characterized in that the working and ending edge of the amplitude envelope of a respective "chirp" signal pulse has a predetermined limited steepness. 3. System according to claim 1 or 2, characterized in that the frequency of the "chirp" signal pulses "1" and "0" are equal functions in relation to time. 4. System according to claims 1 to 3, characterized in that the working and closing edge of the amplitude envelope for the "chirp" signal pulses are cosine functions in dependence on time. 5. System according to claims 1 to 4, characterized in that the temporal duration of the working and closing edge of the amplitude envelope for the "chirp" signal pulses is respectively approximately 15% of the total signal pulse duration. 6. System according to one of claims 1 to 4, characterized in that the temporal duration of the working and closing edge of the amplitude envelope for the "chirp" signal pulses is respectively 50% of the signal pulse duration. 7. System according to one of claims 1 to 6, characterized in that the value for the amplitude envelope for the "chirp" signal pulses is stored in a fixed value storage (131) of a remote control transmitter (21) and that the reference generator (173, 174) of a remote control receiver (22 ) assigned to the fixed value store contains the value of the amplitude envelope of the reference "chirp" signal pulse. 8. System according to claim 7, characterized in that mixers (168 to 171) are arranged in the remote control receiver (22), which multiply the received and prepared "chirp" signal pulses with the reference "chirp" signal pulse. 9. System according to claim 8, characterized in that the amplitude envelope for the reference "chirp" signal pulses has the same temporal course as that of the respective sent "chirp" signal pulses. 10. System according to claim 8, characterized in that the reference "chirp" signal pulse over the total pulse duration has an approximately constant amplitude. 11. System according to one of claims 1 to 10, characterized by a signal transmission in the frequency range from 5 kHz to 20 kHz.