NO780186L - CONTROL DEVICE FOR ELEVATOR SYSTEMS. - Google Patents

Description

Control device for elevator systems.

The invention relates to a control device for an elevator system with several cabins serving a number of floors, comprising group control equipment common to a number of cabins with main floor registration device that generates main floor signals, and cabin control equipment for each cabin with cabin operating apparatus, call registration device and cabin position indicator, of which the latter two generate call and cabin position signals, which control device is connected both to the cabin control equipment and the group control equipment to receive cabin calls and cabin position signals and main floor j esignals.

Overriding control devices for groups of elevators usually strive to maintain car operation to serve the floors of a building regardless of whether the equipment controlling the cars of which an overriding group may fail. This purpose is usually achieved by allocating a separate control equipment for each cabin and common over-determining control equipment in addition to the individual control equipment for controlling the cabins as an over-determining group.

Application of an ordinary computer with capacity for

performing both the control functions for each individual car in addition to the over-determining control functions for groups of cars has gained little traction in the elevator industry despite the desire to achieve the above-mentioned advantage. The costs prevent the use of a separate computer for each cabin in the elevator system for controlling the associated cabin and an additional computer for controlling the cabins in a dominant group. The use of special computers for

elevator systems in this way would require a solution to the problem by transmitting control signals between the overriding computer and each of the computers for the cabins.

Recent developments in the semiconductor industry have led to the inexpensive production of devices such as microcomputers and semiconductor storage devices that can be programmed for a particular application. As a result, the use of a separate microcomputer and a storage device for each cabin in the group, programmed to control the operation of the associated cabin and an additional microcomputer combined with a storage device programmed for the operation of certain cabins as an overdetermining group has become economically possible . The operation of such a control device is dependent on the reliability of the combination of computer and memory for controlling the overdetermining functions by transmitting signals to and receiving cabin control signals from computers and storage devices in connection with each of the cabins in the elevator plant.

The purpose of the invention is to provide a control device of the type mentioned at the outset which provides the above-mentioned advantage on an economic basis.

This is achieved according to the invention by a program storage device which stores control instruction programs for each cabin and for groups of cabins, a cabin processing device which is connected to the program storage device in order to carry out a first set of operations according to each cabin program in order to deliver a first set of cabin control signals in accordance with associated cabin call and cabin position signals and supplying the first cabin control signal to the associated cabin operating apparatus, and a group processing device which is connected to the program storage device and to the cabin processing device to sequentially perform a second set of operations according to each group program to deliver group control signals in accordance with the selected first cabin control signals and main floor call signals to the cabin handling device which supplies other cabin control signals in accordance with the group control signals and distributes the other cabin control signals to the relevant cabin control device f or to put the associated cabin into operation in accordance with the main floor call signals as the overriding group.

Further features of the invention will appear from claims 2-12.

The invention will be explained in more detail below with reference to the drawings. Fig. IA shows a simplified block diagram for part of a control device according to the invention for all cabins in an elevator system for controlling these as an overdetermining group. Fig. IB shows a simplified block diagram for part of the control device according to the invention with a single cabin in an elevator system for controlling the relevant cabin. Fig. 2 shows a simplified connection core for some main floor call circuits in the group control equipment for an elevator system according to the invention. Fig. 3A and 3B show simplified connection diagrams for part of the main floor call selection circuits for the control device according to the invention in connection with the main floor call circuits in fig. 2. Figs 4, 5 and 6 together show a simplified circuit diagram for part of the circuits in the control device according to the invention for the delivery of control signals to a system of elevator cabins as an overdetermining group. Figs. 7, 8, 9A and 9B together show a simplified connection diagram for the signal transmission equipment for connecting the part of the control device shown in fig. 4,5 and 6 with the circuits in each of the cabins. Fig. 10 shows a simplified connection core for the signal transmission circuits in connection with a single cabin to connect the circuits shown in fig. 7,8,9A and 9B with the relevant cabin's control circuits. Figs 11, 12 and 13 together show a simplified connection diagram for the control circuit belonging to a single cabin for generating signals for controlling the relevant cabin.

Fig. 14 shows a simplified connection core for a

part of the cabin call selection circuit in the control device according to the invention in connection with a single cabin.

Fig. 15 shows a simplified connection core for some of the cabin call circuits for a single cabin. Fig. 16 shows a simplified connection core for a cabin control signal selection circuit for a single cabin. Fig. 17 shows a simplified connection core for a cabin operating device for a single cabin. Figs. 18A18B and 18C show wiring diagrams for the connection circuits shown in Figs. 2, 15 and 16. Fig. 19 shows a time diagram for some of the signals produced in the control device according to the invention.

The control device in fig. IA and IB are used for an elevator system with a number of cabins a,b,....h which serve several floors in a building not shown. The control device includes a group control device GCE which is common to all cabins, and cabin control device CCE(a) for a cabin a. The control device includes a group processing device GPM, the cabin processing device CPM, both of which are surrounded by dashed lines, and program storage devices GROM and CROM (a).

The group treatment device GPM and the cabin treatment device CPM comprise a number of circuits which are connected by lines of two thicknesses. The thin lines represent individual signal lines connecting the circuits and the thick lines indicate a number of signal lines connecting the circuits. Both types of signal lines shown in fig. IA and IB are also provided with arrow heads that indicate the desired direction of the signal flow between the different circuits. The designations that also have small letters in parentheses refer to circuits that belong to the respective cabins in the elevator system.

The group treatment facility GPM includes a

group signal processors GPU and an associated group of logic circuits associated with the group program storage device GROM, the group control equipment GCE and the cabin processing device CPM. The bidirectional signal line GDØ-7 connects the group processor GPU with the associated group logic circuits comprising the group cabin logic circuit G/C, the group data storage device GRAM and the group register GR. The output line GAØ-15 from the group register GR with the group cabin logic circuit G/C, the group data storage device GRAM, the group program storage device GROM and the group equipment selection circuit

GESC.

Wires GIO-7 and GDOØ-7 connect the group program storage device GROM and group data storage device GRAM to the group switch device GS and wire GDØ-7 connects the group switch device GS to the group processor GPU.

Individual signal lines 1HU, 2HD...THD connect the group control equipment GCE with the group equipment selection circuit GESC

to receive signals representing registered main floor calls and supply these via the line GDØ to the group handler GPU. In addition to this, the group processor GPU supplies signals via the line GDØ to the group equipment selection circuit GESC for the transmission of main floor call reset signals via the line 1HU, 2HD....THD to the group control equipment

GCE.

As shown in fig. IA, wires DTØ(a), DTØ(b)...DTØ(h) connect the logical group cabin circuit G/C individually to the logical cabin group circuits C/G(a), C/G(b) and C /G(h^i which are parts of the group processing device. For simplicity, the cabin group logic circuits for cabins c-g are not shown. In addition, seven signal lines DT1-DT7 connect the cabin group logic circuit G/C with each of the cabin logic circuits group circuits.

Three additional signal lines XCRDY(a), XCRDY(b) and XCRDY(h) are shown in fig. IA but it is clear that similar wiring is arranged for the cabins c-g, but for the sake of simplicity not shown in the drawing. These wires connect the logical group cabin circuit G/C with the logical cabin group circuits C/G(a) etc. The logical group cabin circuit G/C is also connected via the wire GSUS to the group processor GPU.

The cabin treatment device CPM in fig. The IB comprises a cabin processor CPU(a) and associated cabin logic circuits which are shown as a number of rectangular blocks connected between the cabin processor CPU(a), the cabin program storage device CROM(a), the cabin control equipment CCE(a) and the cabin logic group circuit C/G(a ). However, corresponding circuits are provided for the cabins b-h.

Bidirectional signal lines CDØ(a) - CD7(a), connect the cabin processor CPU(a) with the cabin data switching device SW(a) and the cabin register CR(a). The output wires CAØ(a)-CA15 from the cabin register CR(a) connect this to the cabin data switching device SW(a), the cabin program storage device CROM(a) and the cabin equipment selection circuit CES(a). The cabinda.taom switching device SW(a) is also connected to the cabin logic group circuit C/G(a) via the wires GCAØ(a)-GC7(a), GCDØ(a) - GCD7(a) and DTS(a) . In addition to this, the cabin data switching device SW(a) is connected via the lines CIOØ(a)-CI07(a) to the cabin program storage device CRAM(a) and via the lines CD00(a)-CD07(a) to the cabin data storage devices CRAM(a). The cabin processor CPU(a) is connected to the logical cabin group circuit C/G(a) via the wire CSUS(a).

In the following description of the individual parts of the control device according to the invention, the signal level binary "1" is denoted by L10 and the signal level binary "0" is denoted

with HL1. Furthermore, several signal lines are shown on more than one figure and in that case the figure number where the line also appears has been added after the line designation in parentheses.

The main floor registration circuits use gas discharge tubes with cold cathode as operating buttons 1HU, 2HD... THD as shown in fig. 2 and for the main floor and floors 2-6, 7-11 and 12-T are also used such as shown in U.S. Patent No. 3,614,995 and to which reference is made here for the sake of simplicity. Each of these tubes is connected to a terminal II in an optical coupling converter 18A as shown in fig. 18A and shall be described in more detail in connection with this. Each optical coupling converter 18A is also connected to line BO and line AC1 in feeder PSI. The feeding device PSI delivers a voltage of approx. 95 volts on line AC1 in relation to line BO and a voltage of approx. 150 volts on the wire BO in relation to ground. Por operation of the main floor call circuit, the voltage between lines AC1 and BO and lines BO and ground is 180° out of phase with each other.

Each of the gas discharge tubes conducts current from the wires B+ - BO when a person touches the push button. This represents a main floor call for that floor by applying increased voltage from the cathode of the tube to the input terminal II of the optical switching converter 18A which supplies a binary signal "0" to the wire connected to the output terminal S. To delete a registered main floor signal, a binary signal "0" supplied via the reset line 1HUR, 2HUR...THDR to the reset terminal R in the associated optical coupling converter r which is connected to a conductive gas discharge tube. In response to the binary signal "0" applied to the reset terminal, the anode voltage in the tube will decrease to a value less than the holding voltage and the tube will go out so that the recorded call is deleted. Call signals for floors higher than the main floor are supplied via lines 1HUS, 2HUS j 6HUS, 7HUS, 11HUS and 12HUS to inputs 12,13,2,3,14 and 15 in pairs of main floor selectors 30 and 32 (fig. 3A). Similarly, call signals from floors lower than the main floor are supplied via lines 2HDS, 6HDS, 7HDS, 11HDS, 12HDS and THDS to inputs 13,2,3,14,15 and 4 of the second pair of main floor call selectors 34 and 36 (Fig. 3B ). Additional main floor call signals are fed to other inputs. Each of the outputs 5 in the four main floor selectors 30,32,34 and 36 is connected

with a common wire GDØ for transmitting a binary signal to the group processor GPU (Fig. 4) corresponding to a selected main floor call. The main floor call, which causes the corresponding binary signal to be transmitted via the line GDØ, is selected by supplying a three-bit binary signal on the lines GAØ, GA1

and GA2 to the selector inputs 9,10 and 11 in one of the four selectors and a binary signal "0" via the wires EU1, EU2, EDI or ED2 to the control input 7 in one of the four selectors as will be described in more detail below.

Wire GDØ is also common to the inputs 13 of four eight-bit addressable latch circuits used as main floor call reset signal selectors 38,40,42 and 44 (Figs. 3A and 3B). A main floor reset signal is applied selectively from one of the outputs 5,6,7,9,10,11 or 12

to one of the four selectors via the lines 1HUR, 2HDR....THDR to the reset terminal of a selected optical switching converter l8A as a result of a reset signal applied to the input 13 of the relevant selector via the line GDØ and as a result of a three-bit binary signal which via the lines GAØ, GA1 and GA2 are supplied to the data selector inputs 1,2 and 3 in the corresponding reset circuit 38,40,42 or 44 and a binary signal "0" which via the lines EU3, EU4, ED3 or ED4 is supplied to the control input 14 of the selected selector.

Transmission of recorded main floor calls and reset signals takes place by means of a pair of decoding

and demultiplexer units 46 and 48 which are used as selectors.

The first of these 46 has input terminals 2 and 14 which are connected via the wire GEXØ to an external connection circuit 72 (fig. 5). Wires GRX and GWX connect inputs 1 and 3

with the circuits in fig. 5 while the input 15 retains ground potential. In addition to this, the wire GA3 connects the input terminal 13 in the unit 46 with group registers GR (Fig. 4). As a result of signals supplied to the inputs of the unit 46, a binary signal "0" is supplied from the output 11 or 12 via the lines EU3 and EU4 to the input 14 of the main floor reset unit 38 resp. 40 or from outputs 6 and 7 via lines EU2 or EU1 to input 7 in the main floor registration unit 30 or 32 in fig. 3A.

The second decoding-demultiplexer unit 48 of FIG. 3B is put into operation as a result of a binary signal "Q" via the line in GEX1 from the unit 72 of FIG. 5 to inputs 2 and 14. Inputs 15,3,13 and 1 in unit 48 are via line HL1,

GWX, GA3 or GRX connected to ground potential. This unit works in the same way as the unit 46 described above to supply a binary signal "0" to the inputs 7,6 or 11, 12. The unit 48 supplies a binary signal "0" from the output 7 or 6 via the wire EDI or ED2 to the input 7 in the main floor j eancall registration signal unit 36 resp. 34 or from output 11 or 12 via line ED3 or ED4 to input 14 in the main floor reset unit 42 or 44.

Figs. 4, 5 and 6 together show a simplified connection diagram for the mutual connections between the group processing device GPU and the associated circuits and comprise six eight-bit data registers, an eight-bit accumulator, two eight-bit temporary registers, a storage device for storing program and subroutine addresses and a eight-bit parallel binary arithmetic unit that can perform addition, subtraction and logic operations. Each of these operations is performed in a predetermined number of time states or machine periods Tl, T2, T3, T4, T5, TII, WAIT and STOP which each require two time periods of a timing control signal applied to inputs 16 and 15 of the group processing unit GPU provided by the oscillator 50 with a frequency of 800 kHz. The oscillator 50 (Fig. 4) can be of any type which delivers a pair of complementary pulses with a repetition frequency of 800 kHz and has a pulse width of half its period. These pulses are supplied via the lines G01 and G02 to the input 16 resp. 15 in the group manager GPU. These pulses have a form shown in the timing diagram of fig. 19 and are designated G01 and G02. As a result of supplying these pulses to the group processor GPU, this delivers a pulse signal with a repetition frequency of

about. 400 kHz with a pulse width of half its periods on the output 14 via the line GSYNC to external logic group circuits. The signal supplied via the line GSYNC has a form indicated by the curve GSYNC in fig. 19- The wires GSØ, GS1, GS2 connect the outputs 13,12 and 11 of the group processor with the inputs 3)2 and 1 of a three to eight line decoder 70.

A normally open switch GST has one terminal connected to wire HL1 and another terminal connected to input 18 of the group manager GPU and is manually operated to the closed position to reset the internal program counter in the group manager to zero. The line GSUS is connected to the input 17 of the group processor GPU and with logical group circuits in fig. 9A which will be described in more detail below.

As shown in fig. 4 connects the wires GDØ, GDI... GD7 group processor outputs 9,8,...2 to a pair of 4-bit parallel bidirectional drive units 54 and 56. Outputs 3,6,10 and 13 from these units 54 and 56 is via wires GDØ, GD1...GD7 connected to inputs 2,3,6 and 7 for the transmission of an 8-bit address signal and an 8-bit code signal in four bistable locking circuits 58,60,62 and 64. The four locking circuits 58 ,60,62

and 64 corresponds to the group register GR in fig. IA as indicated in fig. 4. The lines GW, GDI....GD7 are also connected to outputs 4,7,9 and 12 in a pair of data selectors/multiplexers 66 and 68 which are designated as group control switch GS in fig. IA and 4. They transmit group data signals via lines GDØ-GD7 from the group data storage device GRAM (Fig. 6) and group processing instruction signals from the group program storage device GROM to the inputs 3,6,10 and 13 of the units 54

and 56. The wires GDØ, GD1...GD7 are connected to circuits indicated in parentheses, e.g. with the inputs in a number of converters in fig. 6 whose outputs are connected to the data storage device GRAM in fig.6.

The bistable latch circuits 58 and 62 in group registers

GR receives 8-bit address signals on inputs 2,3,6 and 7 and delivers the complement of these signals on lines GAØ, GA1...GA7 to the circuits of fig. 6 as a result of a binary signal "1" via wire GT1 on time control inputs 4 and 13-

The bistable latch circuits 60 and 64 in group registers GR receive 8-bit code signals on inputs 2,3,6 and 7 and supply corresponding and complementary signals on lines GA8, GA9... GA15, GA8, to the logical group circuits of fig. 5,6,7,8,9A and 9B as a result of a binary signal "1" on timing inputs 4 and 13 via line GT2.

The lines GSS, GSR, GCS and GD1EN are connected to the control inputs 1 and 15 in the data selectors 66 and 68 and the drive circuits 54 and 56 connect these inputs to the circuits in fig. 5

as will be described in more detail below.

The group processor GPU supplies a 3_bit binary coded time identification signal on the lines GSØ, GS1 and GS2 from the outputs 13,12 resp. 11 to the selection inputs 1,2 and 3 in the decoding/demultiplex circuit 70 (fig. 5) > The decoder 70 is used as a 3-8-line decoder which delivers signals via the lines GT2, GT1, GTli and GT3 from the outputs 14,13,12 and 11 to the logic group circuits shown in Figs. 4, 5 and 9A.

The wires GA14 and GA15 connect the selection inputs 2 and 3 of the 2-4 line decoder 74 (fig. 5) with the Q outputs 11 and 8 of the bistable latch circuit 54 (fig. 4). The decoder 74 has two additional selection inputs 14 and 13 which are connected via the lines GA10 and GAU to the Q outputs 11 and 8 in the bistable latch circuit 60 (fig. 4). The control inputs 1 and 15 in the decoder 74 are connected to ground by means of the wire HL1 and by means of the wire GA13 to the output 14 of the bistable latch circuit 64.

The decoder 74 supplies a group storage selection signal at the output 10 which is supplied via the line GSS to the selection input 1

in a pair of data selector circuits 66 and 68. Two additional outputs 11

and 12 are connected to the inputs 13 and 12 in an AND gate circuit 80D with two inputs whose output 11 via the line GRSE is for-

tied with two inputs 18 and 19 in a 4-16 line decoding demultiplexer 90 (Fig. 6).

The output 11 of the AND gate circuit 80D is also connected to the input 2 of a NAND gate circuit 84A whose other input 1 is connected to the output 10 of the decoder 74. The output 3 of the NAND gate circuit 84A is connected to the input 5 of a NAND gate circuit 84B with two inputs whose second input 4 is connected via the wire GRX to the output 3 of the AND gate circuit 80A as shown at the top right of fig. 5- The NAND gate circuit 84B supplies a group storage read signal via line GRS to the control output 15 of a pair of data selectors 66 and 68 (Fig. 4).

One half 78B of a dual flip-flop circuit

is connected with its input 7 to the output 8 of a NAND gate circuit 84C with two inputs 9 and 10 which are connected to the outputs 2 and 8 of a pair of inverters 86A and 86D. Wires GPCW and GT3 connect the inputs 1 and 9 of the two inverters 86A and 86D to the respective output'7 of the 2-4 line decoder 74

and with the output 11 of the 3-8 line decoder 70. The half 78B has a reset input 8 connected to the output 4 of the inverter 82B whose input 3 via the line G01 is connected to the output of the oscillator 50. The input 9 and the timing control input 6 of the flip-flop circuit 78B is maintained at binary level "0" as indicated by HL1 and input 12 is maintained at binary level "1" as indicated by LIO. The flip-flop circuit 78B supplies an input signal from the Q output 11 via the line GWX to the input 3 of the selectors 46 and 48, and to the inverter 82A which is connected to the input 20 of a pair of read-only storage devices 96 and 98 (Fig. 6) which will be described in more detail below.

A pair of flip-flop circuits 76A and 76B is shown in the upper right of FIG. 5- Wires GT1I and GT2 connect the setting input 10 and the timing control input 11 of the flip-flop circuit 76B with the outputs 12 and 14 of a 3-8 line decoder 70. The wire L10 connects the reset input 13 with a binary signal level "1" and the wire HL1 connects the data input 12 with a binary signal level "0". Line GCS connects the Q output 9 of the flip-flop circuit 76B to the select input 1 of the bidirectional drivers 54 and 56 (Fig. 4).

The flip-flop circuit 76A has the reset input 1 and the timing input 3 connected via lines GT3 and GT2 to the outputs 11 and 14 of the 3-8 line decoder 70. The D input 2 and the setting input 4 are connected to a binary signal level "1" via the line L10. The Q output 5 of the flip-flop circuit 76A is connected to the input 9 of a two-input AND gate circuit 80C. This gate circuit also receives a pulse signal on the input 10 via the line GSYNC.

Output 8 of the AND gate circuit 80C is connected to input 4 of the two-input AND gate circuit 80B, to input 2 of the AND gate circuit 80A, and to input 11 of the inverter 86E. AND gate circuit 80B also receives a signal at input 50 via line GPCW from output 7 of 2-4 line decoder 74 and supplies a signal from output 6 via line GDIEN to control input 15 of bidirectional driver circuits 54 and 56. AND gate circuit 80A also receives a second signal on input 1 via wire GA14 from output 10 of the bistable latch circuit 64 and supplies a signal via wire GRX to input 4 of the AND gate circuit 84B.

3-8 the line decoder 72 of fig. 5 has two inputs 4 and 5 connected to the output 9 of the 2-4 line decoder 74 and the third input connected to a binary signal level "1" represented by the line L10. Lines GA4, GA5 and GA6 connect outputs 8,11 and 14 of the bistable latch circuit 62 to inputs 1,2 and 3 of the 3-8 line decoder 72 to supply a binary signal level "0" via one of the lines GEXØ, GEX1... GEX7 which is connected to outputs 15,14,13,12,11,10,9 and 7-The part of the program storage device-which is assigned to the group processor GPU (fig. 4) and indicated in fig. IB as the group program storage device GROM, is in fig. 6 shown as a pair of read-only storage devices 92 and 94. It should be noted that the number of such devices varies with the size of the program to be stored. Each of the twelve units has its address inputs 3,2,1,20, 21,19,18 and 17 connected in parallel with outputs 1,14,11 and 8 of the bistable latch circuit 58 and outputs 1,14,11 and 8 of the bistable locking circuit 62 via wires GAØ, GA1, GA2, GA3, GA4, GA5, GA6

and GA7 in such a way that the two devices 92 and 94 as shown

on fig. 6 is connected to circuits 58 and 62.

Each of the twelve units also has its data output 4, 5,6,7,8,9,10 and..11 connected in parallel with the wires GIOØ,

GI01, GI02, GI03, GI04, GI05, GI06 and GI07 which are connected to inputs 3,6,10 and 13 in the data selector pair 66 and 68. In

in addition, each of the twelve devices with the selection input 14 is separately connected to one of the outputs 1,2,3,4,5,6,7,8, 9,10,11 and 13 in the 4-16 line decoder demultiplexer 90.

4-16 line decoder/demultiplexer 90 decodes four binary coded signals supplied to inputs 23,22,21 and 20 via lines GA8, GA9, GA10 and GA12 from outputs 1,14 and 11 of the bistable latch circuit 60 and from output 1 of the bistable latch circuit 64 and supplies a binary signal level "0" on

one of its twelve outputs 1-11 and 13 when a binary signal "0" via line GRSE is supplied to inputs 18 and 19 from output 11 of the AND gate circuit 80D (Fig. 5).

At the top of fig. 6 shows the part of the logic group circuits to be described below. Each of the pair of units 96 and 98 in FIG. 6 with its address inputs 4, 3,2,1,21, 5,6 and 7 is connected in parallel with the group address section in the group register GR (fig. 4) via the lines GAØ, GA1, GA2, GA3, GA4, GA5, GA6 and GA7. Random access storage device 96 has data inputs 9,11,13 and 15 connected to outputs 2,4,6,8 of inverters 98A, 98B, 98C and 98D. The wires GDØ, GDI, GD2 and GD3 connect inputs 1,3,5 and 9

in the inverters 98A, 98B, 98C and 98D with outputs 3,6,10 and 13

in the two-way drive circuit 54 as shown in fig. 4. Similarly, inputs 9, 11, 13 and 15 of random access storage device 98 are connected to outputs 2, 4, 6 and 8 of inverters 100A, 100B, 100C and 100D. Wires GD?, GD5, GD6" and GD7 connect inputs 1, 3, 5 and 9 of inverters 100A, 100B, 100C and 100D to outputs 3, 6, 10 and 13 of bidirectional driver circuit 56 as shown in Fig. 4.

The reading input input 20 in the storage devices 96 and 98 is connected to the output 2 in the inverter 82A. The wire GWX connects input 1 in the inverter. 82A with the output 11 of the flip-flop circuit 78B as shown in FIG. 5- The output 18 and 19 in each of the circuits 96 and 98 are both connected to the output 10 in the 2-4 line decoder 70 (fig. 5) via the wire GSS. The input 70 of the circuits 96 and 98 is connected to a binary signal level "1" via the line L10.

At the top left of fig. 7 shows a pair of data selector multiplexes 100 and 102. The first pair of inputs 2, 5, 11 and 14 in the data selectors 100 and 102 are connected via lines GAØ, GA1...GA7 with the outputs 1, 14, 11 and 8 in the bistable latch circuits 58 and 62 as shown in fig. 4. The second pair of inputs 3, 6, 10 and 13 in the data selectors 100 and 102 are connected via wires GDØ, GD1...GD7 to the outputs 3,6,10 and 13 in the two-way drive circuits 54 and 56 as shown in fig. 4. Wire GCDT connects select input 1 of data selectors 100 and 102 to output 11 of flip-flop circuit l80B (Fig. 9A)

and forms part of a data transmission signal generator which will be described in more detail below.

Output 4 in data selector 100 is connected to inputs 2,5,11 and 14 in each of a second pair of data selector multiplexes 116 and 118. (Fig. 7) - Output 4 in data selector 100 is also connected to input 3 in data selector 116. The outputs 7,9 and 12 in the data selector 100 are connected to the inputs 6, 10 resp. 13 in the data selector 116. The outputs 4,7,9 and 12 in the data selector 102 are connected to the inputs 3,6,10 resp. 13 in the data selector 118. The wire G8B connects the selection input 1 in the data selector 116 and 118 with output 6 in the inverter 170C (fig.9B) which will be described in more detail below. The wire GA13 connects the input 15 in the four data selectors 100, 102, 116 and 118 with the output 15 in the bistable latch circuit 64 (Fig. 4).

The outputs 4 and 7 in the data selector 116 (fig. 7) are connected to the input 6 or 11 in the differential line drive circuit 122. The outputs 9 and 12 of the data selector 118 are connected to the inputs 6 and 11 of a second differential line drive circuit 125-Although not shown in FIG. 7, it is understood that the second additional differential line drive circuit is connected in the same way to the outputs 9 and 12 of the data selector 116 and to the outputs 7 and 4 of the data selector 118.

The upper half of the differential line drive circuit

122 delivers signals on outputs 2 and 3 via wires DTØ(a) and DTØ(a) to inputs 11 and 9 in the differential line receiver

. 236(a) (Fig. 10). It is clear that the circuits of fig. 10 only is

assigned to cabin a and that similar circuits are assigned to each of the other cabins in the facility. The outputs 14 and 13 in the differential line drive circuit 122 are thus connected by lines DTØ(b) and DTØ(b) with logic circuits assigned to cabin b, and the same applies to the other cabins in the facility. The differential line drive circuit 125 is connected with outputs 2, 3jl4 and 13 to two-way signal transmission lines DTØ(g), DTØ(g), DTØ(h) and DT^(h') for cabins g and h.

Four additional differential line drive circuits 126, 128, 130 and 132 are also shown in FIG. 7- The input 6 in the line drive circuit 126 is connected to the output 7 in the data selector 100. The other two outputs 9 and 12 in the data selector 100 are connected to the input 11 resp. 6 in the line drive circuit 128. Outputs 4 and 7 in the data selector 102 are connected to inputs 11 and 6 in the line drive circuit 130. Outputs 9 and 12

in the data selector 102 is connected to the inputs 11 and 6 of the line drive circuit 132. The differential line drive circuits 126, 128, 130 and 132 supply signals via the "line DT1, DT1...DT7 and DT7 to the inputs of the differential line receivers 2360a), 238(a), 240( a) and 242(a) as shown in Fig. 10 and form part of the logical group circuits which are assigned to cabin a. It is clear that these wires are connected by circuits corresponding to those in Fig. 10 which are assigned to each of the additional cabins in the facility.

The two-way signal transmission wires DTØ, DTØ for each cabin and the wires DT1, DT1,DT2...DT7, DT7 which are common to all cabins are also connected to the inputs of a number of differential line receivers l60, l6l, 162 and 163, 150, 152, 154 and 156 as shown in fig. 8. The lines DT1 and DT1 are connected to the inputs 11 and 9 of the differential line receiver 150. The output 15 of the differential line receiver 150 is connected to the input 6 of the data selector multiplexer 156. In a similar way, the signals on the lines DT2, DT2, DT3 and DT3 are connected to the differential line receiver 152 for

to supply signals to inputs 10 and 13 of the data selector 156. The remaining eight signal lines DT4, DT4, DT5, DT5, DT6,

DT6, DT7 and DT7 are connected to the inputs of the differential-line receivers 154 and 156 whose outputs are connected to the inputs

times 3,6,10 and 13 in a second data selector mutliplexer 158

as shown in fig. 8.

Four additional differential line receivers 16O-I63

is also shown at the top right of fig. 8. Inputs 11,9,

5 and 7 in each of the differential line receivers 160,163 are connected to the two-way signal transmission lines DTØ and DTØ in two cabins.

The differential line receivers 160-163 supply the complement of signals which are applied to their inputs to a pair of data selectors 156 and 158 as shown in fig. 8. Outputs 15 and 1

1 the differential line receiver l60 is connected to the input

2 and 5 in the data selector 156. The outputs 15 and 1 in the differential-line receiver 16l are connected to the input 11 resp. 14 in the data selector 156. Outputs 15 and 1 in the differential line receiver 162 are connected to inputs 2 and 5 in the second data selector 158. Furthermore, outputs 15 and 1 in the differential line receiver 163 are connected to input 11 resp. 14 in the data selector 158.

The output signals from the differential line receivers

I60-I63 are also applied to the inputs of an 8-1 line data selector multiplexer 164 (Fig. 8). The common outputs 15 and 1 in each line receiver are connected to different inputs in the data selector 164. Output 5 in the data selector 164 is connected to input 3 in the data selector 156. Lines GA10, GA9 and GA8 deliver a 3_bit binary coded selection signal from the outputs

11, 14 and 1 in the bistable latch circuit 60 shown in fig.

4 to the selection inputs 9, 10 and 11 in the decoder 164. The control input 7 in the decoder 164 is connected via line GA13

to the output 15 in the bistable latch circuit 64 in fig. 4.

The first or second cabin control signal received

of the group processor GPU (fig. 4) is supplied via lines GDØ, GD1...GD7 from the data selector pair 156 and 158 (fig. 8) to the drive circuits 54 and 56 (fig. 4). Leads GRCE and G8B connect outputs 15 and data select inputs 11 of data selectors 156 and 158 to output 8 of NAND gate circuit 174C (Fig. 9A)

and the output 9 in the data selector 200 (fig. 9B) which will be described in more detail below.

Fig. 9A shows a simplified connection core for a

part of the logical group circuits to be described below as group interruption signal generator. The line GD5 connects the output 6 of the two-way drive circuit 56 (Fig. 4) with the input 1 of the inverter 170A and with the input 16 of the flip-flop circuit 172A. The setting input 2 of the flip-flop circuit 172A is connected to a binary signal level "1" represented by the line L10. Timing input 1 of flip-flop circuit 172A is connected to output 4 of inverter 170B whose input 3 is connected to output 6 of three-input NAND gate circuit 174B.

The NAND gate circuit 174B, with input 3, is connected via line G01 to the oscillator 50 with a frequency of

800 kHz (Fig. 4). A second input 4 of the NAND gate circuit 174B is connected to the output 12 of an inverter 176F whose input 13 is connected to the output 14 of the group processor GPU (Fig. 4) via the line GSYNC. The third input 5 of the NAND gate circuit 174B is connected to the output 3 of a pair of NAND gate circuits 178A and 178C forming a flip-flop circuit.

The output 3 of the NAND gate circuit 178A is also connected to the input 9 of the NAND gate circuit 178C whose second input 10 is connected via the wire GT2 to the output 14 of the 3-8 line decoder 70 (Fig. 5). Output 8 of NAND gate circuit I78C is connected to input 2 of NAND gate circuit I78A whose second input is connected via wire GT1 to output 13 of 3-8 line decoder 70.

Input 3 of flip-flop circuit 172A (Fig. 9A) and input 2 of flip-flop circuit 180A are connected to output 12 of a three-input NAND gate circuit 174A. The line GSYNC connects the input 1 of the NAND gate circuit 174A and the timing control input 1 of the flip-flop circuit 18OA with the output 14 1 of the group processor GPU (Fig. 4). The remaining two inputs 2 and 13 of the NAND gate circuit 174A are connected to the Q outputs

15 and 11 in the two parts 180A and 180B of a flip-flop circuit.

The Q output 15 of the flip-flop circuit 180 is also connected to the timing control input 6 of the flip-flop circuit 180B. Furthermore, the Q output 11 of the flip-flop circuit 180B is connected to the input 11 of the NAND gate circuit 174C and via the line GCDT with the select input 1 of the data selector pair 100 and 102 (Fig. 7) and with the select input 1 of the data selector 200 (Fig. 9B ).

Reset inputs 3 and 8 of flip-flop circuits 180A and 180B are connected to output 11 of dual-input NAND gate circuit 178D. One input 12 is connected to the Q output 14 in the flip-flop circuit 172A and the other input 13 is connected via the line GA13 to the output 15 in the bistable latch circuit 64 (Fig. 4). The wire GSUS connects the Q output 14 to the input 17 of the group processor GPU. Inputs 4, 16, 9, 12 and 7 of flip-flop circuit 180A and input 2 of flip-flop circuit 172A are held at a binary signal level "1" represented by line L10.

The NAND gate circuit 174C is connected with the input 11 to the Q output 11 of the flip-flop circuit 180B. The wire GA13 connects its input 10 with the output 14 of the bistable latch circuit 64 (Fig. 4). Wire GRX connects input 9 to output 3 of AND gate circuit 180A (Fig. 5).

The upper half of fig. 9B shows a simplified circuit core for the part of the logic group circuits to be described in more detail below as the cabin interrupt signal generator. The wires GA8, GA9 and GA10 connect the outputs 1, 14 resp. 11 in the bistable latch circuit 60 (fig. 4) with the inputs 1,2 resp. 3 in a binary decoder 190. The decoder 190 has three inputs of which 2, 4 and 5 are connected via the line GA13 to the output 15 of the bistable latch circuit 64. The third input 6 is connected to a binary signal level "1" represented by the line L10 .

The outputs 15,14,13 and 12 of the decoder 190- are connected to the inputs 3,6,10 and 13 of the data selector multiplexer 192.

The other four outputs 11, 10, 9 and 7 in the decoder 190 are connected to the inputs 3,6,10 and 13 in a second data selector 194. The two data selectors 192 and 194 are with their second setting input 2,5,11 and 14 connected to ground potential represented by line HL1. Both data selectors 192 and 194 are connected to the control input 15 via wire GA13 with output 15 in the bistable latch circuit 64 and data selector input 1 is connected via wire GAU to output 8 in the bistable latch circuit 60. Outputs 4 and 7 in the data selector 192 are connected to common inputs 9,10 and 7,6 in the differential-line drive circuits 196AjI96B. In the same way, the outputs 9 and 12 of the data selector 194 are connected to common inputs 9

and 10 and 7 and 6 in a second differential line drive circuit 198A and 198B.

Outputs 9 and 12 of data selector 192 and 7 and 9 of data selector 194 are similarly connected to two differential line drive circuits (not shown). The outputs 13 and 14 of the differential line drive circuit 196A are separately connected to the differential line receiver 210(a) (Fig. 10) which is assigned to the car a in the elevator plant by means of the lines XCRDY(a) and XCRDY(a). It should be noted that the remaining outputs of each of the differential line drive circuits are similarly connected separately with circuits similar to those shown in FIG. 10 assigned to the individual cabins in the lift system.

The lower half of fig. 9B shows the remainder of the logic group circuits indicated by G/C in FIG. IA. The wire GSYNC connects the output 14 of the group processor GPU (Fig. 4) with the input 2 of the data selector 200. Two further inputs 11 and 14 of the data selector 200 are held at a binary signal level "1" as indicated by the wire L10. Inputs 5 and 10 of data selector 200 are connected to output 6 of dual-input NAND gate circuit 202B. The gate circuit 202B is connected with the first input 4 to the output 7 of the decoder 190 (Fig. 9B) and the second input 5

is connected via the wire GAU to the output 9 of the bistable latch circuit 60 (fig. 4). The bistable locking circuit 62 is connected via the lines GA14 and GA14 with the input 13 resp. 6 in the data selector 200. The wire GWX connects the last input 3 of the data selector 200 with the Q output 11 of the flip-flop circuit 78B (Fig. 5).

The outputs 4 and 7 in the data selector 200 are connected to the input 9 resp. 7 in a pair of differential line drive circuits 204A and 204B. The lines GTP, GTP and GDC, GDC connect the outputs of a pair of line drive circuits to the inputs of the differential line receiver 216(a) (Fig. 10).

The output 9 of the data selector 200 is connected to the input 5 of the inverter 170C whose output 6 is connected to the selection input 1 of the data selector 116 and 118 (fig. 7). Furthermore, the wire G8B connects the output 9 in the data selector 200 (fig. 9B) with the selection input 1 in the data selector 156 and 158 (fig. 8). The output 12 of the data selector 200 is connected via the line GCTE to the inputs 7 and 10 of the differential line drive circuits 122-130 (Fig. 7).

Fig. 10 shows a simplified connection core for the circuits in the group treatment device which is assigned to the cabin a and which is indicated by C/G(a) in fig. IA. It should be noted that this circuit is also part of the logical group circuits assigned to cabin a and that similar circuits are arranged for each of the cabins in the elevator system.

As previously mentioned, signal lines XCRDY(a) and XCRDY(a) connect outputs 14 and 13 of differential line driver circuit 196A (FIG. 9B) to inputs 9 and 11 of differential line receiver 210(a) (FIG. 10). The differential-line receiver 210 a is connected via the line CSUS(a) to the input 17 in the cabin processing device CPU(a) as shown in fig. 11 and with the input 9 in the inverter 212D a (fig. 10). The inverter 212D a is connected with the output 8 to the reset inputs 3 and 8 in the flip-flop circuits 214A(a) and 214B(a). Both flip-flop circuits 2l4A(a) and 2l4B(a) are with setting inputs 2 and 7 and inputs 4 and 9 as well as 16

and 12 connected to a binary signal level "1" represented by line L10. The timing input 1 of the flip-flop circuit 214A(a) is connected to the output 2 of the differential line receiver 216(a).

The Q output 15 of the flip-flop circuit 214A(a) is connected to the timing input 6 of the flip-flop circuit 214B(a) and the input 1 of the three-input NAND gate circuit 218A(a). The NAND gate circuit 218A(a) is connected with its second input 2 to the output 2 of the differential line receiver 216(a) and the third input 13 is connected to the Q output 10 of the flip-flop circuit 214B(a). The output 12 of the NAND gate circuit 218A(a) is connected to the input 3 of the inverter 212A(a) whose second output 2 is connected to the timing input 13 of a bistable latch circuit 222(a) and the timing inputs 4 and 13 of a pair of bistable latch circuits 224( a) and 226(a).

As shown at the bottom right of fig. 10, the output 11 of the flip-flop circuit 214B(a) is connected to the input 10 of an AND gate circuit 220C(a) with two inputs whose second input 9

is connected to output 2 of the differential line receiver 2l6(a). AND gate circuit 220C(a) is connected via wire GWD to inputs 5 and 11 of data selector 416(a) as shown in

fig. 13- The output 11 of the flip-flop circuit 2l4B(a) is connected to the input ,5 of the AND gate circuit 220B(a) whose other input 4 is connected to the output 14 of the differential line receiver 2l6(a). The output 6 of the AND gate circuit 220B(a) is connected to the control input 10 of the differential line drive circuit 228(a).

Output 14 in the differential line receiver 2l6(a)

is also connected to input 2 of the bistable latch circuit 222(a) whose output 16 is connected to input 1 of AND gate circuit 220A(a). The AND gate circuit 220A(a) is connected with its second input 2 to the output 6 of the AND gate circuit 220B(a) as described above and the output 3 is connected to the control inputs 10 and 7 in several differential line drive circuits

230(a), 232(a) and 234(a) at the top left of fig. 10.

Wires CGDØ(a), CGD1(a)....CGD7(a) connect inputs 11 and 5 of four differential line drive circuits 228(a), 230(a)j232(a) and 234(a) to the outputs of a pair of AND -gate circuits 412 (a) and 4l4(a) (fig. 13)- Outputs 13,l433and 2

in the differential line receivers are connected with lines DTØ(a)jDTØ(a)3 DT1, DT1,..DT7 and DT7 for the supply of data signals from the circuits assigned to cabin a to the group processor as will be described in more detail below.

The lines DTØ(a)3DTØ(a)3and DT1 and DT1 are connected to the inputs 11, 9, 5 resp. 7 in a differential line receiver 236(a). The other lines DT2, DT2... DT7 are connected in a similar manner to the inputs of three further differential-line receivers 238(a), 240(a) and 242(a) (Fig. 10). Wires GCBØ(a), GCBl(a)...GCB7(a) connect outputs 14 and 2 of differential line receivers 236(a), 238(a)324o(a), 242(a)

with inputs 736, 3 and 2 in a pair of bistable latch circuits 224(a) and 226(a).

Wires GCAØ(a), GCAl(a), ,GCA2(a)3 GCA3(a) connect the Q outputs 9,10,15 and 16 in the bistable latch circuit 224(a) with the inputs 2,5,11 resp. 14 in two input data selectors 408 (Fig. 13). Wires GCA4(a), GCA5(a), GCA6(a) and GCA7(a) similarly connect outputs 9,10,15 and 16

in the bistable latch circuit 226(a) with inputs 2,5,11 and 14

in a second data selector 210(a) (fig. 13)-

Wires GCBØ(a), GCBl(a)....GCB7(a) connect the outputs of the differential line receivers 236(a), 238(a), 240(a) and 242(a) to the inputs 2,5,11 and 14 in a pair of data selectors 400(a) and 402(a) with two inputs (Fig. 13)-

The line DTS connects the Q output 10 in the flip-flop circuit 2l4B(a) (Fig. 10 with apparatus to be described in more detail below in connection with Fig. 13-

Fig. 11, 12 and 13 together show a simplified connection diagram for the part of the circuits in the cabin processing device and the cabin program storage device which are assigned to the cabin a, namely CPU(a), CR(a), SW(a), CRAM(a) and CROM(a) in fig. IB. Additional circuits in the cabin treatment device and the cabin control equipment which are assigned to cabin a and which in fig. IB is denoted by CESC(a) and CCE(a) will be explained in more detail below with reference to fig. 14,15,16 and 17- It is clear that similar circuits will be arranged for all the other cabins in the facility.

A comparison of fig. 4 and 5 and fig. 11 and 12 show that the designations of the circuit elements and their mutual connections are identical. A further comparison shows that the designations on fig. 4 and 5 are provided with a G as the first letter, while in fig. 11 and 12 a C is used.

The part of the program storage device which is assigned to the cabin processor CPU(a) (fig. 11) and in fig. IB is designated cabin program storage device CROM(a) is shown in fig. 13 as a pair of storage devices 392(a) and 394(a) which are connected to the apparatus of fig. 11 in the same way as the associated group program storage device in fig. 6 is connected to the associated apparatus in fig. 5. It should be noted that the designation of the read-only storage device varies with the composition of the stored program.

The upper part of fig. 13 shows the cabin data storage device and the cabin data connection device. Wires

CDØ(a), CDl(a), CD2(a) and CD3(a) connect the first set of inputs 3,6,10 and 13 of data selector 400(a) to outputs 3, 6,10 and 13 of bidirectional drive circuit 354( a) (Fig. 11) and wires CD4(a), CD5(a), CD6(a) and CD7(a) connect the first set of inputs 3,6,10 and 13 of the second data selector 402(a) (Fig . 13) with outputs 3, 6, 10 and 13 of the bidirectional drive circuit 356(a) (Fig.

11). In addition to this, the wires GCBØ(a-), GCBl(a).... GCB7(a) connect the second set of inputs 2,5,11 and 14 in the two data selectors 400(a) and 402(a) with the outputs 1 and 15 in four differential line receivers 236(a), 238(a), 240(a) and 242(a)

(Fig. 10). The data selectors 400(a) and 402(a) are connected with the outputs 4,7,9 and 12 to the data inputs 9,11,13 and 15 in a

pair of 1024 bit (256 x 4) data storage devices 4o4(a) and 406(a).

Wires CAØ(a), CA1(a)...CA7(a) are connected with

the first set of inputs 3,6,10 and 13 in a second set of data selectors 4o8(a) and 4l0(a). The connections using the wires GCAØ(a), GCAl(a)...GCA7(a) with the data selectors 408(a) and 410(a)

is described earlier with reference to fig. 10. These data storage devices are connected with their outputs 4,7,9 and 12 to the address inputs 4,3,2,1,21, 5,6 and 7 in the data storage devices 4o4(a) and 4o6(a).

The two sets of data outputs 10,12,14 and 16 in the data storage devices (404(a) and 406(a) are connected via lines CDOØ(a), CD01(a)...CD07(a) to inputs 2,5, 11 and 14 in one

pair of data selectors 366(a) and 368(a) (fig. 11) for transmitting first and second cabin control signals or group control signals from the cabin data storage device to the cabin processing device CPU(a), (fig. 11). Furthermore, the outputs are 10, 12, 14 and 16

in data storage devices 404(a) and 406(a) connected to inputs 1,4,9 and 12 of a pair of AND gate circuits 412(a) and 414(a) with two inputs. The outputs 3,6,8 and 11 from the AND gate circuits 4l2(a) and 4l4(a) are via lines CGDØ(a), CGDl(a).... GCD7(a) connected to apparatus that is described in connection with fig. 10.

The control inputs 15 in the data selector pair 4o8(a) and 4l0(a)

(fig. 13) shall below be referred to as address switching devices and the inputs 19 in the data storage device pair 4o4(a) and 4o6(a) are connected to the output 4 in the data selector multiplex

is 4l6(a). The input-readout terminal 20 in the storage devices 404(a) and 406(a) and the control inputs 15 in the data selectors 400(a) and 402(a) which are designated below cabin data input switching devices are connected to the output 4 of the inverter 4l8B 3.whose input 3 is connected to the output 7 of the data selector 416(a). The output 18 from the data storage devices 4o4(a) and 4o6(a) is connected to the third output 9 of the data selector 416(a). The wire L10 connects the terminal 17 of the data storage devices HOk(a) and 4o6(a) with a binary signal level "1".

The wire DTS(a) connects the Q output 10 of the flip-flop circuit 214B(a) (Fig. 10) with the input 1 of the data selectors 400(a) and 402(a), the two address selectors 4o8(a) and 4l0(a ) and the control signal selector 4l6(a). The line DTS(a) is also connected to input 1 of the inverter 418A(a) whose output 2 is connected to inputs 2,5,10 and 13 of the AND gate circuits 412(a) and IJ1Ma).

The control signal selector 4l6(a) is with the control input

15 and the input 2 connected with a binary signal level "0" as indicated with the line HL1. The line GWD(a) connects the inputs 5 and 11 of the control signal selector 4l6(a) with the output 8

in the AND gate circuit 220C(a) (Fig. 10). Inputs 3 and 10 in the control signal selector 4l6(a) are connected via the wire CSS(a) to output 10 in the data selector 37Ma) (fig. 12). The wire CWX(a) connects the Q output 11 of the flip-flop circuit 378B(a) (Fig. 12) to the input 6 of the control signal selector H16(a).

Fig. 14 and 16 show the cabin steering signal selection circuits which are assigned to cabin a and in fig. IB shown as CES(a). The cabin control signal selection equipment connects the cabin operating device CCE(a) with the cabin processor CPU(a) which will be described in more detail below and which selectively transmits binary signals inductively from the cabin operating device to the cabin processor. In addition, the cabin control signal selector circuits work in accordance with the relevant cabin handler to transfer a first cabin control signal to the relevant cabin operating device to control the cabin a independently and a second cabin control signal to the relevant operating device to control the cabin a as part of a superdetermining group.

The line CDØ(a) connects the output 5 in three data selection multiplexes 430(a), 432(a) (fig. 14) and 434(a)

(fig. 16) with terminal 3 in the two-way drive circuit 354(11). The cabin call selectors 430(a) and 432(a) and the cabin condition signal selector 434(a) operate in accordance with a binary signal nine "0" to the respective control inputs 7 and a three-bit binary signal supplied via the lines CAØ(a), CAl(a ) and CA2(a) from outputs 1,14 and 11 of the bistable latch circuit 358(a)

(fig. 11) to their data selective inputs 11,10 and 9 for the selector to deliver one of eight signals to inputs 4,3,2,1,15,14,13 and 12 via the line CDØ(a). The selected apparatus which delivers the binary signal level "0" to the control input 7 in the selected unit shall be described in more detail below. The data input 13 in 3-8 bit addressable latch circuits 438(a),. 440(a) (fig. 14) and 444 (a) (fig. 16) are also connected to the wire CDØ(a) and the address inputs 1,2 and 3 are connected to the wires CAØ(a), CAl(a) and CA2 (a). In response to the three-bit binary code applied to the address inputs and a binary signal level "0" applied to the control input 14 of a selected one of the three addressable latch circuits 438(a), 440(a) and 444(a), this will provide a binary signal "0" from one of the outputs 4,5,6,7,9,10,11 and 12 which corresponds to the signal on the line CDØ(a). The apparatus which delivers the binary signal level "0" to the control input 14 in a selected locking circuit will be described in more detail below.

Control input 7 of the pair of cabin call selector circuits 430(a) and 432(a) is connected to outputs 6 and 7 of the 2-4 line decoder 446(a) (Fig. 14). Two further outputs 11 and 12 from the decoder 446(a) are connected to the control inputs 14 of the call reset selectors 440(a) and 438(a). The wire CEXØ(a) connects the control inputs 2 and 14 of the selector 446(a) with the output 15 of the 3-8 line decoder 372(a) which is shown in fig. 12. An input or read signal is supplied via line CRX(a) or CV/X(a) from output 3 of the AND gate circuit 380A(a) (Fig. 12) or the Q output of the flip-flop circuit 378B (a) (Fig. 12) to input 1 or 3 of selector 446(a). Two further signal lines CA3(a) and HL1 connect the inputs 13 and 15 of the selector '446(a) with the output 8 of the bistable latch circuit 358(a) (Fig. 11) and with a binary signal level "0" represented by the line HL1 .

The control input 7 of the cabin condition signal selector 434(a) (Fig. 16) is connected to the output 8 of a three-input NAND gate circuit 442C(a). Leads CA3(a), and CRX(a) connect inputs 9 and 11 of NAND gate circuit 442C(a) to output 9 of bistable latch circuit 358(a) (FIG. 11) and to terminal 3 of AND gate circuit 380A( a) (fig. 12). Wire CEX3(a) connects output 12 of the 3-8 line decoder 372(a)

(Fig. 12) with the input 1 of the inverter 448A(a) whose output 2 is connected to the third input 10 of the NAND gate circuit 442C(.a).

Control input 14 in cabin signal selector 444(a)

(Fig. 16) is connected to output 6 of the three-input NAND gate circuit 442B(a). Wires CA3(a) and CWX(a) connect inputs 3 and 5 of gate circuit 442B(a) to output 9 of bistable latch circuit 358 (Fig. 11) and to Q output 11

in the flip-flop circuit 378B(a) (Fig. 12). Wire CEX4(a) connects output 11 of 3-8 line decoder 372(a) (Fig. 12) to input 3 of inverter 448B(a) whose output 4 is connected to the third input 4 of gate circuit 442B(a).

Fig. 15 shows a simplified connection core for the cold cathode gas discharge control buttons for the main floor and floors 2, 6, 7, H, 12 and T in the building where the elevator system is installed. It is clear that additional cabin call registration circuits for the rest of the floors are connected in the same way.

The anode in each of the tubes lC(a), 2C(a)...TC(a) has a voltage of 135 volts via line B+ from a current source PSI (fig. 3) described above, and the cathodes are connected via a cathode resistor RCL1, RCL2...RCLT which is connected to the current source's second connection line BO. The lines Cl(a), C2(a)...CT(a) connect the cathode in the associated tube with an optical coupling converter 18A which will be described in more detail below. These converters are connected by wires BO and AC1

in the power source PSI.

Cab call registration signals for the circuits on

fig. 15 appears on lines lCS(a), 2CS(a), 6CS(a), 7CS(a), HCS(a), 12CS(a) and TCS(a) and is fed to inputs 12,13,2 and 3 in the call selector 430(a) (Fig. 14 ) and 14,15 and 4 in the call selector 432(a) (Fig. 14).

Call reset signal for each call registration circuit shown is supplied from outputs 12,11,6 and 5 of call reset selector 438(a) (Fig. 14) and outputs 10,9 and 4 of call reset selector 440(a).

via lines 1CR(a), 2CR(a), 6CR(a), 7CR(a), HCR(a), 12CR(a) and TCR(a) to the reset input R of converter 18A.

Fig. 17 shows a simplified connection core for the control equipment which is assigned to cabin a. The elevator cabin 10(a) and the counterweight ll(a) are suspended in hoisting wire 12(a) from

a wire washer 13(a). Cabin 10(a) serves 16 floors Ll-Lt like the rest of the cabins in the group (not shown).

The wire pulley 13(a) is mounted on the axis of the rotor MA^a) of a DC elevator motor which is also equipped with an elevator brake BR(a). The motor armature MA(a) is connected in parallel with the generator armature GA(a) and in series with its field winding GSEF(a) for the DC generator in a motor-generator unit. The motor field winding MF(a) and the generator field winding GF(a) both receive current from a self-excited generator with

an armature EA(a) which is also connected to a common shaft for the motor-generator unit (not shown).

Two rows of normally closed door zone contacts DlZ(a)

and D2Z(a) connects the wire V2(a) to one end of the energizing coil in the door opening switch D0(a). The wire D0(a) connects the other end of the energizing coil of the door open switch D0(a) to terminal 02 of a relay drive circuit l8C(a)

(fig. 16) whose input 13 is connected to output 4 of the relay selector 444(a) (fig. 16).

The energizing coil in the starter switch ST(a) is also connected to wire V2(a) and wire G0(a) which is similarly connected to terminal 02 of a second relay drive circuit l8C(a) (Fig. 16) whose input terminal 13 is connected to output 7 in the relay selector 444 (a). The relay selector 444,(a) has two additional terminals 5 and 6 connected to the input 13 of a further pair of relay drive circuits l8C(a) which are connected via wires AU and AD to one end of the setting coil and one end of the reset coil in the directional hold switch DG(a )

(Fig. 17).

Series-connected door contacts GS(a) and door contacts DS(a) are brought into the closed state when the cabin or floor door is closed and supply the voltage on line V2(a)

via the wire DFC to input 12 of the converter l8B(a). The output 01 of the converter is connected to the input 14 of the signal selector 434(a). Another door switch 0L(a) which is operated when the elevator door is fully open, connects wire V2(a) to wire DFO(a). This latter line is connected to the input 12 of the converter 18B(a) whose output 01 is connected to the input 13 of the signal selector 434(a).

The cabin operating equipment assigned to cabin a comprises a pair of advanced floor position brushes FPU(a) and FPD(a) and a real floor position brush FPB(a) is fitted

on the synchronous panel of a floor selector for contact with the floor position contacts FPCl(a), FPC2(a)...FPCT(a) which are connected to the matrix MT(a) to supply binary signals representing the advanced cabin position and the actual cabin position . The floor position brush in question is connected via normally closed operating switch contact H2(a) to the wire V2(a) when the cabin a is on a floor so that the matrix supplies a binary coded signal representing the real cabin position to the cabin position signal lines CPl(a), CP2( a), CP4(a), CP(a) and CPl6(a). These wires are connected to the input terminal 12 of five converters 18B(a) whose outputs 01 are connected to the inputs 15,1,2,3 and 4 of the signal selectors 434(a).

Normally broken operating break contacts Hl(a) connect wire V"(a) to wire V3(a) which is also connected to wire RUN(a) which connects this to input 12 of converter l8B(a) whose output is connected to input 12 of the cabin mode selector 4 34 (a).

The floor position brushes UlS(a), U2S(a), DlS(a) and D2S(a) in the above selectors are set to cooperate with the series connected floor position contacts lSC(a) and 2SC(a) when the cabin is in a predetermined distance from these floors.

The main deck j eanrop^-• and cabin call recording circuits described above are connected to the converters 18A as shown in fig. l8A. Each of these circuits responds to the detection of the corresponding call to supply a binary signal "0" at output S. To reset a call, a binary signal "0" is applied to input R which causes the signal on wire AC1 to be applied to terminal II.

The input circuits 18B(a) (Fig. 16) are shown in Fig. l8B. In response to an input signal on terminal 12, each of these converters will supply a binary signal "0" on its output terminal 01.

The four relay drive circuits l8C(a) are shown in fig. l8C. In response to a binary signal "0" on the input terminal 13 in each of these relay drive circuits, sufficient ground potential is supplied to the inputs 02 so that an associated relay is energized.

In order to understand how the control system works so that each cabin in the facility works as part of an overriding group, it will be described below how the group management device GPM receives the first cabin control signals from the cabin management device CPM and delivers group control signals to the cabin management device which delivers other cabin control signals in response to this and delivers these signals to the cabin operating equipment assigned to each cabin in the facility so that they work as parts of an overriding group. It is assumed that the cabin processing device CPM in the facility comprises a separate cabin handler and associated logical cabin circuits both for each individual cabin in the facility and that each cabin handler in turn performs a first set of operations by executing a cabin program with instructions for delivering the first cabin control signals in response to cabin call signals and cabin position signals that are delivered to the cabin operating equipment for the cabin in question so that it works as prescribed. It is clear that the cabin processor and the associated logical cabin circuits for each cabin work in the same way so that the description of transmission of the first cabin control signals and group control signals between the cabin processor CPU(a) and the associated logical cabin circuits for a single cabin e.g. a and the group processing device can equally well be used for signal transmission between the cabin handlers and their associated logical cabin circuits individually to further cabins in the facility.

It is also assumed that the group processing device comprises a group processor GPU and associated logical group circuits and that the group processor in turn performs a second set of operations according to a group program to receive main floor call signals from the group control equipment GCE (Fig. 2) and first cabin control signals and deliver group control signals to selected cabin handlers and their associated cabin logic circuits

U.S. Patent No. 3,614,995 discloses apparatus for controlling a number of elevator cars as a dominant group. It also appears that each individual cabin can work according to registrations of cabin calls and signals that indicate the position of the cabin and cause the associated cabin to work in a certain way. E.g. when the cabin stops at a distance from a floor on which the cabin call is registered, the cabin must begin a stop operation for the relevant floor.

In this operation, the step-by-step sequence of instructions will comprise a cabin program which contains a subroutine which causes the transfer of information indicating the registration of a cabin call for a particular floor to the relevant cabin's cabin processor CPU(a) for e.g. the cabin a.

In the same way, information indicating the position of cabin a when stopped at a distance from the floor for a registered call is also transmitted to the cabin handler CPU(a).

The generation of information for registering a cabin call in the cabin a e.g. for the seventh floor, a signal is generated using the optical coupler and converter 18A

which is assigned to that person.cabin a and the seventh floor which provides a binary signal "0". This signal is applied to the cabin call selector 430(a) (Fig. 14).

The subroutine by which the cabin handler CPU(a) receives cabin call information from the seventh floor from the cabin call selector 430(a) is started by the program counter in the cabin handler CPU(a). A count value is added to the program counter at the end of each operating interval Tl for the cabin handler so that it receives step by step the next instruction from its cabin program storage device CROM(a)

(Fig. 13).

Under the assumed conditions, the instruction received from the cabin program storage device CROM(a) will cause the cabin processor CPU(a) to receive the signal supplied via the line 7CS(a) to the cabin call selector fl30(a). In order to

move information from the line 7CS(a) to the processor it is known that the cabin processor CPU(a) must contain, in addition to an 8-bit operation code or instruction received from its program storage device CROM(a), must contain a l6-bit address code. This code identifies the terminal 3 of the call selector 430(a) to which the wire 7CS(a) is connected and ensures that the signal on this wire is transmitted to the cabin handler CPU(a).

The address code in the cabin processor CPU(a) causes the registers 358(a), 362(a), 360(a-) and 364(a) to deliver 16 corresponding signals via the lines CAØ(a) to CA15(a) during the time intervals Tl and T3 for the practitioner. The signals on the wires CAØ(a), CAl(a) and CA2(a) are fed to terminals 11,10

and 9' in the call selector 430(a) for selecting the signal supplied to it via line 7CS(a) and for delivering a corresponding signal at output 5. The signals on lines CA10(a), CA13(a), CAlMa) and CA15 (a) are such as to cause decoder 374(a) to supply a binary signal "0" at output 9-This is applied to decoder 372(a) in response to the address contained in the signal on lines CA4(a), CA5( a) and CA6(a) supplies a binary signal "0" on the line CEXØ(a). The address signal applied via the line CA3(a) and the binary signal "0" on the line CEXØ(a) are applied to the multiplexer 446(a) and upon receiving a binary signal "1" via the line CRX(a) and a binary signal "0 " via the wire CWX(a), the multiplexer will supply a binary signal "0" on the input 7 of the call selector 430(a). A ..binary signal "1" is supplied via line CRX(a) during the time interval T3 because during the preceding time interval T2 a binary signal "0" was supplied via the line CT2(a) to flip-flop circuit 376(a) for delivery of a binary signal "1" to the AND gate circuit 380(c) from the output

5. During the first half of the time interval T3

a binary signal "1" is delivered via the line CSYNC from the processor CPU(a). This caused a binary signal "1" on wire CT3A(a) which in combination with the binary signal "1"

on line CA14(a) as a complement to the coded operating signal on line CAl4(a) causes the AND gate circuit 380A(a) to supply a binary "1" signal on line CRX(a). A binary signal "1" is delivered on the line CWX(a) because the processor performs a reading and at the beginning of the time interval T3 a binary signal "1" is delivered on the line C01(a)

which resets the flip-flop circuit 378B(a) and causes that

a binary signal "0" is supplied to the wire CWX(a).

When receiving the binary signal "0" at the input

7, the call selector 430(a) supplies a binary signal "0" on the line CDØ(a) to terminal 3 of the bidirectional drive circuit 35Ma). When the handler is in the time interval T3 and a reading takes place, the binary signal "0" and the binary signal "1" supplied via the lines CCS(a) and CDIEN(a), signals generated on the lines GCS(a ) and the CDI(a)

(fig. 4) when the group processor GPU(a) receives data from the cabin data storage device CRAM(a) for cabin a. These signals on the lines CCS(a) and CDIEN(a) produce the complement of the signal on the line CDØ(a) which indicates registration of cabin calls from the seventh floor which are fed to the cabin handler CPU(a) for temporary storage.

From the foregoing it is clear how other signals

which indicates other information about the elevator car is transferred from the car control equipment to the car processor CPU(a). Information such as indicates that the elevator car a is at a stopping distance from the seventh floor, is transferred

via the brush FPU(a) or FPD(a) (fig. 17), depending on the direction of movement of the cabin and contact FP7(a) in relation to the matrix MT(a). Binary signals indicating this information are transmitted via the output line CPl(a) to CPl6(a)-

from the matrix MT(a). These binary signals are supplied to the associated selectors 18B(a). The output signals from the selectors l8B(a) are transmitted via the line CDØ(a) to the cabin processing device CPU(a) in the same way as signals indicating registration

of cabin calls on the seventh floor.

The cabin processing device CPU(a) (Fig. 11) uses the signals indicating that the cabin is within stopping distance from the seventh floor and that a cabin call on the seventh floor has been registered to control the cabin to stop on the seventh floor. It does this by jointly producing a signal that a stop is to be initiated. A signal will then be supplied via wire CDØ(a) to terminal 13 of decoder 444 to supply an output signal at output 7 which causes the associated relay driver circuit 18C(a) to supply a binary signal "1" on wire GO(a) . This signal supplied to the coil ST(a) (fig. 17) will trigger the associated stop switch and cause the cabin to stop in the desired manner in accordance with the subsequent triggering of the switches FE(a)3E2A(a), EIA(a), H(a ) and U(a) or D(a) depending on the cabin's direction of movement.

It is desirable to store the signal on the wire

CDØ(a) which causes the binary signal "1" to be produced on line GO(a) in the cabin data storage device CRAM(a)

(fig. 13) with the intention of having it ready for later use. This happens because the processor in its stepwise operation receives an 8-bit movement instruction for storing the signal in this way. This instruction is retained in the cabin processor CPU(a) and indicates that a signal corresponding to that on the line GO(a) is to be moved to the cabin data storage device CRAM(a). In addition to this, a 16-bit address code is also contained in the cabin processor CPU(a).

The first eight of these latter sixteen signals are supplied via lines CAØ(a) - CA7(a) to the data selector 408(a) and 410(a) to prepare the addressing of the cabin data storage device CRAM(a). These signals, after application in the cabin data storage device, will cause the storage of a signal corresponding to that on the line GO(a) in the position of its corresponding address indicated by signals supplied via the lines CAØ(a) to CA7(a).

The last eight of the sixteen signals are supplied to leads CA8(a)-CA15(a). These signals are such that they bring the apparatus in fig. 12 to supply a binary signal "0" on the line C.RSE(a) and a binary signal "1" on the line CWX(a). The first of these signals is due to part of the code which is supplied via the lines CA10(a)3 CAll(a), CA13(a)3CAl4(a) and CA15(a) which has now been changed from the previously described in that the signal on the wire CAlMa) has the binary value "1". The latter signal on line CWX(a) is binary "1" during the third time interval T3 of the cabin treatment device because during this interval the signal on line CT3(a) is binary "0" and during a storage operation the signal on line CPCW(a) is also also binary "0" because the code signal CAl4(a) and CA15(a) are both binary "1". The binary signals "0" on the lines CT3(a) and CPCW(a) cause the flip-flop circuit 378B(a) to supply a binary signal "1" on the line CWX(a).

The signals on the lines CSS(a) and CWX(a) are applied to a selector 4l6(a) (Fig. 13) and together with the binary signal "1" appearing on the line DTS(a) causes the selector to supply an output signal to prepare the cabin processing unit CPU(a) for entering information, i.e. storing signals indicating information in the cabin data storage device CRAM(a). A binary signal "1" is applied to the wire DTS(a) as a result of the binary signal "0" on the wire GA13 as a code for the group processor which is always binary "0" with the exception of when the cabin processor GPU (Fig. 4 ) must communicate with the cabin handling equipment as described in more detail below. This causes line driver circuit 196A (Fig. 9B) to supply a binary "0" signal on line XCRDY(a) to receiver 210(a) (Fig. 10). This produces a binary signal "0" on terminals 3 and 8 of flip-flop circuits 214A and 214B and resets them and causes a binary signal "1" on line DTS(a).

The binary signal "1" on the wire DTS(a) together with the output signals from the switching device 416(a) sets the selectors 408(a) and 410(a) for transferring the address signals on the wires CAØ(a) - CA7(a) to the cabin data storage device CRAM(a) for transmitting the signal corresponding to that on the line G0(a) to the cabin data storage device via the data selectors 400(a) and 402(a). The signal corresponding to that on the wire G0( a )o verf is heard via the wire C.DØ( a) via the selector 400(a) in the next sequence of operations. This occurs because the cabin processing device CPU(a) is affected by the 8-bit push signal to push this signal out through the line CDØ(a) immediately after transmitting the address signals. As a result, the signal corresponding to that on the line GO(a) will be pushed along the line CDØ(a) to the data selector 400(a) and through this to a position in the cabin data storage device CRAM(a) as a result of the 8-bit address

which was previously transmitted by the cabin processing unit CPU(a).

Extraction of stored information from the data storage device CRAM(a) by means of the cabin processing device CPU(a) corresponds to the operation by which the cabin processing device stores information in the data storage device. The difference between storage and withdrawal is that during the latter operation the 16-bit address signal must be such that the apparatus in fig. 12 changes the state of the signal on line CWX(a) to binary "0" from binary "1" provided during storage. This binary signal "0" is supplied via the line CWX(a) in the same way as previously described

for transmitting the signal corresponding to that on the line G0(a) to the data processing unit CPU(a). The change of state takes place after the end of the time interval T3 when the signal on the line CT3(a) and the signal on the line C01(a) become binary signals "0" after which a binary signal "0" is applied to terminal 8 of the flip-flop circuit 378B(a). The signal on the line CWX(a) is not changed to binary "1" during the time interval T3 for a reading such as during storage because during the reading the signal on the line CPCW(a) is not binary "0" as during the storage. Consequently, the flip-flop circuit 378B(a) remains in the reset state during the reading and continues to supply a binary signal "0" on the line CWX(a).

This enables the reading of information from the cabin data storage device CRAM(a) (fig. 13), i.e. the cabin data storage device delivers output signals on the lines CDOØ(a)-CD007(a) during the reading as opposed to its reception

of signals from the cabin processing unit CPU(a) which are supplied via the lines CDØ(a) - CD7(a) during storage.

Also the operating signals are such that they change the state of the signal on the wire CSS(a) to binary "0" on

a way that will appear clearly from the following explanation-

clarification of how a binary signal "0" is applied to the line GSS when the group processor GPU(a) receives data. This binary signal "0" on line CSS(a) enables signals on lines CDOØ(a) to CD07(a) to be transmitted by data selectors 366(a) and 368(a).

The cabin processing unit CPU(a) can be controlled by instructions stored in the cabin program storage device CROM(a) and received from it via the lines CIOØ(a)-CI07(a), so that after the termination of a stop resulting from a cabin call on the seventh floor, the handler can CPU(a) transmit signals for canceling the call. This would mean a storage operation similar to the reading operation for the cabin call on the seventh floor for the transmission to it of a signal indicating this. The difference between the storing operation and the reading operation is that the address code causes the generation of a binary signal "1" on the line CWX(a) during the time interval T3 as opposed to producing a binary signal "1" on the line CRX(a). Also during the store operation, a binary signal "0" is transmitted via the line CDØ(a) to terminal 13 of the cabin call reset selector 438(a) in contrast to the read operation, when a binary signal "0" is transmitted via the line CDØ(a) from terminal 5 of the cabin call selector 430(a) as previously explained.

As a result of the binary signal "0" being supplied to the terminal 13 of the selector 438(a) and the code corresponding to the seventh floor on the lines CAØ(a), CAl(a).and CA2(a) and the binary signal "1" on line CWX(a), selector 438(a) produces a signal on line 7CR(a) which is supplied via converter 18A to clear the cabin call from the seventh floor by means of tube 70(a) and thus cancel the call.

It shall be assumed that a cabin call for the seventh floor is not registered in the cabin a but that the cabin handler CPU(a) has performed operations in accordance with a cabin position subroutine whereby the position of the cabin a is located at a stopping distance below the seventh floor indicated by the brush FPU(a ) which touches the contact FPC7(a) and this is stored in a specific position in the cabin data storage device CRAM(a), and that the cabin processor CPU(a) has established an upward movement for the cabin a. Consequently, a binary signal "0" is supplied via the wire AU(a) to the setting coil SDG(a) so that the direction relay is energized to maintain the direction of the created direction of motion. It is also assumed that the group handler GPU has performed operations in accordance with a main floor call subroutine and has received a signal indicating the registration of a seventh floor call signal. Furthermore, it is assumed that during the step-by-step operation, the group processor has received cabin position information for cabin a which is stored in the relevant cabin data storage device CRAM(a) and has generated a signal that is to be transmitted to the cabin data storage device for cabin a in order for it to stop for the registered call signal on the seventh floor.

In order to understand how the group processing device GPU works to receive signals directly from and store signals directly in the cabin data storage device CRAM(a), it will be described below how cabin position information for cabin a is received by the group processing device and how a signal to begin a stop of cabin a on the seventh floor is transmitted from the group processing device GPU to the cabin data storage device CRAM(a).

The subroutine by which the group handler receives cabin position information from the cabin data storage device is started by the program counter in the group handler. It is well known that a count value is added to the program counter at the end of each time interval Tl for the group processor so that it in turn receives the next instruction from its group program storage device GROM. After receiving this 8-bit instruction, it is used in the group handler and the 16-bit address code comprising the position in the cabin data storage device CRAM(a) is stored. The address code signals in the group processor GPU are transmitted via the drive circuits 54 and 56

to the lines GDØ - GD7 for storage in the registers 58,62,60

and 64 in the . two time intervals Tl and T2.

During the last quarter of the time interval T1, a binary signal "0" on line GT1 causes the NAND gate circuit 178a to supply a binary signal "1" on its output.

During the second half of the time interval T2, a binary signal "1" is supplied on the line G01 and a binary signal "0" on the line GSYNC. As a result, the NAND gate circuit 170B will supply a binary signal "1" to the terminal 1 of the flip-flop circuit 172A. At the same time, a binary signal "0" is supplied via line GD5 to terminal 16 and its complement is supplied to terminal 4. At the beginning of the last quarter of the time interval T2, a binary signal "0" is supplied to line GT2 so that the output of gate circuit 178A supplies a binary signal "0". As a result, a binary signal "0" will also be applied to terminal 1 of the flip-flop circuit 172A which supplies a binary signal "0" on the line GSUS.

The signal on wire GSUS is applied to terminal 17 of the group processor GPU to interrupt its normal order of operation at the end of time interval 12. This interruption continues for four wait states before the processor enters time interval T3. In this way, regardless of asynchrony between the group processor and the cabin handler, wait a sufficient period of time to ensure that before the beginning of the time interval T3, the operational state in the cabin handler is interrupted at the end of the time interval T2 as will be explained in more detail below.

In the meantime and as a result of the supply of address code signals on the lines GDØ - GD7, output signals are supplied on the lines GAØ to GA15 and GA8 to GA15, the signals on the latter lines being the complement of signals on the lines GA8 to GA15. These signals are produced by registers 58,60,62 and 64. The binary signal "1" on line GA13 causes the two-four line decoder 74 and AND gate circuit 80D to supply a binary signal "1" on lines GRSE and GSS. These signals are supplied to terminals 18 and 19 of the group data storage device GRAM and prevent the group storage device from responding to address signals on the lines GAØ-GA7-

Since the group processor GPU is to receive signals from the cabin data storage device CRAM(a) for cabin a, the three signals on wires GA8, GA9 and GA10 are coded to identify cabin a as the selected cabin for the delivery of signals. These three signals together with the binary signals "1" on lines GAU and GA13 and the binary signal "0" on line GA13 cause the 3_8 line decoder 190, the data selectors 192 and 194 and the line driver circuit I96A to supply a binary signal 1 on line XCRDY(a ). This signal is applied to the differential line receiver 210 and causes it to deliver a binary signal "1" on the line CSUS(a) which is applied to terminal 17 of the cabin processor CPU(a) for cabin a and causes its operation to be interrupted at the end of the next time interval T2 .

Before the generation of the binary signal "0" on the line GSUS (Fig. 9A) which causes an interrupt in the group processor GPU (Fig. 4), the signal on the line GSUS was of the opposite state. At that time this signal and a similar signal on wire GA13 (fig- 9A) (the signal on wire GA13 is always binary "1" except when the group handler communicates with the cabin equipment) caused by the supply of the binary signal "0" on terminals 3 and 8 in the flip-flop circuit l80A and l80B. This causes a binary signal "0" on the line GCDT. While this signal continues and after the signal on line GA13 has become binary "0", the address signals on lines GA1 - GA7 (Fig. 4) are transferred to data selectors 100 and 102 via lines GCD1 - GCD7 to the four differential drive circuits 126, 128, 130 and 132 as shown in fig. 7.

At this time, a binary signal "0" is applied via line G8B (Figs. 7 and 9B) because the binary signal "0" on lines GA13 dg GCDT (Fig. 9B) causes the binary signal "1" on line L10 to the input 11 in the data selector 200, the line G8B and the complement of the line G8B are supplied. In the same way, the signal supplied on the line L10 to the input 14 is supplied to the line GCTE.

As a result, the binary signals supplied via lines GA13 and G8B are supplied, the signals are transferred from terminal 4 in the selector 100 (fig. 7) which is supplied to terminal 3

in selector 116 and terminals 2,5,11 and 14 in both selectors 116 and 118, via wires GCDØ(a) - GCDØ(h). These signals are supplied to the inputs of the differential line drive circuits 122, 123, 124 and 125 as shown in fig. 7- As a result of these signals and the binary signal "1" supplied via the line GCTE, these drive circuits will deliver corresponding and complementary signals on the lines DTØ ( a ) and DTjJ(a) to DTØ(h) and DTØ (h ) .

As a result of the signals supplied via lines GCD1-GCD7 and the binary signal "1" on line GCTE, differential line driver circuits 126, 128, 130 and 132 supply signals on lines DT1 and DT1 - DT7 and DT7 to the second set of differential line receivers 236, 238, 240 and 242 as shown in FIG.

fig. 10. The signal on wires DT1, DT1, DT2....DT7 is common to the differential line receivers assigned to cabin a as shown in fig. 10 as well as the line receivers which are assigned to further cabins (not shown), but correspond to those in fig. 10 and is assigned to each additional cabin. The lines DTØ(a) and DTøTa) - DTØ(h) and DTØ(h) for each of these cabins are connected only to the line receivers assigned to the relevant cabin.

The differential line receivers 236(a), 238(a), 240(a)

and 242(a) transmits an 8-bit binary signal corresponding to the address signal via lines GCBØ(a) - GCB7(a) to the inputs of a pair of bistable latch circuits 224(a) and 226(a) shown in FIG. 10. The corresponding equipment for other cabins works in the same way and should therefore not be described further.

During the time interval in which the 8-bit address signals are transmitted from the bistable latch circuits 58 and 62

to the bistable latch circuits 224(a) and 226(a), the group processor GPU continues and supplies signals via line GSYNC to terminal 2 of the selector 200 (FIG. 9B). As a result of each of these pulses, a corresponding pulse is delivered on line GTP from line drive circuit 204A. The second of these pulses causes the line receiver 2l6(a) (Fig. 10) and the flip-flop circuits 2l4A(a) and 2l4B(a) to supply binary signals "1" to the corresponding inputs of the NAND gate circuit 2l8A(a) . As a result, inverter 212A(a) supplies a binary signal "1" to latches 224(a) and 226(a) to store the 8-bit address signal applied to their input terminals. This causes these latch circuits to supply 8-bit address signals representing the address of the position in the cabin data storage device CRAM(a) via the lines GCAØ(a)-GCA7(a) to the data selector pair 4o8(a) and 4l0(a) as shown in fig. 13.

Meanwhile, the binary signal "0" on the line GAU (Fig. 9B) has caused the NAND gate circuit 202B, the selector 200 and the line driver circuit 204B to produce a binary signal "1"

on the wire GDC. This is supplied via the receiver 2l6(a)

(Fig. 10) to terminal 2 of latch circuit 222(a) in which it is stored as a result of the binary signal "1" provided by inverter 212A(a) as previously described. At the end of the pulse on line GTP which causes inverter 212A(a) to supply the binary signal "1", flip-flop circuit 214B(a) (FIG. 10) supplies a binary signal "0" on line DTS(a) . At the same time, a binary signal "1" is produced on terminal 11

in the flip-flop circuit 2l4B(a). This together with the binary signal "1" on line GDC causes the AND gate circuit 220B(a) to supply a binary signal "1". The end of the pulse on line GSYNC which causes the pulse on line GTP to terminate also causes flip-flop circuit 180B (Fig. 9A) to change the signal on line GCDT to a binary "1".

This causes the binary signal "1" supplied to the line GDC (Fig. 9B) by the binary signal "1" on the line GAU to cease. However, this is replaced by a binary signal "1" which is supplied as a result of the binary signal "1" on the line GAlT.

The binary signal "1" from gate circuit 220B(a) is supplied to terminal 10 of line drive circuit 228(a) and to an input

in the AND gate circuit 220A'(a). The other input also receives a binary signal "1" and as a result inputs 7 and 10 of the drive circuits 230(a), 232(a) and 23^(a) as well as input 7 receive

in the drive circuit 228(a) also binary signals "1". Accordingly, each of the driver circuits 228(a), 232(a) and 234(a) is set to transmit signals via lines DTØ(a) and DTØ(a) - DT7(a)

and DT7(a) to these via the wires CGDØ(a) - CGD7(a).

The signal on the line DTØ(a) as shown applied to the input of the differential line receiver 160 supplies this signal to the 3-8 line decoder 164. The binary coded signal supplied via the lines GA8, GA9 and GA10 causes the 3-8 line decoder 164 to select the binary signal supplied via line CGBØ(a) to input 4 and delivers a corresponding signal from output 5 via line CGBØ to input 3 in data selector 156 (fig. 8). If another cabin was selected,

would the signals on the lines GA8, GA9 and GA10 select the signal for this cabin supplied to the line CGBØ. In addition, the signals on the lines DT1 to DT7 are supplied via the lines CGB1 to CGB7

to the inputs in the data selectors 156 and 158 (fig. 8). The signals correspond to the signals supplied via the lines CGBØ -

CGB7 to inputs 3,6,10 and 13, supplied to outputs 4,7,9

and 12 in the data selector pair 156 and 158 as will be described below. The outputs in the data selector pair 156 and 158 are connected by means of the wires GDØ - GD7 to the terminals in the two-way drive circuits 54 and 56 as shown in fig. 4 for supplying binary signals representing data stored in the data storage device CRAM(a) to the data inputs of the group processor GPU.

At this time, the flip-flop circuit 78B (Fig. 5) supplies a binary signal "0" on the line GWX. This is because the flip-flop circuit is reset at the end of the last time interval T3 for the group processor GPU (Fig. 4) by the binary signals on the lines GT3 and G01. The binary signal "0" on the line GWX together with the previously mentioned binary signal "1" on the line GCDT (Fig. 9B) supplies a binary signal "0" on the line GTP. This maintains the output signal from AND gate circuit 220C(a) (Fig. 10) on line GWD(a) as binary signal "0".

The binary signals "0" on the lines DTS(a), GWD(a) and HL1 cause the data selector 4l6(a) (Fig. 13) to supply binary output signals "0" on the outputs 4,7 and 9> These cause the data selectors 4o8 (a) and 4l0(a) supply address signals on lines GCAØ(a) - GCA7(a) to the cabin data storage device CRAM(a). As a result of the output signals from the data selector 416(a), the cabin data storage device CRAM(a) supplies signals which are stored therein addressed at the address on the lines CDOØ(a)-CD07(a). These signals are when supplied to the cabin equipment in fig. 11 are not effective in providing a result at least because the cabin processing device is in a standby state and will not accept signals even if applied to it because latch circuits 358(a), 362(a), 360(a) and 364(a) is not in operation as a result of the binary signals supplied via the lines CTl(a) and CT2(a).

The signals on_the lines CDOØ(a) to CD07(a) are also supplied to the AND gate circuits 4l2(a) and 4l4(a) (fig. 13) - As a result of the binary signal "0" on the line DTS(a), these gate circuits will supply these signals to the wires CGDØ(a) and CGD7(a). These signals are transferred to the line drive circuits 228(a) 3230(a), 232(a) and 234(a), (Fig. 10) and are supplied to the lines DTØ(a) to DT7(a).

The group processing device GPU (Fig. 4) continues to deliver pulses on the GSYNC line. At the end of the first of these to be supplied- after the supply of the binary signal "0" to the line DTS(a), the flip-flop circuits supply l80A

and 180B (Fig. 9A) binary signals "1" to inputs 2 and 13 of NAND gate circuit 174A. After the generation of the next pulse on the GSYNC line, the NAND gate circuit 174A delivers

a binary signal "0" on terminal 3 of the flip-flop circuit 172A.. This causes a binary signal "1" on the line GSUS which is supplied to the group processor GPU (fig. 4) so that it terminates its waiting state and goes into the time interval T3.

Before the group processor GPU (Fig. 4) enters its wait state and at the end of the preceding time interval T2, a binary signal "0" is supplied via wire GT2 to terminal 3 of the flip-flop circuit 76A and causes it to supply a binary signal "1" on terminal 5. This signal is combined in gate circuit 80C with the pulse on line GSYNC when the group handler enters time interval T3 to deliver a binary signal "1" on line GT3A. This signal together with the opcode binary "1" signal on line GAlT for the complement of the opcode signal on line GA14 causes gate circuit 80A to supply a binary "1" signal on line GRX. This signal is applied to the input 9 of the NAND gate circuit 174C (Fig. 9A). In addition, NAND gate circuit 174C receives a binary signal "1" on lines GA13 and GCDT from terminal 11 of flip-flop circuit 180B which supplies a binary signal "0". This is supplied via the line GRCE to the control input 15 in the data selector pair 156 and 158 (fig. 8).

The binary signal "1" on line GCDT also causes the binary signal "1" applied to input 6 of selector 200 (Fig. 9B) to be applied to line G8B. This input signal and consequently the signal on the line G8B are binary signals "1" as a result of the binary signal "1" of the operation code on the line GA14. The binary signal "1" supplied via wire G8B affects the data selector pair 156 and 158 (Fig. 8) so that the signals supplied to inputs 3,6,10 and 13 are transferred to outputs 4,7,9 and 12. As a result of the binary signal "0"

on line GRCE, data selectors 156 and 158 will supply binary signals representing data received by the group processor via lines GDØ-GD7 to the bidirectional data inputs of drive circuits 54 and 56. The drive circuits transmit the complements of the signals supplied to them via lines GDØ-GD7 to the inputs of the data processor after receiving a binary signal "1" supplied via the line GDIEN in conjunction with the binary signal "0" supplied via the line GCS.

The signal on the wire GCS at this time is

binary "0" because at the end of the last time interval T2

a binary signal "0" was applied via the line GT2 to the terminal 11 of the flip-flop circuit 76B (Fig. 5) and causes a binary signal "0" to be applied via the line GCS. The binary signal "1" on the line GDIEN is produced as a result of the binary signal "1" from the AND gate circuit 80C combining with the binary signal "1" from the output 7 of the 3-8 line decoder 74 supplied via the line GPCW to produce a binary signal "1" on the wire GDIEN. The signal on the wire GPCW

is a binary signal "1" as a result of a reading operation being carried out at such a time when the signals on the line GA14 and GA15 are binary "0" resp.' "1". With binary signal "0"

on line HL1 it is clear that these signals will produce a binary signal "1" on line GPCW from decoder 74.

As a result of the supply of the binary signal "1"

on the wire GDIEN and the binary signal "0" on the wire GCS will the data signal indicating the position of the cabin a

now be transferred to the group manager GPU. The cabin processor CPU(a) can now be reset to operation. This is happening

because during the next time interval T1 and T2 for the group processor GPU, a binary signal "0" is applied via line GA13- This causes the line driver circuit 196A (FIG. 9B) to supply a binary signal "0" to the line XCRDY(a) which is applied to the receiver 210 (a) (Fig. 10). As a result, a binary signal "1" is supplied via the wire CSUS(a) to the terminal 17 of the data processor CPU(a) (Fig. 11) and releases it from its

waiting state. At the same time, the inverter 212D (FIG. 10) supplies a binary signal "0" to the reset inputs 3 and 8 of the flip-flop circuits 214A(a) and 214B(a) to produce a binary signal "1" on the line DTS(a ) for setting the cabin processor CPU(a) to communicate with its cabin data storage device CRAM(a) once again. At the same time, a binary signal "0" is produced on line GCDT as a result of binary signals "1" on lines GSUS and GA13 as previously described.

From the foregoing it appears that the group handler GPU can use information relating to the position of cabin a to decide whether the cabin should be stopped as a result of registered main floor calls. It can do this by requesting information about the recording of such calls from the equipment in fig. 3A and 3B in the same way as explained for the cabin a in terms of cabin call registration information for the seventh floor from the equipment of fig. 14. The group processor GPU will also request information regarding the direction of movement of cabin a in the same way as explained for the request for information about the position of cabin a. After the position of cabin a has been determined and its direction of movement was correct for stopping in response to a registered main floor call, which information can be transmitted to the cabin data storage device for cabin a so that its processing device GPU(a) can use this to initiate a stop of cabin a in the same manner as explained above for initiating a stop of cabin a as a result of a cabin call on the seventh floor. To do this, a signal must be transmitted by the group processor GPU to a specific position in the cabin data storage device CRAM(a) (fig. 13) - This happens in a similar way as explained where the group processor GPU receives information from the cabin data storage device CRAM(a).

The operation of storing or reading data in the cabin data storage device CRAM(a) is carried out in the same way as previously described for reading data from this until the transfer of the relevant address in the data storage device via the lines GCAØ(a)-GCA7(a) to the selectors 4o8(a) and 4l0(a)

(fig. 13)- As this operation includes the storage of data is

the signal on the line GAlH for the address code a binary signal "1" as opposed to the binary signal "0" described for the reading operation. Accordingly, the complement of line GA14 (Fig. 9B) is a binary signal "0". Instead of a binary signal "1" being thus supplied via the line GDC (Fig. 9B) after the supply of a binary signal "1" on the line. GCDT to the selector 200, a binary signal "0" is applied to this line. Gate circuits 220B(a) and 200A(a) (Fig. 10) do not provide any binary "1" signals to drive circuits 228, 230, 232 and 234 for the read operation. Instead, binary signals "0" are supplied to the inputs 7 and 10 to prevent the operation of these drive circuits so that they do not prevent the reading.

The binary signal "1" on the line GAl4 also produces a binary signal "1" on the line GCTE during the group processor's wait state so that the drive circuits 122 to 130 during the storage as opposed to the binary signal "0" supplied via the line GCTE during the read , prevent these drive circuits from interrupting the operation.

The binary signal "0" on the line GA14 also causes the generation of a binary signal "0" on the line GRX (Figs. 5 and 9A) during the storage in contrast to the binary signal "1" which is generated on this line during the reading. As a result of this change, a binary signal "1" is applied to line GRCE (Fig. 9A). This prevents the selectors 156 and 158 (fig. 8) from delivering the signal on the wires GDØ-GD7 and interrupting the storage operation.

When the group processor GPU enters the time interval T3, it will, as previously explained for the reading operation, ensure that the data signals are transferred to the cabin data storage device CRAM(a) via the lines GDØ-GD7 because this is a storage operation. These signals are transmitted via the selectors 100, 102, 116 and 118 (fig. 7) to the lines GCDØ(a)-GCDØ(h) and GCD1 - GCD7 to the drive circuits 122-130. As only cabin a will receive these signals, only its equipment will be explained here. These drive circuits transmit corresponding signals on the wires DTØ(a) and DTØ(a) - DT7 and DT7 to the receivers 236(a) - 242(a) (fig. 10). Corresponding signals are supplied via the lines GCBØ(a) - GCB7(a) by these receivers to the data selectors 400(a) and 402(a) (fig. 13).

Since the binary signal "1" on the line GAlh has produced a binary signal "0" on the line GPCW (Fig. 5) when the time interval T3 reaches its last quarter, the binary signal "0" on the line GT3 (Fig. 5) will cause that the flip-flop circuit 78B produces a binary signal "1" on the line GWX. This signal causes selector 200 (Fig. 9B) to supply a binary signal "1" on line GTP for use in receiver 216(a) (Fig. 10). I. meanwhile during the wait state as previously explained for the read operation, the flip-flop circuit 214B(a) (Fig. 10) has supplied a binary signal "1" from its terminal 11. This in combination with the binary signal "1" supplied on terminal 2 of receiver 216(a) as a result of the signal supplied via line GTP causes gate circuit 220C(a) to supply a binary signal "1" on line GWD(a).

The binary signal "0" on the line DTS(a) (Fig. 13) which was produced during the wait state as explained for the reading operation, in combination with the binary signal "1" on the line GWD(a), causes the selector 4l6(a) supplies a binary signal "1" to the inverter J4l8B(a) (Fig. 13)- This causes a binary signal "0" to be applied to terminal 20 of the cabin data storage device CRAM(a) and terminal 15 of the selectors 400(a) and 402(a). Meanwhile, during the standby state, the binary signal "0" on the line ■DTS(a) in combination with the binary signal "0" on the line HL1, has caused the selectors 4o8(a) and 4l0(a) to supply the address signal to the cabin data storage device CRAM( a). As a result, the data signals on the line GCBØ(a) and GCB7(a) are transferred to the cabin data storage device CRAM(a) for storage therein.

The cabin processor CPU(a) is released from its interrupted state in the same way as explained for the release from this state after the reading operation. It is clear from the foregoing how the information that the cabin is to begin a stop operation as a result of a main floor call can be used by the cabin operator CPU(a) to allow the cabin control equipment to perform such an operation and consequently this shall not be described in more detail here.

As mentioned above, the group manager operates the GPU

in accordance with the group program of instructions to cause interruption of the order of operation and the order of operation of a single selected cabin processor CPU(a) to receive cabin data signals from or transfer group data signals to the relevant cabin data storage device CRAM(a). However, it is clear that in the exemplary embodiment the group processor will not transfer 8-bits of useful information simultaneously to a single cabin data storage device, but information contained in a particular one of the 8-bits is useful for a particular cabin. When it is desired to transfer information to cabin a, this is supplied via the wire GDØ and this will result in a signal corresponding to the information supplied via the wire DTØ(a). In a similar way, information for the cabin b will be supplied via the line GDI, which results in a signal on the line DTØ(b), etc.

In the design example, the group handler also works in the same way as described for cabin a, but. simultaneously causes interruption of the order of operation for all cabin handlers to receive cabin data signals from or transmit group data signals to the relevant cabin data storage device CRAM. Since the operation in which the group processor receives cabin data signals from or transfers group data signals to the cabin data storage device CRAM(a) is similar to the operation in which it simultaneously receives cabin data signals from or transfers group data signals to each of the cabin data storage devices, only the difference between these two operations shall be described here.

It is assumed that the group processor receives instructions for receiving cabin data signals from the cabin data storage device assigned to each cabin. The group handler works in accordance with this instruction and supplies an address code signal to the latch circuits 58, 62, 60 and 64 in the manner described above which causes the group handler to interrupt the sequence of operations. In accordance with the assumed instruction, the latch circuit 60 supplies a binary signal "0" on the line GAU and a binary signal "1" on the line GAU opposite to the binary signals "1" and "0" supplied via these lines to indicate data transfer between the group handler and cabin data storage device assigned to a single cabin as previously described.

The binary signal "0" on line GAU causes data selectors 192 and 194 (Fig. 9B) to supply the complements of the signal applied to inputs 2,5,11 and 14 to driver circuits 196A, 196B, 198A and I98B and to the additional driver circuits which are assigned to cabins c-g (not shown). As a result, driver circuit I96A supplies a binary signal "1" via line XCRDY(a) to receiver 210(a) (FIG. 10) to cause it to supply an interrupt signal to cabin processor CPU(a) (FIG. 11) as previously described. At the same time, in the same manner, a binary signal "1" is separately supplied via lines XCRDY(b) to XCRDY(h) to circuits similar to those shown in FIG. 10 and which is assigned to each cabin to cause these circuits to deliver an interruption signal to the cabin operator assigned to them.

After the supply of the interrupt signal to each cabin operator, the address signals are supplied via two-way signal transmission lines DTØ(a), DTØ(a), to DTØ(h), DTØ(h) and DT1, DT1 to DT7 and DT7 to the equipment assigned to each cabin on the way in which the address signals are supplied via the wires DTØ(a), DTØ(a) and DT1, DT1 - DT7 and DT7 to the circuits assigned to the cabin a. However, before these address signals can be transferred to the drive circuits•which are assigned to each cabin handler corresponding to the drive circuits 228a, 230a, 232a and 23a which are assigned to the cabin a as shown in fig. 10, they must be prevented from interfering with these address signals. Accordingly, the signals on lines GA8, GA9 and GA10 are selected to cause decoder 190 (Fig. 9B) to supply a binary signal "1" to NAND gate circuit 202B(a). As a result of this signal and the binary signal "1" on the line GAU, the NAND gate circuit 202B(a) causes a binary signal "0" to be applied from terminal 7 of the selector 200 to the drive circuit 204B(a). As a result, the drive circuit 204B(a) supplies a binary signal "0" via the common line GDC in place of the binary signal "1" as previously described. This binary signal "0" is supplied to the receiver 216A(a) (Fig. 10) which supplies it to the register 222(a) for storage therein when the NAND gate circuit 218A(a) supplies a binary signal "1"

to this as previously described. In addition, the binary signal "0" is also stored in the register corresponding to the register 222(a) assigned to each cabin. As a result, will the register 222(a) as shown in fig. 10 for the cabin a and similar registers supply a binary signal "0" to the AND gate circuit 220A(a) and similar gate circuits assigned to other cabins to prevent the drive circuits 228(a), 230(a), 232(a) and 23Ma) assigned to cabin a and similar drive circuits assigned to the other cabins from interfering with the signals on wires DT1, DTT to DT7 and DT7. Furthermore, the binary signal "0" on the line GDC will cause a binary signal "0" to be applied to the AND gate circuit 220B(a) and similar gate circuits (not shown) to prevent the driver circuit 228(a) from

and similar drive circuits assigned to the other cabins, from interfering with the address signals to be transmitted to the circuits assigned to each cabin.

As previously described for the read operation, the address signals are applied via data selectors 100 and 102 (Fig. 7) to data selectors 116 and 118 and via lines GCD1-GCD7 to driver circuits 126,128,130 and 132. At this point, the least significant bit LSB of the first eight bits of the address signal supplied via the selectors 116 and 118 and the lines GCDØ(a) - GCDØ(h) to the drive circuits 122,123,

124 and 125 - The drive circuits 122-125 deliver bit LSB of the first eight bits of the address signal via the lines DTØ(a) and DTØ(a) separately to the receiver 236(a) as shown in fig. 10 and via the wires DTØ(b), DTØ(b) to DTØ(h) and DTØ(h) separately to similar receivers assigned to each cabin. The drive circuit 126,28,130 and 132 supplies the seven most important

bit of the address signal via wires DT1, DT1 - DT7 and DT7, to. receivers 236(a), 238(a), 240(a) and 242(a) and to similar receivers assigned to each of the cabins. Consequently, based on what has been described previously where the address signals are supplied to the cabin data storage device CRAM(a), it is clear that similar circuits assigned to each of the cabins work in the same way to supply the first eight bits of the address signal to the cabin data storage device

CRAM(b) to CRAM(h) (not shown).

It is assumed that data stored in positions in the cabin data storage devices and identified by . the address signal, is supplied to the group processor. As previously described, this is a reading operation and as previously described during the reading operation of the drive circuits 122-130 (fig. 7) these are prevented from interfering with the signals supplied via the lines DTØ(a), DTØ(a)- DTØ(h) and DT^ (h) and DT1-DTT to DT7 and DT7.

During this reading, a single data bit is received by the group processor from the cabin data storage device assigned to the relevant cabin processor in contrast to the reading previously described where up to 8 bits are received by the group processor from the cabin storage device CRAM(a) which is assigned to the cabin processor CPU(a). The data bit received from the circuits assigned to each cabin is transmitted via lines DTØ(a), DT^(a) to DTØ(h) and DTØ(h) to the receivers 160, 161, 162' and 163 as shown in fig. 8.

Although the following description is directed to the circuits which

is assigned to cabin a which delivers a single data bit on the wires DTØ(a) and DTØ(a), it is also possible that the circuits assigned to the remaining cabins transmit a single bit via the wires DTØ(b), DTjZKb) - DTØ(h ) and DT^(h).

As previously described during reading, selector 200 (Fig. 9B) supplies the binary signal "1" on line GA14 to driver circuit 204B which transmits this signal via

the common wire GDC to the receiver 2l6(a) (fig. 10).

As a result of the binary signal "1" from the receiver 216(a) and the flip-flop circuit 214B(a), the AND gate circuit 220B supplies a binary signal "1" to the terminal 10 of the driver circuit 228(a) which transmits the signal receives from the cabin data recording device CRAM(.a) via the line DTØ(a) and DTØ(a) to the receiver l60 (fig. 8). The circuits assigned to the remaining cabins similarly transmit data signals via lines DTØ(b), DTØ(b) to DTØ(h) and DT^(h) to receivers l60, l6l, 162 and 163. These signals are supplied via lines CGBØ (a) - CGBØ(h) to selectors 156 and 158. At this time selector 200 supplies the binary signal "1" from NAND gate circuit 202B (Fig. 9B) via wire G8B to selectors 156 and 158 which supply the .signals via wires CGBØ(a) - CGBØ(h) to the wires GDØ-GD7 which are connected to the two-way drive circuits 54 and 56

(Fig. 4) for transfer to the group handler GPU.

If the address code is such that the group handler transfers a single bit of data to each cabin, the first eight bits of the address are first supplied to the cabin data storage device assigned to each cabin as described. During time interval T3 for the group handler, data is supplied via lines GDØ to GD7 via selectors 100 and 102 (Fig. 7) to selectors 116 and 118. At this time, the binary signal "1" from the AND gate circuit 202B (Fig. 9B) is changed and supplied via wire G8B to the data selectors 116 and 118 (fig. 7) so that these supply signals corresponding to the signal on terminal 4 in the data selector 100 via the wires GCDØ(a) to GCDØ(h) to the drive circuits 122, 123, 124 and 125. The remaining circuit operations correspond to those described under the storage operation where data is transferred to the cabin data storage device CRAM(a) which is assigned to cabin a.

Claims (12)

1. Control device for multi-car elevator systems serving a number of floors, comprising group control equipment common to a number of cars with main floor recording device generating main floor signals, and car control equipment for each car with car operating apparatus, call recording device and car position indicator, the latter two of which generate call and cabin position signals, which control device is connected both to cabin .the control equipment and the group control equipment for receiving cabin call and cabin position signals and main floor signals, characterized by a program storage device which stores control instruction programs for each cabin and for groups of cabins, a cabin processing device which is connected to the program storage device in order to perform a first set of operations according to each cabin program to deliver a first set of cabin control signals in accordance with associated cabin call and cabin position signals and supply the first cabin control signal to the associated cabin operating apparatus, and a group processing device connected to the program storage device and to the cabin processing device to sequentially perform a second set of operations according to each group program to supply group control signals in accordance with the selected first cabin control signals <p> g main floor call signals to the cabin processing device which supplies second cabin control signals in accordance with the group control signals and distribute the other cabin control signals to the relevant cabin operating device in order to put the associated cabin into operation in accordance with the main floor's call signals as overriding group. 2. Device according to claim 1, characterized in that the cabin processing device comprises a separate cabin processor and a separate logical cabin circuit for each cabin, that each logical cabin circuit connects each cabin processor with the program storage device, and the group processing device and the cabin control equipment separately with the associated cabin, and that each cabin processor in accordance with the cabin program, it delivers the first and second cabin control signals in accordance with cabin calls, cabin position signals and group control signals via the associated cabin logic circuit to the relevant cabin operating device for operation of the associated cabin as part of the overriding group. 3. Device according to claim 2, characterized in that the group processing device comprises a group processor and a logical group circuit which connects the group processor with the program storage device and the group control equipment, and via the separate logical cabin circuit with each cabin processor, that the group processor in turn performs the second order of operations in accordance with the group program for the delivery of group control signals in accordance with the main floor call and selected first cabin control signals from each cabin attendant, and that the group control signals are supplied to the group control equipment and via the logical group circuit to each cabin attendant to control the operation of the relevant cabins as an overriding group. 4. Device according to claim 3, characterized in that the logical group circuit comprises a group setting signal generator which is connected to the group processor which in turn performs the second set of operations upon receipt of a specific group instruction to receive a first or second cabin control signal from or send a group control signal to a specific cabin handler, which group handler works in accordance with the specific group instruction and causes the group setting signal generator to deliver a group setting signal which is supplied to the group handler to set it to perform the second set of operations in turn. 5. Device according to claim k, characterized in that the logical group circuit comprises a cabin setting generator which is connected to each cabin manager and which, upon receiving the specific group instruction containing an address code with a cabin selection signal that identifies a selected cabin, which group manager delivers the cabin selection signal to the cabin setting signal generator for providing a cabin setting signal for the selected cabin, which cabin setting signal supplies the cabin setting signal to the selected cabin handler to set it to perform the first set of operations in turn. 6. Device according to claim 5, characterized in that each logic circuit comprises an associated data storage device for receiving and storing the associated first and second sets of cabin control signals and group control signals, that the logical group circuit comprises a separate data transmission signal generator which is assigned to each cabin and which is connected to the respective cabin's logic circuit and with the cabin setting signal generator, and that each data transmission signal generator works in matching a cabin setting signal for the cabin in question to provide a data transfer signal indicating that the associated cabin logic circuit is set so that a first or second cabin control signal can be supplied from the associated cabin data storage device to the group processor or that the group processor can send a group of control signals to the associated cabin data storage device . 7 • Device according to claim 6, characterized in that each logical cabin circuit comprises cabin data switches which each connect the associated cabin handler with the associated cabin data storage device so that the associated cabin handler must deliver the first and second cabin control signal to the relevant cabin data storage device and retrieve these again, and that the cabin data switches operate in accordance with the associated data transmission signal to disconnect the associated cabin data storage device from the associated cabin processor and connect this storage device to the group processor for delivery of a first and second cabin control signal from the associated cabin data storage device to the group processor or to send a group control signal _from the group processor to the relevant cabin data storage device . 8. Device according to claim 7, characterized in that when the specific group instruction is received by the group processing device, this contains address signals that identify a position in the selected cabin's data storage device, in which a specific first or second cabin control signal is stored that the relevant group processor must retrieve or in which a specific group control signal is to be stored, which address signals are transmitted from the relevant group processor to the cabin data storage device via the cabin data switch in accordance with the connection and disconnection which is due to the generation of the associated data transmission signal. 9. Device according to claim 8, characterized in that the specific first or second cabin control signal is taken from or the specific group control signal is stored in the relevant cabin data storage device by the group processor by transmission via the relevant cabin data switch in accordance with the connection or disconnection which is due to the generation of the associated data transmission signal. 10. Device according to claim 9, characterized in that when the group processor receives the specific group instruction, the address code it contains can identify a number of cabins to be selected, and the group processor can extract a first or second cabin control signal from the cabin data storage device for each selected cabin at the same time or store it same group control signal in the cabin data storage device for all these cabins at the same time. 11. Device according to claim 6, characterized in that the program storage device comprises a group program storage device which stores the group program, and a number of cabin program storage devices which each store a cabin program for an associated cabin and which contain instructions for the associated cabin operator to store first and second cabin control signals in an identified position in the associated cabin data storage device for retrieval by the group processor, and that the group program storage device comprises instructions for the group processor to store group control signals in identified positions in the cabin data storage devices for retrieval by the associated cabin processor, which group program storage device also includes instructions for the group processor to retrieve first and second cabin control signals from the relevant cabin data storage device. 12. Device according to claim 5, characterized in that the logical group circuit comprises a group register in which the group processor stores the address code including the cabin selection signal, and from which the cabin selection signal is supplied to the cabin setting signal generator until the group processor, in accordance with the execution of the second set of operations, delivers another address code to the group register .