CA1116325A - Elevator control system - Google Patents

Abstract

AN ELEVATOR CONTROL SYSTEM

Abstract:
An elevator control system having a car processor, its associated car processor memory and car logic circuitry individually associated with each car to apply a first set of car control signals to the car associated control equipment to cause it to operate the car in a particular manner and having a group processor, its associated group memory and group logic circuitry common to each of the cars receiving hall call sig-nals and selected first car control signals and in response thereto applying group control signals to selected car pro-cessor circuitry which operates in response thereto to apply second car control signals to its associated car control equipment to cause it to operate its associated car as a member of a supervised group. Whenever the group processor is to receive a first car control signal from or is to transmit a group control signal to the selected car processor circuitry, the group logic circuitry operates to cause the group processor and the selected car processor to suspend their sequence of operations and to cause the signal transfer therebetween.

Description

This invention relate~ to elevator control ~stems.
More particularly, it concerns a control system for control-ling the operation of a plurality of car~ of an elevator in-stallation as a supervised group.
Supervisory control systems for groups of elevators normally possess a highly desired advantage of maintaining th~
car operable to serve the landings of a building notwithstand-ing the equipment w~ich controls the cars a~ a supervised group might fail~ This advantaye is u~uall~ accomplished ~y providing an individual control equipment for each of the cars and common supervisory control equipment separate from ~he in-dividual contxol equipment for controllin~ the cars as a super~ised group.
The advent o the general purpose computer having the capability of assuming both the control fu~ctions for each car in addition to the sùpervisory control function.s for the group has had little impact on the elevator indus-try because - of the desire to retain the above-mentioned desirable advan tage. Cost considerations prevented the utili~ation of a separate general purpose computer ded.icated to each car of t~e elevator installation for controlling its associated car and :
an additional computer for controlling the- op~ration o~ the cars as a supervised group. Furthermore th~ utilization of separate general purpose computers in an elevator in~tallation in this manner would require a solut;.on to ~e problem of , .,.. -transmitting control signals between ~he supervisory computer and each of the car control computers~
More recent developments in t~e semiconductor indus~
try have led to the 1GW cost production o such devices as microprocessors and semiconductor memories having the capa~
bilities of being programmed for specific uses. As a xesu~t a separate microprocessor and memory dedicated to each one o~
~ the cars of ~he group and programmed to direct the operations ; of its associated cax and an additional mi.croprocesso~ and ~ 35 memory combination programmed to direct the operation o~ the s separate cars as a supervised group is now economically fea-sible. ~o be operable such an ele~ator control system depends on the ability of the processor and memory combination dedi-cated to direct the supervisory control functions to transmit supervisory signals to and to .receive car control signals from the processors and memories associated with each o~ t~e cars of the elevator installation~
It is an object of this invention to provide an im-proved group supervisory elevator control system.
It i~ another object o~ this invention to provide an elevator control system employing moder~ electrical switching equipment.
It is another object of this invention to provide apparatus to enable a group supervisory elevator system com prising a microprocessor and memory combination to transmik signals to and to receive si.gnals from one or more micropro-cessor and memory combinations associated with the car.s of the elevator systems.
In accordance with the invention there is provided a control system for use in an elevator installation having a plurality of cars serving a plurality of floors~ Th~ elevator installation includes group control e~uipment compri~ing hall registration means for producing ~all call signals and cax control equipment individual to each o~ ~he cars of the eleva=
tor installation comprising car operating apparatus t car call registration means and car position signifyinq means~ the :~ latter two producing car call and car position s.ignals respec-:: tiv~ly. In response to the hall ~all signals, car call sig~
nals and car position signals the control system produces irst and second car control signals and group control signals : ~ w~ich are applied to the car operating apparatus i.ndividually associated with each one o~ -~he cars to cause the car oper~
ating apparatus to control its associated car as a mem~er of a supervised group~ The control system includes car processing ~5 means, group processing mean~ and program storage means stor-.. . _ 3 ~

ing control program~ of instructions including a car progr~m of instructions and a group program of instructions. ~h~ cax proce~sing means in following the car program of instructions in a step by step manner sequentially performs a first set of operations to produce first car control signals in response to the car call and car position signals of a particular car and to apply the first car control signals to the car operating apparatus associated with the particular car to cause it to operate its associated car in a particular manner. The group processing means in following its group program o instruc-tions in a step by step manner sequentially performs a secondset of operation~ to produce group control signals in re~pon3e to selected first car control signals and hall call signals and to apply the group control signals to the car processing means. In re~ponse to the group control signals the car pro-cessing means produces second car control signals which are applied to the individual car operating apparatus to cau e the car operating apparaku~ to operate the cars as members of a supervised group. The car processing means includes a separate car processor and separate car logic circuitry associated with each of said cars, said separate car logic circuitry connecting each car processor to said program storage means, said group processing means and the car control equipment individual to its associated car, each car processor performing in accordance with the car program of instructions for its associated car to produce said first and second car control signals in response to said car call and car position signals and said group control signals and to apply said first and second car control signals through said connected car logic circuitry to said associated car operating apparatus to cause it to operate said associated car as a member of the supervised group. Furthermore the group processing means includes a group processor and group logic circuitry connecting said group processor to said program storage means, said group control equipment and through said separate car logic circuitry to each said car processor, said group processor in sequentially , 4 performing said second sequence of operations in accordance with the group program of instructions producing ~roup control signals in response to said hall call signals and selected first car control signals from each said car processor, said group control signals being applied to said group control equipment and through said group logic circuitry to each said car processor to control the operation o~ said associated cars as a supervised group.

Other objects, features and advantages of the in-vention will be apparent to those skilled in the art from t~e following description and appended claims w~en considered in conjunction with the accompanying drawing in which:
Figure lA is a simplified block diagram of a portion sf the disclosed embodiment of the invention associated with all of the cars of an elevator installation for controlling them as a supervised group;
Figure lB is a simplified block diagram of a portion of the disclosed embodiment of the invention associated with a single car of an elevator installation for controllin~ its associated car;
Figure 2 is a simplified schematic diagram of some of the hall call circui~s of the group control equipment of an ele~ator installation including block diagram representations of hall call in~erace circuits:

- 4a -Figure 3A and 3B are simplified schematic diagrams of a portion of hall call selection circuitry oE the control system of the invention associated with the hall call circuits shown in Figure 2;
Figure~ 4, 5 and 6 combined are a simplified sche-matic dia~ram o~ a portion of the circuitry of the control system of the invention for producing si~nals for controlling a plurality o elevator cars as a supervised group;
Figures 7t 8, 9A and 9B combined are a simplified schematic diagram of signal transmission circuitry for con~
necting the portion of the control s~stem shown in Figures 4r 5 and 6 and the circuitry associated with each of the cars, Figure 10 is a simplified ~chematic dia~ram of sig~
nal transmission circuitry associated with a single car for connecting the circuitry shown in Figures 7, 8 r 9~ and 9B to its associated car control circuitry, Figures 11, 12 and 13 combined are a simplified schematic diagram of control circuitry associated with a single car for pxoducing signals or controlling its asso-ciated car;
Figure 14 is a simplified schematic diagram o~ a : portion of car call selection circuitr~ of the control system associated with a single car;
Figure 15 is a simplified schematic diagram of some :` 25 of the car call circuits associated with a single car inclu-diny block diagram representations of cax call :interace circuîts;
Figure 16 is a simplified schematic diagram of car -control signal selection circuitry of the system associated with a single car including block diagram representations of the car operating apparatus interfacing circuitry, Figure 17 -is a simplified schematic diagram of the car operating apparatus associated with a single car;
Figures 18A, 18B and 18C are schematic diagrams of the interface circuitry utilized in each o~ the blocks shown , in Figures 2, 15 and 16; and Figure 19 is a timing diagram illustrating ~he characteristics of some of the signals generated by the apparatus of this invention.
The simplified block diagrams shown in Figures lA
and 1B illustrate a control system for use in an elevator in-stallation having a plurality of cars a, b ~O. h (c through g not shown) serving a plurality of floors of a building (not shown). The elevator installation includes group control equipment shown as a solid line rectangulax block GCE (Fig.
lA) comman to the cars a~ b ... h and car control equipme~t shown as a rectangular block CCE(a) (Fig~ lB) individual to car "a". ~he control system comprises group processing means GPM tFigure lA), car processing mean~ CPM (Figure lB) both repre5ented by dashed line rectangular blocks and program -- storage means shown as separate solid line rectangular blocks -GROM and CROM(a) (Figures lA ~ lB~ respectively.
As shown group processing means GPM and car process-ing means CPM include a plurality of circuits shown as various solid line rectangular blocks interconnected by lines of two thieknesses. The narrower of the two lines represents indi-vidual signal line connections between circuits and t~e broad-er lines indicate a plurality of signal line connections be tween circuits. Both types of signal lines shown in Figures ~^ 25 lA and lB have also been sho~n with appropriate arrowheads to indicate where desirable the direction of signal flow ~etween the variou~ bloeks representing the circuits. In viewing the block diagxam it should be understood that the blocks having an addi tional small letter in parent~esis appended to their reference char~cters represent circuitry individually asso-eiated with a respective car of the elevator system. Further-more in viewing Figure lB it is to be understood that the block diagram represents the circuitry associated with car " a"
and it is also to be understood that similar circuitry is pro vided for each additional car of an elevator installation.

h~ er~

Because the circuitry associated with each of the cars is similar, the herein disclosed embodiment of the invention has been simplified where deemed practical by showing only the circuitry associated with car "a" although it is to be under-stood that the equipment shown is capable o~ use in a system having up to eight cars, a - h.
Group processing means GPM (Figure lA) comprising a group processor GPU and associated group logic circuitry shown as a plurallty of rectangular ~locks in Figure lA is shown connected to group program storage means GROM, group control equipment GCE and car processing means CPM (Fig~ lB). As indicated in Figure lA bi-directional signal lines GD0~7 interconnect group processor GPU and its associated group logic circuitry including group to car logic circuitry G/C, group data storage means GRAM and group register GR. The output lines GA0-15 of the group register G~ interconnect group to car logic circuitry G/C, group data storage means GRAM, group program storage means GROM, and group equipment selection circuitry GESC.
Lines GIO-7 and GDO~7 connect group program storage means GROM and group data storage means GRAM to the group switching means GS and lines GD0-7 connect group switching means GS to the group processor GPU.
Individual signal lines .~HU, 2HD O~ THD connect the group control equipment GCE to the group equipment selection circuitry GESC to recei~e signals representing registered hall calls and apply them along line GD0 to group processor unit GPU. In addition group processor unit GPU applies signals along line GD0 to group equipment selection circuitry GESC to have it transmit hall call reset signals along lines lHU, : 2HD ..................... THD, to group control equipment GCE.
As illustrated in Figure lA, lines DT0(a), DT0(b) ...DT0(h) connect the group to car logic circuitry G/C in-dividually to car to ~roup logic circuits also included as part o the group processing means shown as rectangular blocks C/G(a), C/~(b) and C/G(h). Those for cars, c ~hrough g are not shown ~or simplification purposes. In addition seven signal lines DTl - DT7 connect the group to car logic cir-cuitry G/C to each of the car to group logic circuits C/G(a), etc.
rnhxee additional individual signal lines XCRDY(a), XCRDY(b) and XCRDY(h) are shown in Figure lA, it being under-stood that similar lines for cars c through g are not shown for simpli~ication. These llnes connect the group to car logic circuitry G/C to the car to group logic circuits C/G(a) etc. illustrated in Figure lA~ Group to car logic circuitry G/C is also connected by line GSUS to the group processor GPU (Figure lA).
The block diagram representation of the car process-ing means CPM (Fig. lB) is shown with re~erence characters having an appended suffix "(a)" representing the circuitr~ of the control system associated with car "a". Because of the similarity of the circuitry associated with each car the ~ol-lowing description of Figure lB although limited to the cir-cuitry associated wit~ car "a" will be understood to be also - applicable to the remaining car associated circuits (not .~ .
- shown).
Car processing means CPM comprises a car processor CPU~a) and associated car logic circuitry shown as a plurali-ty of rectangular blocks connected between car processor CPU(a), car program storage means CROM(a), car control equip-ment CCE(a), and car to group logic circuitry C/G(a) of group processing means GPM (Figure lA).
As shown in Figure lB bidirectional sisnal lines CD0~a) - CD7(a) interconnect car processor CPU(a) wit~ car data switc~ing means SW(a) and car register CR(a). The output line~ CA~(a) - CA15 ~rom car register CR(a) intexcon-- nect it with car data switching means SW(a), car program storage means CROM(a), and car equipment selection circuitry CES(a). Car data switching means SW(a) is also connected to the car to group logic circuitry C/G(a) ~Fig. lA) by means of lines GCA0(a~ - GCA7(a); GCD0(a) ~ GCD7(al and DTS(a)~ ~n ad-dition car data switching means SW(a) is connected by lines CIO0(a) - CIO7(a) to car program storage means CROM(a) and by lines CDO~(a) - CDO7(a) to the car data storage means CRAM(a).
Car processor CPU(a) is connected to the car to group logic circuitry C/G(a) (Fig. lA) by means of line CSUS(a).
The schematic diagrams illustrated in a simplified manner in Figures 2 to 18 include a plurality of commercially made circuits identified herein b~ reference numerals which correspond to a particular manufacturer's part numbex~ In this description wherein the commercially available cixcuitry is usea, only certain input, output and control signal connec-tions are described it being understoad ~hat those input, output or control connections not descrîbed are made in ac-cordance with the manufacturer's standard instructionsO It is also to be understood that where a particular manufacturers part number is used ~hat is the part employed in the construc-ted embodiment disclosed herein. It is contemplated that equivalent Par~ of other manufacturers could be substitutad therefor.
For the purpose of illustxating the typical- and, nor, or, nand and inversion functions the standar~ 8ymbo~s have been used. However, to identiy ~hose circuits w~ich are common to a particular commercial part containing a plurality of such cir~uits each circuit of the same commercial part is identified by the same reference numeral having an appended sufi~ letter.
In the following description a continuous binary one level signal or voltage i~ indicated a~ being applied along a line identified by the reference characters LlO and a contin~
uous binary level zero signal is represented as being applied ~ along a line iden~ified by the reference characters HLl.
- Many of the signal lines are shown in more than one figure. Whenever this occurs a brac~eted numeral indicative of the other figure in which the line is also shown is appen-ded to the reference characters which identify the line.
Hall call registration circuits utilizing the well-known cold cathode gas tube touch buttons lHU, 2HD ... THD of the RCA type lC21 or equivalent are shown in Figure 2 for the main landing and landings 2 - 6, 7 - 11 and 12 - T as similar-ly shown in U. S. Patent No. 3,614,995. The operation of the constructed em~odiment described herein was patterned on the operation of the system of that patent and its disclosure may be referred to for certain useful background information. A
complete description of the operation of the buttons is found in that patent. While only cextain hall call ragistra-tion circuits are shown herein it is to be understood that similar circuit~ are provided for other landings. Each cathode of each tube is connected to terminal Il of a dif-ferent optical coupler and level converter 18A having the circuitry shown in Figure 18A to be more fully described here-inafter. Each optical coupler and level converter 18A is also connected to line BO and line ACl of power supply PSl. P~wer supply PSl applies a potential of approximately 95 vol~s R.M~S. with respect to line B0 along line ACl and a potential of approximately 150 volts R.M.S. with respect to ground along line BO. For the desired operation of the hall call circuits the potential between line~ ACl and BO and lines BO
and ground are 180~ out of phase wi~h each other.
Each of the gas tubes is arranged to conduct current from line B~ to BO in re~ponse to a person touching the but-tonO q!his register~ a hall call for the ~orresponding landing by applying an increa~ed voltage from the tube cathode to the input terminal Il of ~he associated optical coupler and level .
converter 18A which applies a binary zero signal to the line connected to the output terminal marked S. In order to cancel a registered hall call a binary zero signal i~ applied along the reset line lHUR, 2HUR ~O~ THDR associated with the reset terminal R o the optical coupler and ~evel converter àsso-~ ''~' .

ciated with a conducting gas tube~ In response to the binaryzero signal applied to its reset terminal, the plate potential across the tube is reduced to a value less than its sustaining value and the tube is extinguished thereby cancelling the registered call.
Up hall call registration signals are applied along lines lHUS, 2HUS, fiHUS, 7HUS, lLHUS and 12HUS to input pins ~~~ 12~ 13, 2~ 3, 14 and 15 of a pair of hall call selection units 30 and 32 (Fig. 3~) of th0 Signetics type 74251 or equivalent.
Similarly, down hall call registration signals are applied along lines 2HDS~ 6HDS~ 7HDS~ llHDS~ 12HDS and T~S to input pins 13, 2~ 3~ 14, 15, and 4 of another pair of hall call selec-tion units 34 and 36 (Fig. 3B) of the Signetic~ type 74251 or equivalent. Additional hall call registration signals are ap-plied to other input terminals. Each of t~e output pins 5 ofthe four hall call selection units 30~ 32r 34 and 36 are con~
nected in common to line GD0 to transmit a binary signal to group processor GPU (Fig. 4) corresponding to a selected ha~l call. The hall call which causes the corresponding binary sig-nal to be transmitted along line GD0 is selected ~y applyiny athree bit binary signal along lines GA0, GAl and G~2 to th~ data selection input pins 9, lO and 11 of a particular one of our units and a binary zero signal along line EUl, EU2, EDl or ~D2 to the enable pin 7 of that one of the four unîts in ~ manner to be explained hereinafter Line GD0 is also common to the input pins 13 o four eight bit addressable latches o~ t~e Fairchild type 9334 or equivalent used as hall call reset si~nal selection units 38, 40, 42 and 44 of Figures 3A and 3B~ A hall call reset signal is selectively applied from one of ~he output pins 4, 5t 6t 9 10, 11 or 12 of one o~ the four units along lines IHUR, 2HDR
Ø TMDR to t~e reset terminal of a selected optical couplex and level converter 18A (Fig. 2~ in response to a re~et sig-nal being applied to pin 13 of the corresponding unit along line GD0, to three bit binar~ signal being applied along lines E;32~

GA0, GAl and GA2 to the data selection pins 1, 2 and 3 of the corresponding reset unit 38, 40, 42 or 44 and a binary æero signal being applied along lines EU3, EU4, ED3 or ED4 to the enable pin 14 of the selected unit.
Signal transmission of hall call registration and reset signals is enabled by a pair of Dual 2-Line to 4-~ine Decoder/Demultiplexer units 46 and 48 used as selection de-vices of the Signetics type 74155 or equivalent. The first of these units shown as a rectangular block 46 in Figure 3A
has its input pins 2 and 14 connecte~ b~ line GEX0 to exter-nal interface circuit 72 (Fig. 5). As shown lines GRX and GWX connect input pins 1 and 3 to the cixcuitry shown in Fig. 5 while pin 15 is maintained at ground potential~ In addition line GA3 connects input pin 13 of unit 46 to the group register GR (Fig. 4)~ In response to the signals ap-plied to its input pins unit 46 applies a binary zero signal from its output pins 11 or 12 along the lines EU3 and EU4 to ~ pins 14 of hall call reset signal units shown as blocks 38 an~
`~ 40 (Fig. 3A) respectively or from its output pins 6 and 7 along lines EU2 or EUl to pins 7 of the hall call registra-tion signal units shown as blocks 30 and 32 respe~tively in Figure 3A.
The second of Decoder/Demultiplexer units ~hown as a .
;~ rectangular block 48 in Figure 3B is ena~led to operate in - ~ Z5 response to a binary zero signal applied along line GEX~ from i~ unit 72 of Figure 5 to its input pins 2 and 14~ The input pins 15, 3, 13 and 1 of unit 48 tFig. 3B) are connecked to ground potential along line HLl, line GWX, line GA3 and line GRX respectively~ This unit operates in the same manner as unit 46 described above to produce binary zero signals which are applied to pins 70 6 or 11, 12~ Unit 48 applies a binary zero signal from pin 7 or 6 along line EDl or ED~ to ~npu~
pins 7 of the hall call regiskration signal units shown as blocks 36 and 34 respectively or from pin 11 or 12 alon~ line ~- 35 ED3 or ED4 to pins 14 of the hall reset signal units shown as ~7..~

blocks 42 and 44 respectively in Figure 3B.
Figures 4, 5 and 6 combined show a simplifi~d sche-matic of the interconnections between the group processor unit GPU and as~ociated circuitry which for~ a part of the group processing means illustrated in b~ock d.iagram form in Figure -lA. Although it is contemplated that equivalent units could be satisfactorily employed, the group processor unit GPU of the constructed embodiment is an Intel Single Chip 8-Bit Paral-lel Central Processor Unit type 8008 ~nd includes six 8-~it data registers, an 8-bit accumulakor, two 8-bit temporary registers, a memory stack for storing program and subroutine addresses and an 8-bit parallel binary arithmetic unit which implements addition~ subtraction and logical operations. Each of these operations is performed in a predetermined num~er o time states or machine cycles Tl, T2, T3, T4, T5, TlI, WAIT
and STOPPED, each requiring two time periods o~ a clock pulse signal applied to pins 16 and 15 of ~he group.processor un:it GPU by 800K HZ oscillator 50.
Free xunning oscillator 50 (Fig. 4) may ~e of any well-known variety w~ich produces a pair of complementary pulsed signals of approximately 800K HZ and having a pulse width of one-half its period. These pulses are applied along : lines G01 and G02 and to input pins 16 and 15 respectively of group processor GPU (Fig. 4). T~ese pulses have the charac-teristics shown in the timing diagram of Figure 19, adjacent the reference character G01 and G02~ In response to the 800K
HZ pulsad signals applied to it group processor GPU generates a pulse siynal of approximatel~ 400K HZ having a pulse width of one~~alf its period at its output pin 14 along line GSYNC
to the external group logic circuitry. The signal applied along line GS~NC has the characteristic shown in the ~:im.ing diagram o~ Figure 19 adjacent reerence character GS~N~.
~ines GS0, GSl r~nd GS2 (Figures 4 and 5~ connect ~roup processor pins 13, 12, and 11 and pins 3, 2iand 1 respec- -tively o~ a 3-to-8 line decoder unit 70 of the Signeti~ t~pe - ~3 -7~

74S138 ~Fig. 5) variety or its equivalent.
A normally open switch GST (Fig. 4) having one ter-minal connected to line HLl and its second terminal connected to pin 18 of group processor GPU is manually actuated to its closed position to enable an operator to zero the internal program counter of the group processor. Line GSUS is con-nected to pin 17 of the group processor GPU and to group logic circuitry of Figure 9A which will be described hereinafter.
As shown in Figure 4, lines GD0, GDl ... GD7 connect the group processor data bus pins 9, 8, ... 2 to a pair of 4-bit parallel bidirectional bus driver units 54 and 56 of the Intel type 8226 variety or their equivalent. T~e bidirection-~` al data bus pins 3, 6, 10 and 13 of the pair of bus drivers 54 and 56 are connected to lines GD0, GDl ... GD7 respectively to transmit an eight bit address signal and an eight bit codesignal to the D input pins 2, 3, 6 and 7 of four quadruple bistable latches 58, 60, 62 and 64 of the Signetics type 7475 variety or their equivalent. The four latches 58, 60, 62 and 64 correspond to group register GR of Figure lA and have been 20 so identified in Figure 4. Lines GD0, GDl GD7 are al~o connected to the output pins 4, 7, 9 and 12 of a pair o tri-state quad two data selectors/multiplexers 66 and 68 of the Signetics type 74258 vari~ty or their e~uivalent. These are identified as group control switch GS in Figures 1~ and 4.
They transmit group data signals along lines ~D0-GD7 from the ;~ group data storage means GR~M (Fig. 6) and group processor in~
struction signals from the group program storage mean~ GROM
(Fig. 6) to the bidirectional data bus pins 3, 6r 10 and 13 of : ~ `
units 54 and 56~ In addition as indicated by the bracket ap-30 pended to line segments GD0~ GDl GD7 shown at the top o~
Figure 4, these lines are connected to circuitry to be de-- scribed and to the input pins of a plurality of inverters shown in Figure 6 which have their output pins connected to the data storage means GRAM of that Figure.
Quadruple bistable latch units 58 and 62 o~ ~roup - ~4 ~

register GR receive the 8~bit address signal applied to their D input pins 2~ 3, 6 and 7 and operate to apply the comple-ments of those signals along lines GA~, GAl ... ~A7 to the circuitry shown in Figure 6 in response to ~ binary one level pulsed signal applied along line GTl to their clock input pins 4 and 13. In addition quadruple bistable latch units 60 and 64 of group register GR receive the 8-bit code signal applied to their D input pins 2, 3, 6 and 7 and operate to apply cor-responding and complementary signals along lines GA8, GA9 ...
GA15, GA8, GA9 .... GA15 to the group logic circuitry of Fig-- ures 5, 6, 7, 8, 9A and 9B in re~ponse to a binary one level pulsed signal applied -to their clock input pins 4 and 13 along line GT2.
Lines GSS, GSR, GCS and GDlE~ connecte~ to control pins 1 and 15 of data seleckors 66 and 68 and of ~us drivers 54 and 56 connect those pins to apparatus of ~igure 5 to be described later.
Group processor GPU applies a 3-~it binary coded timing state identification signal alon~ lines GS~, Gsl and GS2 from its output pins 13, 12, and 11 respectively to ~he select input pins 1, 2 and 3 of a decoder/demultiplexer unit 70 (Fig. 5) of the Signetics type 74S138 variety or its equiv-alent. Decoder 70 used as a 3-to-8 line decoder applie~ sig~
nals along lines GT2, GTl, GTlI and GT3 from its output pins 14, 13, 12 and 11 re~pectively to the group logic circuitry shown in Figures 4, 5 and 9~. ~
Lines GA14 and GA15 connect the select input pins 2 and 3 of 2-to-4 line decoder unit 74 ~Fig. 5) to the Q output pins 11 and 8 o bistable latch unit 54 (Fig. 4~l ~ecoder 74 is of t~e Signetics type 74S139 vari~ty o~ it~ equivalent. De~
coder unit 74 has two additional select input pins 14 and 13 shown connected by lines GA10 and GAll to the Q output pins 11 and 8 respective~y of bistable latch 60 ~Fig~ 4). Enable input pins 1 and 15 of unit 74 are connected by line ~Ll to ground and by line GA13 to output pin 14 of bistable latch 64 v~

(Fig. 4) respectively.
Decoder unit 74 applies a group storage selection signal from output pin 10 along line GSS to the select input pins 1 of the pair of data selector units 66 and 68 (Fig. 4~.
Two additional oukput pins 11 and 12 are ~hown connected to the input pins 13 and 12 respectively of 2-input And gate 80D
which has its output pin 11 connected by line GRSE to two strobe input pins 18 and 19 of a 4-to-16 line decoder/demul-tiplexer unit 90 (Fig. 6) of the Signetics ~ype 74154 variety or its e~uivalent.
Output pin 11 of And gate 80~ is also connected to input pin 2 of ~and gate 84A which has its second input pin 1 connected to output pin 10 of decoder unit 74~ Output pin 3 of ~and ga~e 84A is connected to input pin 5 o~ 2-input Nand ; 15 gate 84B which has its second input pin 4 connected by lineGRX to output pin 3 of ~nd yate 80~ shown in the upper right hand corner of Figure 5. ~and gate 84B applies a read group storage signal along line GSR to the control output pins lS of ` the pair of data selectors 66 and 68 tFig. 4).
One-~alf of dual J-K master slave -Elip-flop 78B of the Signetics type 7476 variety or its aquivalent ha~ its -~ preset input pin 7 connected to the output pin 8 of two input ~and gate 84C which has its input pins 9 and 10 connected to output pins 2 and 8 respectively of a pair of inverters 8~A
and 86D. Lines GPCW and GT3 connect k~e input pins 1 and ~ of ; the two inverters 86A and 86D ko the respective output pin 7 ~` ~ o~ 2-to-our line decoder unit 74 and outpuk pin 11 o~ 3-tQ-~
line decoder unit 70. As shown J-K flip-flop 78B has it~
clear input pin 8 connected to the output pin 4 of inver~er 82B which has its input pin 3 connected by line G01 to the output of oscillator 50 (FigO 4)0 The ~ input pin ~ and the clock input pin 6 of J~K flip-flop 78B are maintained at bin-ary level zero represented by the line HLl and the K input pin 12 is maintained at a ~inary one level represented ~ line L10. J-K flip-flop unit 78B applies a write signal from its .

,, i.3~;

Q output pin 11 along line GW~ to input pins 3 of the selec-tion devices 46 and 48 (Figs. 3A and 3B) and to inverter 82A
(Fig. 6) connected to pins 20 of a pair of read only memory units 96 and 98 (Fig. 6)-to be hereinater described~
A pair of D type flip-flops units 76A and 76B of the Signetics type 7474 dual D-type edge triggered flip-flops or their equiva~ents is shown in the upper right hand portion of Figure 5. As shown, lines GTlI and GT2 respectivel~ connect preset input pin 10 and clock input 11 of flip~flop 76B to output pin~ 12 and 14 of 3-to-8 line decoder unit 70~ Line ~10 connects clear input pin 13 to a binary one level signal and line ~Ll connects the data input pin 12 to a binary zero level signal. As s~own, line GCS connects the Q outpu~ pin 9 of flip-flop 76B ko the select pins 1 o~ the bidirectional bus driver units 54 and 56 (Fig~ 4).
Flip-flop 76A has its clear input pin 1 and its c~ock input pin 3 connected by lines GT3 and GT2 to ~he output pins 11 and 14 respectively of 3-to~8 line decoder unit 70.
The D input pin 2 and the preset input pin 4 are connected to a binary one level signal by means of line ~10. As shown, ~he ~ Q output pin 5 of flip~flop 76A is connected to input pin ~ of ;~ 2-input And gate 80C. And gate 80C also receives a pul~ed ; signal applied to its input pin 10 along line GS~C~
Output pin 8 o And gate 80C is connected ta input pin 4 of 2-input And gate 80B, to input pin 2 of And gate 80A
and to input pin 11 of inverter 86Eo Two input ~nd ~ate 80 also receives a ~ignal applied to its input pin 5 along line--~
GPCW rom output pin 7 of 2-to-4 line decoder unit 74 and ap-plies a signal from its output pin 6 along line GDIEN ~o the data in dir~ction enable control pins 15 of bidirectional bus driver units 54 and 56 ~Fig. 4)O As shown, And gake 80A also receives a second signal applied to its .input pin 1 along-line GA14 from output pin 10 of bistable latch unit 64 (Fig. 4 and is connected to apply a signal a~ong line GRX to input pin 4 of And gate 84Bu ~ 17 -~3 ~

Three to eight line decoder 72 of the Signetics type 74S138 shown in Figure 5 has two of its ena~le input pins 4 and 5 connected to output pin 9 of 2-to-4 line decoder unit 74 and its third enable input pin connected to a binary one level signal represented by the line L10~ Lines GA4, GA5 and GA6 connect the output pins 8, 11 and 14 of bistable latch 62 (Fîg. 4) to the input pins 1, 2 and 3 respectively of 3-to-8 line decoder to cause it to apply a binary zero level signal along one of the lines GEX0, GEXl ~.. GEX7 connected to its output pins 15, 14, 13, 12, 11, 10, 9 and 7.
That portion of the program storage means associat~d with group processor GPU (Fig. 4) and identified in Figure lB
as the group program storage means GROM is shown in F:igure 6 :: as a pair of read only memory units 92 and 94. It is to be .` 15 understood that t~e num~er of such units varies with k~e com-plexity of the stored program and although not shown ~he con-structed embodiment of t~e invention utilizes twelve 2Q48 ~it Electrically Programmable Read Only Memory Units of the Intel ~- Silicon Gate MOS type 1702A. Each one of the twelve units has its address input pins 3, 2, 1, 20, 21, 19, 18 and 17 connec-ted in parallel to output pins 1, 14, 11 and 8 of bista~le latch unit 58 (Fig. 4) and output pins 1, 14, 11 and 8 of bistable latch unit 62 (Fig. 4) by means of lines GA~, GAl, GA2, GA3, GA4, GA5, GA6, and GA7 respectively in t~e manner in ~:~ 25 which the two ROM units 92 and 94 shown in Figure 6 are con-nected to units 58 and 62 (Fig. 4).
Each one of the twelve units also has its data out-put pins 4, 5, 6, 7, 8, 9, 10 and 11 connected in parallel to lines GIO0, GIOl, GIO2, GIO3, GIO4, GIO5, GIO6 and GIO7 w~ich are connected to the input pins 3, 6, 10 and 13 of the pair of data selector units 66 and 68 (Fig. 4)~ Additionally each o~
the twelve ROM units has i~ selection pin 14 individually : connected to a different one of the output pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 and 13 of a 4-to-16 line decoder demulti-plexer unit 90 of the Si.gnetics Type 74154.

;3~

The 4-to-16 line decoder/demultiplexer 90 decode3 the four binary coded signals applied to its input pins 23~
22~ 21 and 20 along lines GA8, GA9, GA10 and GA12 from output pins 1,14 and 11 Oe bistable latch 60 (Fig~ 4~ and from output pin 1 o~ bistable latch 64 (Fig. 4) and applies a binary zero level signal to one of its twelve mutually exclusive output pins 1 - 11 and 13 when a binary zero signal is applied along line GRSE to its strobe input pins 18 and 19 from output pin 11 of And gate 80D (Fig. 5).
~ Shown in the upper portion of Figure 6 is that por-tion of the ~roup logic circuitry referred to hereinafter as group data storage means GRAM comprising a pair of 1024 Bit Static MOS RAM~ with separate I/O of the Intel type 8101 Each one of the pair of RAMS identified as units g6 and 98 in Figure 6 has its address input pins 4, 3. 2t ~ 21, 5, 6 and 7 connected in parallel to group address portion o~ the group register GR tFig. 4) by means of lines GA0, GAl, GA2, GA3, GA4, GA5, GA6 and GA7 respectively. The random access memory - unit 96 has its data input pins 9, 11, 13 and 15 connected to ;: 20 the output pins 2, 4, 6 and 8 of inverters 98A, 98B, 98C and 98D respectively. Lines GD0, GDl, GD2, and GD3 connect the input 1, 3, 5 and 9 of inverters 98~, 98B~ 98C an~ s~n to the output pins 3, 6, 10, and 13 of the bidirectional bus driver ~ 54 shown in Figure 4. Similarly random accsss memory unit 9 - - 25 has its input pins 9, 11, 13 and 15 connected to th~ output ~ ~ pin 2, 4t 6, 8 of inverters lOOA, 100B, 100C, an~ lOOD re-_ :~ ~ spectively. Lines GD4, GD5, GD6 and GD7 connect the input pins 1, 3, 5 and 9 of the inverters lOOA, 100B, 100C and lOOD
to the output pins 3 9 6, 10 and 13 of the bidirectional bus driver 56 shown in Figuxe 40 . The raad-write ena~le input pins 20 of ~he pair of random access memory units 96 and 98 are connected to the out-put pin 2 of inverter 82A. ~ine GWX connects the input pin 1 o invertex 82A to the output pin 11 of ~K flip-flop 78B
shown in Fig~ 5. The output disable pins 18 and enable pins ,9_ .

"" , .,, .. , , . . . . .. . . . .. . . . , . . _ . ... ... ,~. , .

~3;~

19 of each of the units 96 and 98 are both connected to output pin 10 of 2-to-4 line decoder unit 70 (Fi~. 5) by means of line GSS~ The chip enable pins 17 of units 96 and 98 are con-nected to a binary one level signal as .indicated by line L10 In the upper left hand cornex of Figure 7 is shown a pair of quadruple 2-input data selector/multiplexer units 100 and 102 o~ the Signetics type 74157. The first pair of quadruple input pins 2, 5, 11 and 14 of data selectors 100 and 102 are connected by lines GA0, GA1 ... GA7 to the output pins 1, 14, 11 and 8 o bistable latch units 58 and 6Z shown in Figure 4. The second pair of quadruple input pins 3 t 6, 10 and 13 of data selectors 100 and 102 are connected b~ line~
_ GD0, GDl ... GD7 to the output pins 3, 6, 10 ana 13 of bidi-rectional bus drivers 54 and 56 shown in Figure 4. Line GCDT
connects the select input pins 1 of data selectors 100 and 102 to the output pin 11 of J-K flip~flop 180B ~Fig. 9A) forming part of a data transfer signal generator to be hereinafter described.
- Output pin 4 of data selector 100 is connected in common to input pins 2, 5, 11 and 14 of each unit of a second pair of quadruple 2-input data selec~or/multiplexer units 116 and 118 (Fig. 7) also of the Signetics type 74157. Output pin 4 of selector unit 100 is also connected to input pin 3 of selector unik 116. Output pins 7~ 9 and 12 of data selector 100 are respectively connected to input pins 6, 10 and 13 of data selector 116~ Output pins 4, 7, 9 and 12 of data selec=
tor 102 are respectively connected to the second set of ~uad~
rupl~ input pins 3, 6, 1O and 13 of data selector 118. Line G8B connects the select input pins 1 of data selectors 116 and 118 to the output pin 6 of inver~er 170C (Fig~ 9B) to be here-inafter described. ~ine GA13 connects t~ strobe input pins 15 vf the four data selector units 100~ 102, 116 and 118 (Fig. 7) to the output pin 15 of bistable latch 64 tFig. 4).
The output pin~ 4 and 7 of data selector 116 (Fig~7) are connected to input pins 6 and 11 respectively of a dua~
, differential line driver 122 of the Texas Instrument type 75113. The output pins 12 and 9 of data selector 118 are connected to input pins 6 and 11 of a second dual differential line dri~er 125 of the type 75113. Although it has not been shown in Figure 7 it is understood that 2 additional differ-ential line drivers of the type 75113 are connected in the same manner to the output pins 9 and 12 of data selector 116 and the output p.ins 7 and 4 of data selector 118.
The upper half of dual differential line driver 122 applies signals from output pins 2 and 3 along lines DT0(a) and DT0(a) which are connected to the input pins 11 and 9 re-spectively of dual diferential line receiver 236(a)~(Fig.lO).
It is to be understood that the circuitry shown in Figure lO
is employed with car "a" only and that circuitry similar to that of Figure lO is provided for each of the cars in the ; system. Thus, output pins ~4 and 13 of dual differential line driver 122 connected to lines DT0(b) and DT0(b) are ~ thereby connected to logic circuitry associated with car "b"
(not shown) but similar to that of Figure lO for car "a". It ; 20 is to be understood that similar connections are to be made from the output pins of additional dual differential line drivers, not shown, for cars "c", "d", "e" and "f" to -those portions of the group logic circuitry associated with those cars which circuitry also is not shown. The dual differential line driver unit 125 has its output pins 2, 3, 1* and 13 con-nected by bidirectional signal transmission lines DT0(g~, DT0(g), DT0(h) and DT0(h) for cars "g" and "h" to circuitry associated with cars g and h (not shown) similar to that of Figure lO for car "a"~
Four additional dual differential line drivers of the type 75113 are also shown in Figure 7 as a solid line rectangular blocks 126, 128, 130 and 132. As shown input pin 6 of the line driver 126 is connected to output pin 7 of data selector lQO. The remaining two output pins 9 and 12 of data selector lOO are respectively connected to input pins 11 and 6 3~

of line driver 1~8. Output pins 4 and 7 of data selector 102 are connected to the input pins 11 and 6 of line driver 130.
Output pins 9 and 12 o data selector 102 are connected to in-put pins 11 and 6 o line driver 132. ~he dual diferential line drivers 126, 128~ 130 and 132, apply signals along the line~ DTl, DTl ... DT7 and DT7 to the input pins of dual dif-fe.rential line receivers 236(a~, 238(a), 240(a) and 242(2) ,shown in Figure 10 forming part of the group logic circuitr~
associated.with car ~a~. It is to be understood that,.these .., .
lines DTl, DTl . ~ ~DT7, D'~7 are connected,to'the circuitry:simi-lar to that'in'Figure~lO'which is individually-pxovided for'each of the additiona~ cars'of the elevator installation.
Bidirectional signal transmission lines DT0, DT0 for each of the cars and lines DTl, DTl, DT2 ... DT7, DT7 common to all of the cars are also connected to the input pins of a plurality o dual differential line recaivers 160, 161, 162 and 163, 150, 152, 154 and 156 of the Advanced Micro Devices, type AM2615,shown in Figure 8. Lines DTl and DTl are connect~
ed to input pins 11 and 9 of dual differential line receiver 150. The signal on output pin 15 o differential line xe-ceiver 150 is applied to input pin 6 of tri-state quadrupled

2-data selector/multiplexer 156 o the Signe~ics type 74257c Similarly t~e signals on line~ DT2, DT2, DT3 and DT3 are ap~
plied to the dual differential line xeceiver 152 whi.ch applies signals to t~e input pins 10 and 13 of data selector 1S6. T~e remaining eight additional signal lines DT4, DT4, DTS, DT5, DT6, DT6, DT7 and DT7 are connected to ~he input pin~ of the dual differential line receiver units 154 and 156 which have their output pins con~ected to the input pins 3, 6, 10 and 13 ~' 30 of a second tri-state quadrupled 2-data selector/multiplexer 158 as shown in Figure 8~
Four additional dual diferential line receivers 160-163 of the AMD type AM2615 are also shown in the upper left hand corner o Figure 8. The input pin~ , 5 and 7 of each dual differential line receiver 160 ~ 163 are , . .

connected to the bidirectional signal transmission lines DT0 and DT0 of two cars.
The differential line receivers 160 - 163 apply the complements of the signals applied to their input pins to a pair o~ data selectors 156 and 158 shown in Figure 8. As shown output pins 15 and 1 of dual differential line receiver 160 are connected to the input pins ~ and 5 of data selector 156. Output pins 15 and 1 of dual differential line receiver 161 are connected to input pins 11 and 14 respectively of data selector 156. Output pins 15 and 1 of dual differential line receiver 162 are connected to the input pins 2 an~ 5 of the second data selector 158. .Additionally dual differential line receiver 163 has its output pins 15 and 1 connected to the input pins 11 and 14 of data selector 158, respectively.
The output signals from the dual diferential line receivers 160 - 163 are also applied to t~e input pins of a 8-line to 1-line data selector/multiplexer 164 (Fig. 8) of the Signetics type 74151. ~s shown common output pins lS and of each line receiver are connected to different input pins of selector 164. butput~pin 5,of t~le~ selector 164 is connec-ted 'to the.input pin.3..of.data selector unit.l56..~-~ines,G,B~0, GA9 and GA8 apply a three bit binary coded selection signal from the output pins 11, 14 and 1 respective~y o~ bistable latch 60 shown in Figure 4 to the select ;nput pins 9, 10 and 11 of decoder 164. The strobe input pin 7 of decoder 164 is . .
~, connected by line GA13 to the output pin 15 of bista~le latch 64 shown in Figure 4.
The first or second car control signals to be re-: ceived by the group processor GPU (Fig. 4) are applied along lines GD0, GDl ..~ GD7 from the pair of tri-state quadruple 2-data selector units 156 and 158, Figure 8, to the bidirec-tional bus drivers 54 and 56 shown in Figure 4. Lines.GRCE
: and G8B respectively connect the output control pins 15 and data select inpuk pins 1 of data selector units 156 and 158 to the output pin 8 of ~and gate 174C (Fig, 9A) and the output - 23 _ ,r~ 3~

pin ~ of data se~ ctor unit 200 (Fig. 9B~ to be hereinafter described.
Shown in Figure 9A is a simplified schematic diagram of that portion of the group logic circuitry referred to here-inafter a~ the group suspension s.i~nal generator. Line GD5connects ~.he output pin 6 of bidirectional bus driver unit 56 (Fig~ 4) to the input pin 1 of hex inverter 170A and to the K
input pin 16 of J-K flip-flop 172A -Eorming one section of a dual ~-K master-slave flip-flop of khe Signetics type 7476~
The preset input pin 2 of J-K flip-~lop 172A is connected to a binary one level signal represented by means of line L1~.
Clock input pin 1 of J-K flip-flop 172A is connected to output pin 4 of inverter 170B which has its input pin 3 connected to output pin 6 of a three input positive Nand gate 174Bo ~and gate 174B has its input pîn 3 connected b~ line G01 to the 800K EZ oscillator 50 (Fig. 4)r A second input 4 of ~and gate 174B i9 connected to output pin 12 of a hex in-verter 176F w~ich has its input pin 13 connected to the output pin 14 of group processor GPU (FigO 4) by means of line GSYNC.
The third input pin 5 of ~and gate 174B is connected to output pin 3 of a pair of two input ~and gate 178A ~nd arranged wit~
~and gate 178C as a set reset flip-flop~
Output pin 3 of ~and gate 178A is also conn~cted to input pin 9 of ~and gate 178C which has its second input pin 10 connected by means of line GT2 to output pin 14 of three to eight line decoder unit 70 (Fig. 5)O Output pin 8 o~ ~and ~- gate 178C i5 connected to input pin 2 o~ Nand gate 178A w~ich - has its second input pin connected ~y means of line GTl to output pin 13 of the 3-to-8 line decod~r unit 70.
Input pin 3 of the J-K 1ip flop 172A (Fig. 9A) and input pin 2 of J-K ~lip-flop 180A (Signetics typ~ 7476) are connected to output pin 12 of a three input Nand ~ate 174~
Line GSYNC connects input pin 1 of Nand gate 174A and clock input pin 1 of J-K flip-flop 180A to the output pin 14 of group processor GPU (FigO 4). The remainin~ two input pins 2 _ 24 -,;, .

~ zr~

and 13 of Nand gate 174A are connected to the Q output pins 15 and 11 respectively of the two sections 180A and 180B of a dual ~-K master slave flip flop of the Signetics type 7476 arranged as a toggle flip-flop. As shown the Q output pin 15 of J-K flip-flo~ 180~ i s also connected to the clock input pin 6 oE J-K flip-flop 180B. In addition the Q output pin 11 of J-K flip-flop 180B is connected to input pin 11 of Nand gate 174C and by means of line GCDT to the select input pins 1 of the pair of data selectors 100 and 102 in Figure 7 and to the select input pin 1 of data selector 200 shown in Figure 9B .
Clear input pins 3 and 8 of the two J-K *lip-flops 180A and laOB are connected to output pin 11 of two input ~and gate 178D. As sho~wn ~and gate 178D has one of it~ input pins 12 connected to Q output pin 14 of J-K flip-flop 172A and its second input pin 13 connected by line GA13 to output pin 15 of bistable latch 64 (Fig. 4). Line GSUS connects the Q output : pin 14 to input pin 17 of group processor GPU (Fig. 4). The J-K input pins 4 and 16 of J-K flip-flop 180A, the J-X and preset input pins 9, 12 and 7 of J-K flip-flop 180A and preset input pin 2 of J-K flip-flop 172A are maintained at a binary one level represented by line L10.
: ~and gate 174C has its input pins 11 connected to Q output pin 11 of J-K 1ip-fIop 180B . ~ine GA13 connects its input pin 10 to output pin 14 of bistable latch 64 ~Fig. 4).
Line GRX connects its input pin 9 to output pin 3 of And gate 80A (Fig. 5).
The upper hal of Figure 9B shows a simplified schematic diagram representation of that portion of the group logic circuitry hereinafter referred to as car suspension sig-nal genérator. Lines GA8, GA9 and GA10 are connected from output pins 1, 14 and 11 respectively of bistable latch unit 60 (~ig. 4) to input pins 1, 2 and 3 respectively of high spPed one of eight binary decoder 190 of the Intel type 3205.
. 35 Decoder 190 has three enable input pins~ two of which, pins 4 -and 5, are connected by means of line G~13 to output pin 15 of bistable latch 64 (Fiy. 4). 1~e third enable .input pin 6 is connected to a binary one level signal xepresented by means of line L10.
Output pins 15, 14, 13 and 12 of unit 190 are con-nected to the input pin 3, 6, 10 and 13 of a quadruple 2-input data selector/multiplexer 192 of the Sigrletics type 74158.
The remaining four output pins 11, 10, 9 and 7 of decoder 190 are connected to input pins 3, 6, 10 and 13 of a second data selector 194 of the Signetics type 74158. Both data selector units 192 and 194 have their second set of input pins 2, 5, 11 and 14 connected to ground potential represented by the line HLl. Both units 192 and 194 ~ave ~heir strobe input pins ; 15 connected by means of line GA13 to output pin 15 of bistable latch 64 (Fig. 4) and their data select input pins 1 connected by means of line GA11 to output pin 8 of bistable latch 60 ~Fig~ 4). Output pins 4 and 7 of data selector 192 are con-nected to common input pins 9, 10 and 7, 6 respectively of dual differential line driver 196A and 196B of the Fairchild type 9614. Similarly output pins 9 and 12 of data selector 194 are connected to common input pins 9, 10 and 7, 6 of a second dual differential line driver 198A and 198B of the Fairchild type 9614.
Output pins 9 and 12 of data selector 192 and pins 7 and 9 of data selector 194 are similarly connected to an-oth~x two dual differantial line drivers (not shown) in the same manner described a~ove. Output pins 13 and 1~ of dif-ferential line driver unit 196A are individually connected to dual differential line receiver 210(a) (Fig.10) associated with car "a" of the elevator system by lines XCRDY(a) and XCRDY(a).
It is to be understood that the remaining output pins of each .. of the dual differential line drivers are similar~y separatel~
connected to circuitry simil.ar to that shown in Figure 10 in-dividual to each of the additional cars of t~e elevator in-stallation.

.

31 d ~

Shown in the lower half of Figure 9B is the remain-ing portion of the group logic circuitry illustrated b~ the rectangular block G/C in Figure lA. Line GS~NC connects out-put pin 14 of group processor GPU (Fig. ~) to input pin 2 of 5 data selector 200 of the Signetics type 74157. Two additional input pins 11 and 14 o data selectox 200 are maintained- at a binary one level as indicated b~ the line L10. Input pin 5 and input pin 10 of data selector 200 are shown connected to the output pin 6 of two input ~and gate 202~. Nand gate 202B
10 has its first input pin 4 connected to output pin 7 of decoder 190 (FigO 9B) and its second input pin 5 connected by line GAll to output pin 9 of bistable latch 60 (Fig~ 4). Bistable latch 62 is connected by lines GA14 and GA14 to input pins 13 - and 6 respectively o data selector 200, -Line GWX connects 15 the last input pin 3 of data selector 200 to the Q output pin 11 of J-K flip-flop 78B shown in Figure 5~ ;
Output pins 4 and 7 of data selector 200 are respec-: tively connected to input pins 9,and 7 of a pair of differen-tial line drivers 204A and 204B of the Fairchild type 96140 20 Lines GTP, GTP and GDC, GDC connect the output pins o the pair of line drivars to the input pins o dual differential . line receiver 216(a) (Pig. 10) of the AMD type ~M2615~
.~ Output pin 9 of data selector 200 is connected to input pin 5 of inverter 170C w~ich has its output pin 6 con-25 nected to the select i~pu~ pins 1 of data selectors 116 and ~:: 118 shown in Figure 7. In addition line G8B connects~ output pin 9 of data selector 200 (Fig~ 9B) to the select .input pins 1 of data selectors 156 and 158 shown in Figure 8. Data se-lector 200 also has its output pin 12 connected by.line 30 GCTE to input pins 7 and 10 o dual differential line drivers . ~ 122 through 130 shown in Figure 7.
: . F~igure 10 is a simplified schematic ~epr~senta~io~
of the circuitry of ~e group processing means associated with car "a" and illustrated in Figure lA b~ the rectangular. block 35 C/G(a)O It is to be understood that although this ~ircuitry , , . . .
' - 27 -,, ,, i5 considered part of the group logic circuitry it is indi-~idually associated with car "a" and that similar circui.try to that shown in Figure 10 is provided for each of the addi-tional cars of the elevator system.
As mentioned earlier signal lines XCRDY(a) and XCRDY(a) connect output pins 14 and 13 o~ dual differential line driver 196A (Fig. 9B) to the input pins 9 and 11 respec-tivel~ of dual differential l:ine receiver 210(a) (Fig. 10) of the .AMD type AM2615. Dual differential line receiver 210(a) is connected by line CSUS(a) to input pin 17 of car pro-ce~sor unit CPU(a) shown in Figure 11 and to input pin 9 of in-verter 212D(a)(Fig.10). Inverter 212D(a) has its output pin 8 connected to the clear input pins 3 and 8 of a pair of J-K
flip-flops 214A(a) and 214B(a) of the Signetics type 7476 ar-ranged as a toggle flip-flop. Both flip-flops 214A(a) and : 214B(a) have their preset input pins 2 and 7, their J input ; pins 4 and 9 and their K input pins 16 and 12 connected to a binary one level signal represented by line L10. Clock input pin 1 of J-K flip-flop 214A(a) is connected to output pin 2 of dual differential line receiver 216~a) of the AMD type AM2615.
Q output pin 15 of J-K flip~flop 214A(a) is connected to clock input pin 6 of J-K flip-flop 214B(a) and .input pin 1 o a 3-input ~and gate 218A(a). ~and gate 218A(a) has its sec-ond input pin 2 connected to output pin 2 of dual differential line receiver 216(a) and its third input pin 13 connected to the Q output pin 10 of J-K flip-flop 214B(a). Output pin 12 of Nand gate 2l8A(a) is connected to input pin 3 of inverter 212A(a) which has its output pin 4 connected to clock input : 30 pin 13 of a quadruple bistable latch 222(a) and clock input pins 4 and 13 of a pair of quadruple bistable latches 224(a) and 226(a) all three latches being of the Signetics type 7475.
: As shown in the lower right hand corner of Figure 10 output 11 of J-K flip-flop 214B(a) is connected to input pin 10 of a two input And gate 220C(a) which has its second input`pin - - - 28 ~

~ ~$.~

9 connected to output pin 2 of dual differential line receiver 216(a). And gate 220C(a) is connected by line GWD to input pins 5 and 11 of data selector 416(a) shown in Figure 13. Output pin 11 of J-K flip-flop 214B(a) i5 also connected to the input pin 5 of And gate 220B(a) which has its second input pin 4 con-nected to output pin 14 of dual diferential line receiver 216(a). Output pin 6 of And gate 220B(a~ is connected to con-trol pin 10 of dual differential line driver 228(a~ of the Texas Instrument type 75113.
Output pin 14 of dual differentia1 line receiver 216(a) is also connected to input pin 2 of quadruple bistable latch 222(a) which has output pin 16 connected to input pin 1 of And gate 220~(a)~ And gate 220A(a) has its second .input pin 2 connected to output pin 6 of And gate 220B(a) described above, and its output pin 3 connected to control input pins 10 and 7 of a plurality of dual differential line dxivers of the Texas Instrument type 75113 or equivalent shown as rectangular blocks 230(a), 232(a) and 234(a) in the upper left hand corner o$ Figure 10.
Lines CGD0(a)~ CGDl(a) ... CGD7(a) connect input pins 11 and 5 of the four dual differential line drivers 228(a), 230(a)~ 232(a) and 234(a) to t~e output pins of a pair . of quadruple 2 input positive And gates 412(a) and 414(a) (Fig. 13). Output pins 13, 14, 3 and 2 of the dual differen~
tial line receivers are connected to lines DT0(a),:DT0(a), DTl, DTl ... DT7 and DT7 to apply data signals from the cir-cuitry associated with car "a" to the group processor as will be hereinafter described.
Lines DT~(a), DT0(a), and DTl and DTl are conne~ted ~ 30 to the input pi~s 11, 9, 5 and 7 respectively of a dual dif-- ferential line receiver 236(a) of the Fairchild type 9615. Theremaining lines DT2, DT2 ... DT7 are connecte~ in a similar fashion to the input pins of three additional dual differen-tial line receivers shown as rectangular blocks 238(a), 240~a~ -and 242(a) in Figure 10. Lines GCB0(a), GCBl(a) ... GCB7~a) conn~ct the output pins 14 and 2 of the differential line re-ceivers 236(a), 238(a), 240(a), 242(a) to the D input pins 7, 6, 3 and 2 of a pair of bistable latches 224(a) and 226(a) of the Signetics type 7475.
Lines GCA0(a), GC~l(a), GCA2(a), GCA3(a) connect the Q output pins 9, 10, 15 and 16 of bistable latch 224(a) to in-put pins 2, 5, 11 and 14 respectively of a quadruple two input data selector 408 (Fig. 13) of ~he Signetics type 74157. Lines GCA4(a), GCA5ta), GCA6(a) and GCA7(a) similarly connect the output pins 9, 10, 15 and 16 of bistable latch 226(a) to input pins 2, 5, 11 and 14 of a second quadruple 2-input data selec-tor 410(a) (Fig. 13) of t e Signetics type 74157~ -Lines GCB0(a), GCBl(a) .~ GCR7(a) connect the out~
put pins of dual differential line receivers 236(a), 238(a), 240(a) and 242(a) to input pins 2, 5~ 11 and 14 of a pair of quadruple 2-input data selectors ~OO(a) and 402(a~ (Fig. 13) of the Signetics type 74158.
~:~ Line DTS connacts the Q output pin 10 of J-K flip-flop 214B(a) (Fig. 10) to apparatus to be described later in connection with Figure 13.
~- . Figures 11, 12 and 13 com~ined show a simpli~ied schematic representation of that portion of the circuitry o-E -the CaL processing means and the car program skorage means ~ associated with car "a" illustrated by the.rectangular blocks ~ 25 CPU(a), CR(A)y SW(A), CRAM(a) and CROM(a) Figure lB~ The ad-.

ditional circuitry of the car pxocessiny maans and the car control equipment associated with car "a" and shown as rectan-gular blocks OE SC(a) and CCE(A~ respectively in Figure lB will be described hexeinafter with reerence to the simplified sche-matic diagrams of Figures 14y ~5; 16 and 17O Th~ equipment il~
lustrated in block diagram form in Figure lB for car 'ia" is re-quired for each of the additional cars of the.elevator instal-lation. Consequently it is to be understood t~at the followi~g circuit description specifically directed to the circuitry as sociated with car "a" as so referenced ~ the suffix character (a) appended to the reference characters of the circuitry of Figures ll through 17 is also applicable to similar clrcuitry required for the remaining cars of the installation but not shown herein in the interest of brevit~.
A visual comparison of the simplified schematic diagrams of Figures 4 and 5 previously described and of the circuitry shown in Figures 11 and 12 discloses that the sche~
matic representation of the circuit elements and their inter-connections are identical. A further comparison indicatqs that the distinguis~ing chararteristic between the two figures res-ts only in that the prefix "G" is affixed to the reference char-acters shown in Figures 4 and 5 while the prefix "C" is affix~
ed to the same characters shown in Figures ll and 12. It is of course understood that the additional appended bracket nu-merals indicative of the interconnections of signals lines he~
tween various figures are also different. However the intercon-nections between the various pieces of equipment shown on Fig-ures ll and 12 are identical to the interconnections be~ween the corresponding pieces of equipment on Figures 4 and 5.
That portion of the program storage means associated with car processor CPU(a) (Fig. ll) and identified in Figure lB as the car program storage means CROM(a) is shown in Figure 13 as a pair o~ read only memory units 392(a) and 394ta) is connected to apparatus in Figure ll in the same mann~r as the corresponding group program storage means of Figure 6 is con-- nected to the corresponding apparatus of Figure 5. It is un-derstood that the numb~r of read only memory units varies with the complexity of the stored program and although not shown the disclosed embodiment of the invention utilizes tw~lve 2048

3~ Bit Electrically Programmable Read only Memory Units of the Intel Silicon Gate MOS type 1702A.
- Shown in the upper portion of Figure 13 is ~hat por-tion of the car logic circuitry hereinafter referred to as the - car data storage means and the car data switching means. Lines CD0(a), CDl(a), CD2(a) and CD3(a) connect the first set of input pins 3, 6, 10 and 13 of data selector unit 400(a~ to the output pins 3, 6, 10 and 13 of bidirectional bus driver 354(a) (Fig. 11) and lines CD4(a), CD5(a), CD6(a) and CD7(a) connect the irst set of input pins 3, 6, 10 and 13 of a second data selector unit 402(a) (E~ig. 13) to the output pin 3, 6, 10 and 13 of bidirectional bus driver 356(a) (Fig. 11). In addition lines GCB0(a), GCBl(a) ... GCB7(a) connect the second set of input pins 2, 5, 11 and 14 of the two data selector ùnits 400(a) and 402(a) to the output pins 1 and 15 of the four dual differential line receivers 236(a), 238(a), 240(a) and 242(a) shown .in Figure 10. The data selector units 400(a) and 402(a) ; have their output pins 4, 7, 9 and 12 connected to t~ data input pins 9, 11, 13 and 15 of a pair of 1024 bit (256 x 4~
Static MOS RAM units 404(a) and 406(a) of the Intel type 8101.
Lines CA0(a), CAl(a) ~... CA7(a) are connected to the first set of input pins 3, 6, 10 and 13 of a second set of data selector units 408(a) and 410(a) of the Signetics type 74157. The connections by l.ines GCA~(a), GCAl(a) ..~ GCA7(a) to units 408(a) and 410(a) have been describèd previously with respect to Figure 10. These units have their output pins 4, 7, 9 and 12 connected to address input pins 4, 3, 20 1, 21, 5, 6 and 7 of RAM units 404(a) and 406~a).
: . .
The two sets of qua~ruple.data output:pins 10,~12, ` 14 and 16 of the data storage units 404(a~ and 406(a) are con-nected by lines CDO0(a), CDOl(a) .OO CDQ7(a) to input pins 2, 5, 11 and 14 o~ a pair of data selector units 366(a) and 368(a) (Fig. 11) to transmit first and second car control signal~ or group control signals from the car data storage means to the car processor unit CPU(a) ~Fig. 11). In addition output pins 10, 12, 14 and 16 of data storage units 404(a~ and 406(a) are -connected to the input pins 1, 4, 9 and 12 o~ a pair o quad-ruple 2~inpuk positive And gates 412(a) and 414(a) of the Sig~
netics type 7408~ Output pins 3, 6, 8 and 11 of And gates 412(a~ and 414(a~ are connected by lines CGD0(a), CGDl~a) CGD7(a) to apparatus described in connection with Figure 10.
..
~ 32 -Strobe input pins 15 of the pair of data selectors 408(a) and 410(a)(Fig. 13~ hereinafter referred to as the car addre3s switching means and the chip enable input pins 19 of a pair of 1024 bit (256 ~ 4) static MOS RAMS 404(a) and 406(a) (Fig. 13) with separate I/O of Intel type 8101 are connected to the output pin 4 oE quadruple 2-input data selector/mul-tiplexer 416(a) (Fig. 13) of Signetics type 74157. The read write pins 20 of the pair of RA~ units 404(a) and 406(a) and the strobe input pins 15 of the pair of data selectors 400(a) and 402(a) o the Signetics type 74157 hereinafter referred to as the car data input switching means are connected to the out-put pin 4 of inverter 418B(a) of the Signetics type 7404 or equivalent which has its input pin 3 connected to the output pin 7 of data selector 416(a). The output disable pins 18 of both ~AM units 404(a) and 406(a) are shown connected to the third output pin 9 oE data selector 416~a). Line ~10 connects the chip enable pins 17 of the data storage units 404(a) and 406(a) to a binary one level signal.
As shown line DTS(a) connects the Q ~utput pin 10 oE
J-K flip-flop 214B(a) (Fig. 10) to the select input pins 1 of the two data selector units 400(a) and 402(a), the two address : selector units 408(a) and 410(a) and a control signal selector unit 416(a) of the Signetics type 74157. The line DTS(a) ib :;. also connected to the input pin 1 of in~erter 418A(a) which has : 25 its output pin 2 connected to the four input pins 2, 5, 10 and 13 of quadruple And gate units 412(a) and 414(a~.
The control signal selector 416(a) has its stxobe input pin 15 and its input 2 maintained at a binary zero level by line HLl. Line GWD(a) connects input pins 5 ana 11 of con-trol signal selector 416(a) to the output pin 8 of And gate 220C(a) (Fig. 103. Input pins 3 and 10 of con-trol signal se-. lector 416(a) are connected by line CSS(a) to ~he output pin 10 of data selector 374(a) (Fig. 12). Line CWX(a3 connects the Q output pin 11 of ~-K :Elip-flop 378Bta) (Fig. 12) to the : ~ 35 input pin 6 of the control signal selector unit 416(a).
, Figures 14 and 16 comprise a schematic representa-tion of the car control equipment signal selection circuitr~
associated with car "a" and illustrated in Figure lB b~ -the rectangular block CES(a). The car control equipment ,selection circuitry connects the car operating apparatus CCE(a) to be hereinafter described to the ~ar processor CPU~a) and operates in response to its associated car processor to selectively transmit binary signals indicative of the car operating appa-ratus to the car processor. In addition the car control .
equipment selection circuitry operates in response to its associated processor to transmit first car control signals to its associated car operating apparatus to cause it to control the operation of car "a" in an independent manner and second car control signals to the associated operating apparatus to cause it to control the operation o~ car "a" as a member of a supervised group.
Line CD0(a) connects output pins 5 of three data se-lector/multiplexer units 430(a), 432~a) (Fig. 14) and 434(a) ~- (Fig. 16) of the Signetics type 74S251 to pin 3 of bidirec-tional bus driver 354 (Fig. 11). The car call selection units 430(a) and 432(a) and the car status signal selection unit 434(a) operate in response to the application o~ a binary zero ; level signal to their respective stro~e input pins 7 and a 3-bit binary signal applied along lines CA0(a)~ CAl(a) and CA2~a) from the output pin~ 1, 14 and 11 of bistable ~atc~ 358~a) (Fig. 11) to their data select pins 11, lO and 9 respecti~ely to cause the selected unik to apply one of eight signals ap-plied to its input pins 4, 3, 2, 1, 15, 14, 13 and 12 alon~
line CD0(a). The selection apparatus which applies the binary zero level signal to the strobe input pin 7 o-E the selected unit will be described hereinafter.
In addition three-to-eight bit addressable latch units 438(a), 440(a) (Fig. 14) and 444(a) (Fig. 16) o-E the Fairchild type 9334 or equivalent have their data input pins 13 also connected to lines CD0(a) and their address input pins .

d ~

l, 2 and 3 connec-ted to lines CA0(a), CAl(a) and CA2(a), In response to the thre~ bit binary code applied to their address input pins and a binary æero level signal applied to the strobe input pin 14 of a selected one of the three units 438(a~
5 440(a) and 444(a), that unit appli.es a binary zexo signal from one of its output pins 4, S., 6, 7, 9, 10, 11 and 12 which corresponds to the signal on line CD0(aj. The apparatus which applies the binary zero level signal to the strobe input pin 14 of a selected unit will be described hereinafter.
As shown the ~trobe input pins 7 o the pai.r of car call selection units 430(a) and 432(a) are respectively con-nected to the output pinæ 6 and 7 of dual 2-to-4 line decoder or chip selection device 446(a) (~ig~ 14) of the Signetics type 74155. Two additional output pins ll and 12 o chip se-lection device 446(a) are respectively connected to the strobe input pins 14 of the call reset selection units 440(a) and 438(a). Line CEX0(a) connects t~e strobe input pins 2 and 14 of chip selection device 446(a) to the output pin 15 of 3-to 8 line decoder 372(a) shown in Figure 12~ A read or write sig-nal is applied along lines CR~(a) or CWX(a) xom the output pin 3 of And gate 380A~a) (Fig. 12) or the Q output pin of ~-K
flip-flop 378B(a) (Fig. 12~ to t~e input pins l or 3 of the chip selection device 446(a). Two additional signal lines CA3(a) and HLl connect input pins 13 and 15 of the.chip selec-: 25 tion device 446(a~ respectively to the output pin 8 o~ bistable latch 358(a) (Fig. 11) and to a binary zero leve~ signal re-presented by line HLl.
The strobe input pin 7 of cax statu~ signal selec~
tion circuit 434(a) (Fig. 16) is shown connected to output pin 8 of a three input Nand gate 442C(a). Lines CA3(a), and CRX(a) : respectively connect the ~ t pl~S 9 and ll o ~and gate . -442C(a) to the output pin 9 of bistable latch 358(a)- ~Fig. }.1~, and pin 3 of And gate 380A~a) (FigO 12). Line CEX3~a) con~
nects output pin 12 of 3-to-8 line decoder 372~a) (Fig. 12) to input pin l of inverter 448~ta) w~ich has îts ou~put pin 2 ~ 35 -., , i: :

., connected to the third input pin 10 of Nand gate 442C(a).
The strobe input pin 14 of the car output signal selection device 444(a) (Fig. 16) is connected to the output pin 6 of three input Nand gate 442B(a)~ Lines C~3(a) and CWX(a) respectively connect the input pins 3 and 5 of Nand gate 442B(a) to output pin 9 of bistable latch 358 (Fig. 11) and to the Q output pin 11 of J-K flip-flop unit 378B(a) (Fig. 12). Line CEX4(a) connects output pin 11 of 3-to-8 line decoder 372ta) (Fig. 12) to input pin 3 of inverter 448B(a) which has it~ output pin 4 connected to the third input pin 4 of ~and gate 442B(a).
A simpliEied schematic diagram of the car call re-gistration circuits utilizing the well-Xnown cold cathode gas B tube touch button of the RC~ type lC21 or equivalent is shown in Figure 15 or the main landing and landings 2~ 6, 7, 11, 12 ! , and T of the building in which the system i.s installed. It i5 ; understood that add1tional car call registration circuits for the remaining landings are connected between ~he broken lines shown in Fig. 12 1n a fashion similar to the circuits shown therein.
The anode of ea~h gas tube lC~a), ~C(a~...TC~a) has a potential of 135 volts referenced to line B0 applied to it along line B+ rom power supply PS1 (Fig. 3) previously de~
scribed and has its cathode connected to an associated cathode resistor RCLl, ~CL2~ C~T which has its second side connectea to line B0 of power supply PSln Line~ Cl(a), C2(a)..~CT(a) connect the cathode of their associated tube to individual solid line rectangular blocks identified by the referance characters 18A representing an optical coupler and level con~
~; 30 verter to be described hereinater. The optical couplers and level converters are also connected to lines BQ and ACl o - po~er supply PSl (F3g. 2) to enable the gas tube touch button to be operated.
The car call registration signals for the circuits shown in Figure 15 ~re applied alon~ lines lCS(a), 2C5(a) r ~ 36 ~

, , ~ . .. . . . . . . . ... . . .. . . .. .. ...

6CS(a), 7CS(a), llCS(a), 12CS(a) and TCS(a) to ~he input pins 12, 13, 2 and 3 of call selection unit ~30(a) ~Fig~ 14) and pins 14, 15 and 4 of call selection unit 432(a) (Fig~ 14). It is to be understood that the corresponding pins of the optical couplers and level converters which are not shown ~ut asso-ciated with the additional car call registration circuits which are not shown are similarly connected to the remaining input pins o the call selection units.
Call reset signals ~or each of the call registration circuits shown are applied from the output pins 12, 11, 6 and 5 of call reset selection unit 438(a) (Fig. 14) and output pi.ns 10, 9 and 4 of call reset selection unit 440~a) (Fig~ 14) alon~
lines lCR(a), 2CR(a), 6CR(a), 7CR(a), llCR(a), 12CR(a~ and TCR(a) to the reset pins R of the optical couplers and level converters 18A (Fig. 15)~
A simpliied schematic representation of the control apparatus associated with car "a" for use wit~ the control system of the present inv~ntion is shown in Figure 17. As shown elevator car lO(a) and counterweight ll(a) are .suspended by hoist ropes 12(a) from sheave 13(a). Car lO(a) serves si~-teen landings ~l-Lt as do all the ~ars in the group (not shown~
Sheave 13(a) is mounted on the shaft of armature MA(a) of a direct current hoisting motor which also houses a typical elevator brake BR(a~. Motor armature M~(a) i~ con-nected acro3s both generator armature GA(a~ and its serie~
field GSEF(a) of the direct current generator of a motor gen-arator set. The motor field MF(a) and the generatox field GF(a) are both connected to receive current from a self ex-cited generator having its armature EA (a) alsa connected to ` 30 the shaft common to the motor generator set (not shown).
Two series connected normally closed door zone con tacts DlZ(a) and D2Z(a) connect the line V2(a) to one side of : - the coil of door open switch DO(a~. Line DO(a) connact~ the ~econd sid~ of the door open switch coil DO(a) to the terminal -02 of relay driver cixcuit shown as rectangular ~lock 18C(a~

~ '7~3~ ~

(Fig. 16) which has its input terminal I3 connected to the output pin 4 o~ relay selection device 44~(a) (Fig. 16~.
The coil of start switch ST(a) is also connected to line V2(a) and to line GO(a) which is similarly connected to the terminal 02 o~ a second relay driver circu;t shown as rec-tangular block 18C(a) (Fig. 16) which has its input terminal I3 connected to the output pin 7 of relay driver selection de-vice 444(a) (Fig. 16). Relay selection device 444(a) (Fig. 16 as shown has two additional pins 5 and 6 respectively con-nected to the input terminals I3 of an additional pair of re~lay drivers shown as rectangular blocks 18C (a) (Fig. 16) which are connected ~y lines AU and AD to one side of the set coil and one side of the reset coil of direction hold switch DG(a) (Fig. 17).
Series connected gate contacts GS(a) and door con-tacts DS(a) operate to their closed position w~enever the car or hoistway gates are closed and apply the voltage on line V2(a) along line DFC to the input terminal of optical I2 of optical coupler and level converter circuit represented by rectangular block 18B(a) (Fig. 16). The converter circuit has its output terminal Oi connected to t~e input pin 14 of signal selection device 434(a) (FigO 16). Another door switch O~(a) which engages its contacts when t~e elevator doors are fully open is shown connecting line V2(a) on line ~FO(a). This latter line is connected to input terminal I2 of optical coupler and level converter 18B(a) (Fig. 16) which has its output terminal 01 connected to the input pin 13 of signal selection device 434(a) (Fig. 16)~
The car operating apparatus associated with car "a"
includes a pair of advanced floor position brushes FPUla) and FPD(a) and an actual floor position brush FPB(a) mounted on the synchronous panel o~ a typical ~loor selector unit ar-ranged to contact the floor position contacts FPCl(a), FPC2~a~
... FPCT(a) connec-ted to matrix assembly shown as rectangular block MT(a) to produce binary signals representing the ad-_ 38 -~ ~fi,~,tj vanced car position and actual car position. As shown the actual ~loor position brush i9 connected by normally closed running switch contacts H2(a) to line V2(a) whenever car "a"
is located at a ~loor to cause the matrix assemhly to apply a binary coded signal representing the actual car position to car position signal lines CPl(a), CP2(a), CP4(a), CP(a~ and CP16(a). These lines are connected to the input terminals I2 o~ five optical coupler and level converter circuits 18B(a) (Fig. 16) having their respective output terminals 01 connec-ked to the inputs lS, 1, 2, 3 and 4 of signal selection device 434(a) (Fig. 16).
~ormally opened runnin~ switch contacts Hl(a~ con~
nect line V2(a) to line V3(a) which is also connected to line RUN(a) which connects it to the input terminal I2 o~ optical coupler and level convexter 18B(a) haviny its output terminal connected to input pin 1~ of car status selection unit 434~a) (Fig. 16).
Floor position ~rushes UlS(a), U2S(a), DlS(a) and D2S(a) of the aforementioned selector are set to engage ~heir associate series connected floor position contacts lSC~a) and 2SC(a) when the car is at predetermined distances rom the~e landings.
The hall call and car call registration c.ircuit~ de-; scribed prevîously are connected to reckangula~ blocks 18A re-;- 25 presenting opkical coupling and level conver~ing drivers which are shown schematically in Figure 18A~ Eac~ of these circuits operates in response to the registratîon of its correspondin~
call to produce a binary zero on its "Sl' output. To reset the : call a binary zero is applied to the "R" input which causes the signal on line ACl to be applied to kerminal Ilo ~he inpuk signal circuit~ shown as rectangular blocks 18B(a) Figure 16 are each illustrated sc~ematicall~ in Figure 18B. In re~ponse to an inpuk si~na~ applied to its terminal I2 each o~ these optical couplers and level convert-ers apply a hinary zero signal to its terminal 01.
- . _ 39 ~

The four relay driver circuits shown in Fig. 16 as rectangular blocks 18C(a) are each schematically illustrated by the circuit shown in Fig. 18C. In response to a binary zero signal applied to its input terminal I3 each of these re-lay drivers applies a suficient enough ground to its 0~ ter-minal to cause an appropriate relay to be energized.
In order to understand how the control system of the disclosed invention operates to cause each of the cars of an elevator installation to operate as a member of a supervised group a description will be provided of how the group process-ing means GPM receives first car control signals rom the car processing means CPM and applies group control signals to the car processing means which produces second car control signals in respo~se thexeto and applies those signals to the car oper=
ating apparatus associated with each of the cars of the eleva-- tor installation to cause them to operate as members of a ~u-pervised group. It will be assumed that the car processing : means CPM of the elevator installation includes a separate car processor and associated car logic circuitry both individual to each car of the installation and that each car processor sequentially performs a irst set of operaklons by following in any well~known manner a car program Gf instructions to pro-duce first car control signals in response:to car call signals-and car position signals which are applied to the car operat.ing apparatus of the associated car to cause the associated car to .~ operate in a particular manner. It should be und~rstood that . the car processor and its associated car logic circuitry indi-.- vidual to each car operate in the same manner and consequently the description of the transer o~ the first car con rol sig-nals and group control signals between the car processor CPU(a~ and ;ts associated car logic circuitry individual to a single car, car "a", and the group processing means will be understood to be equally applicable to signal transer between the car processors and their associated car logic circuitry individual to the additional cars of the elevator installation : .. ..
. ~ 40 -'''', .~

and the group processing means.
It will also be assumed that the group processiny means includes a group processor GPU and its associated group logic circuitry and -that the group processor sequentially per-forms a second set of operations by following in any well-known manner a group program of instructions to receive hall call signals from group control equipment GCE (Fig. 2) and first car control signals and to apply group control signals to se-lected car processors and their associated car logic circuitry.
1~ U~S. Patent ~o. 3,614,995 discloses apparat~s oper-able to control a plurality of elevator cars as a supervised group. Apparatus is also disclosed by w~ich each individual car can operate in response to ~he registration of car calls therein and to signals signi~ying the-position of the car to cause the associated car to operate in a particular manner.
For example, when the car is located sto~ping distance away from a landing for which a car call is registered, the car is caused to initiate a stopping operation for that landing. A
skilled programmer or system analyst would understand how to program the apparatus disclosed herein to produce ~ similar result.
In doing this in the constructea emhodiment, t~e step-by-step sequence of instructions comprising the car pro-gram includes a subroutine which causes the transfer o~ in-formation indicating the registration o a car call for a particular landing to the associated car's processor, say ~or car "a"
CPU(a) (Fig. 11). Similarly, information indicating the loca-tion of car "a" at stopping distance from khe landing ~or which the call is registered is also transerred to car pro~
cessor CPU(aj.
In generating information for the registration o~ a car call in car "a", sa~ one for the 7th landing, a signal is generated by the optical coupler and level converter 18A asso-ciated with car "a"-(Fig.15) and with the 7th landing ~au3ing it ~o produce a ~inary zero signal. This signal is applied to car -call~selection~

;3~

device 430(a) (Fig. 14).
The subroutine by which car processor CPU(a) re-ceives the 7th landing car call information from car call se-.
lection device 430(a) is initiated by the program counter in-ternal to car processor CPU(a) (Fig. 11). As is well known, a count is added to the program counter at the completion o~
each Tl timing state o~ operation of the car processor to en-able it to operate in its step-by-step manner and to receive the next instruction from its car program storage means CROM(a) (Fig~ 13).
Under the assumed conditions, the instruction that is received from the car program storage means CROM(a) directs the car processor CPU(a) to receive the s;gnal applied along line 7CS(a) to car call selection device 430(a). In order to move the information from line 7CS(a) to the processor, as is well known, the car processor CPU(a3 must contain in addition to an 8-bit operational code or instruction received from iks program storage means CROM(a), a 16-bit address code. This lat-ter code identifies pin No. 3 o~ call selection device 430(a) to which line 7CS(a) is connected and enables the signal along line 7CS(a) to be transmitted to the car processor CPU(a).
The address code contained in car processor CPU(a~
: cau~e registers 358(a), 362(a)~ 360(a) and 364(a) -to apply six-teen corresponding signals along lines CA~(a) through CAlS(a) in the next well known Tl and T3 timing states of the processor.
The signals along lines CA0(a), CAl(a), and CA~(a) axe applied to pins 17, 10 and 9 of call selection device 430(a) ~Fig. 14) to select the signal applied thereto along line 7C~(a) and to - apply a corresponding signal to its output pin 5. The signals . 30 along lines CA10(a), CA13(a), CA14(a) and CA15(a) are such as -.~ to cause decoder 374(a) (Fig. 12) to produce a binary zero at its output pin 9. This is applied to decoder 372(a) ~hich in response to the operation of the address contained in the sig-nals along lines CA4(a)~ CA5~a) and CA6(a) produces a binary zero signal along line CEX0(a). The address signal applied along line CA3(a) and the binary zero signal along line cEx0(a) are applied to multiplexer 446(a~ and upon receipt of a binary one signal along line CRX(a) and a binary zero signal along line CWX(a) this multiplexer will appl~ a binary zero signal to input pin 7 of call selection device 430(a) A binary one signal .is applied along line C~X(a) during the T3 timing state because during its preceding T2 timing state, a binar~ zero signal was applied along line CT2(a) to flip-flop 376(a) to cause it to apply a binary one signal to And gate 380(c) from its pin 5 output. During the first half of the T3 timing state a binary one signal is applied along line CSYNC by processor CPU(a) (Fig. 11). This produces a binar~ one signal along line CT3A(a) which in combination with the binary one signal applied along line CA14(a) as the complement of the operational code signal along line CA14(a) causes And gate 380A(a) to produce a binary one signal on line CRX(a). A binary zero signal is applied along line CWX(a) because the processor is performing a "reading" operation and at the beginning of the T3 timing state the binary one signal applied along line C01~a) reset flip-flop 378B(a) causing it to apply the binar~ zero signal along line CWX(a).
- Upon t~e receipt of the ~inar~ zero signal at input pin 7, call selection device 430(a) applies a ~inary zero sig-nal along line CD0(a) for application to pin 3 of bidirectional bus driver 354(a) (~ig. 11~. Since the~proces~or is--in a T3 timing state and a "reading" operation is taking place, binary zero and binary one signals are applied along lines CCS(a) and CDIE~(a) respectively, for reasons which will be clear from the hereinafter described manner in w~ich comparable si~-nals are generatea along lines GCS(a) and CDIE~(a) (Fig. 4) when the group processor GPU(a) is operaking to receive data from the car data storage means CRAM(a) of car "a". These sig-nals along lines CCS(a) a~d CDIEN(a) cause the comp~emenk of the signal along line CD0(a)signifying khe re~istration of the 7th landing car call to be applied to the car processor CPU(a) for temporary storage therein. - -From the foregoing, it should be understood how other signals signifying other information relative to the elevator car are transferred from the car control equipment to the car processor CPU(a). For exc~mple, in~ormation indicative of eleva-tor car "a" being located at stopping distance away from the 7th landing is transmi-tted through hrush FPU(a) or FPD(a) (Fig. 17) depending upon the direction of travel of the car and contact FP7(a) to matrix MT(a). Binary signals indica-tive of this informationare transmitted along output lines CPl(a) through CP16(a) from matrix MT(a). These binary sig-nals are applied to their associated sel~ction devices 18B~a) (Fig 16). Output signals from selection devices 18E~ta) are transmitted along line CD0(a) to the car processor unit CPU(a) 15 (Fig. 11) in a manner in which the signal indicative of the registration of the 7th landing car call was transmitted there-to.
j The car processing unit CPU(a) Fig. 11) uses signals indicating that the car is located stopping distance away ~rom the 7th landing and that a 7th landing car call is in registration to control the car to cause i-t to stop at the 7th landing.. It does this by operating in response to their simul-taneous existence to generate a signal that a stop is to ~e ` ~ initiated. In so responding it pro~ides a signal along line ..
-~ 25 CD0(a) to pin 13 of decoder 444 for applica-tion to output pin 7 thereo~, in order to have the associated relay driver 18C(a) produc~-a binary one signal along line GO(a).. This signal upon application to coil ST(a) (Fig. 17) will release ~he associated stopping switch to cause the car to stop in a de-sired mannar in response to the consequent releasa of switches ~ ~ FE(a), E2A(a), ElA(a), EX(a) and U(a) or D(a) depending upon ;- : the direction of travel of the car. .
. .
It is desirable to store ~he signal along line CD0ta~
which caused the generation of the binary one signal along line GO(a) in the car data storage means CRAM(a) (Fig. 13) in order to have it available for later use. This is accomplished be-cause the processor in its step-by-step operation receives an eight bit "move" instruction to store the signal in this manner. This instruction is retained in the car processor CPU(a) and indicates ~hat a signal corresponding to that along line GO(a) shDuld be moved to car data storage means CRAM(a)~ In add:ition a six-teen bit address code is also contained in the car pro-cessor CPU(a).
The first eight of these latter sixteen signals are applied along lines CA0(a) - C~7(a) to da~a selec~ors 408(a) and 410(a) in preparation of addressin~ the car data storage means CRAM(a~. These signals upon application to the car data storage means will anable it to store a signal corresponding to that along line GO(a) in the location therein corresponding to the address indicated by the signals applied along lines CA0(a) - CA7(a).
` The las-t eight of the latter sixteen signals ar~
applied along lines CA8~a) --CA15(a). These signals are such ~` 20 as to enable the apparatus of Fig. lZ to produce a binary zeroon line CRSE(a) and a binary one on line CWX(a). The ~ormer of these signals exists as a result of the part of the - ~ -code applied along lines CAlO(a) 9 CAll(a1, CA13(a), C~14(a~
and CA15(a) which although now is changed from that previously described in that the signal along line CA14~a) is a binary ona . The latter signal along line CWX(a) is a binary one dur-ing the third timing state T3 o~ tha car processor unit because ~ during t~at period the signal on line CT3(a) is a binary zero `~ and during a "storing" operation the signal on line C~CW(a) is also a binary zero since the code signals CA14(a) and CA15~a~
are both binary ones. The binary zero signals along lines ~ CT3(a) and CPCW(a) cause flip-flop 378B(a~ ~o produce a binary ; one along line CWX(a)~
~he signals along lines CSS(a) ana CWX(a) are ap-plied to selector switch 416(a) (Fiy. 13) and with the binary , Q~

one signal then existing on line DTS(a)cause ~hat switch to operate to produce output signals in preparation for the car processor unit CPU(a) to'~rite information into" i.e., to store signals indicative o-f information in, the car data storage means CRAM(a). A binary one signal is applied along line DTS(a) as a result of the binary zero signal along line GA13 of the operational code of the gxoup prc,cessor which is always a binary zero except when the car processor GPU (Fig.

4) is to communicate with the car eguipment as will be ex-plained hereinafter. This causes line driver 196A (Fig. 9B~to appl~ a binary æero signal along line ~CRDY(a) to receiver 210(a) ~Fig. 10). This produces a ~inary zero at pins 3 and 8 of flip-flop 214A and 214B resetting them and causing a binary one signal along line DTS(a).
The binary one signal along line DTS(a) ~o~e~her ` with the output signals from switch 416(a) ena~le selectors 408(a) and 410(a) to transmit to car data storage means CRAM(a) the address signals applied along lines CA0(a) - CA7(a) in ~; preparation for the later transmission of the signal corres-ponding to that along line GO(a) to the car data storage means thxough data selectors 400ta) and 402(a). The signal corres-ponding to that along line GQ(a) is transmitted along line ~ CD0(a) through selector 400(a) in the next se~uence of opera-- tion. This takes place because car processing unit CPU(a) is actuated by the eight bit "move" si~nal to transfer this sig- -nal out through line CD0(a) immediately after having transmitted the "address" signals. ~As a consequence, ~he signal corres-ponding to that along line GO(a) flows along line CD~(a) into data selector 400(a) and t~rough t~at unit into the location in the car data storage means CRAM(aj identified by the ei~ht "address" ~its previously transmitted by the car processing unit CPU(a~. - -The retrieval of stored information from the car data storage means CRAM(a) by the car prscessing unit CPU(a) is similar to the operation by which the car pro~essing unit ~ ~ ~J,~3.~ 5 stores information in the car data skorage means. The difer-ence between the operation of storing and the operation of retrieval is that during the latter operation the 16 bit address signal must be such as to cause the apparatus of Figure 12 to change the status of the signal along line CWX(a) to a binary zero signal from the binary one produced during a "storing"
operation. This binary æero signal is applied along line Cr,~
in the same manner as was previously explained during the opera-tion of transferring the signal corresponding to that along liné GO(a) to the car processor unit CPU~a). The change in status takes place after the T3 timing state ends when ~he signal along line CT3(a) and the signal along line C01(a) ~e-come binary zero signals whereupon a binary zero is applied to pin 8 of flip-flop 378B(a). The signal along line CWX(a) is not changed to a binary one state duriny the T3 timing state o~
a "reading" operation as occurred during a storage operation because during the "reading" operation the siynal along line CPCW(a) is not a binary zero signal as it is durin~ a storage operation. As a consequence, flip-flop 378B(a~ remains in its reset condition during the "reading" operation and continues to apply a binary zero signal along line CWX(a). This enables the "reading" oE information from car data storage means CRAM(a) (Fig. 13); i.e., the car data storage means produces output signals along lines CD00(a3 - CD07(a) during the retrieval or ..:
"reading" cycle, in contrast to its receiving signals from the car processor unit CPU(a) applied thereb~ along lines CD0(a) -CD7(a) during the "writing" or storage cycle.
Also, t~e operational signals are such as ~o change the status of the signal along line CSS(a~ to a binary zero in a manner which will be clear fro~ t~e hereinafter explanation .
of how a binary æero signal is applied along line GSS when the group processor GPU(a) is receiving data~ This binary zero signal along line CSS(a) enables the signals along lin~s CD00(a) through CD07(a) to be transmitted by data selectors 366(a3 and 368(a).
~ 47 -.

/

~ 3 ~

It is to be understood that car processor unit CPU(a) can be controlled by instructions stored in car program storage means CROM(a) (Fig. 13) and received therefrom by way of lines CI00(a) - CI07(a) in a well known manner so that upon the initiation of the stopping operation in xesponse to the 7th landing car call the processor CPU(a) can transmit signals to cancel the call. This procedure would constitute a "writing"
operation and would be performed in a manner similar to that by which the processor "read" the 7th landing car call for the transmission thereto of a signal indicative thereof as has been explained. The difference between the "writing" operation and the "readin~" operation is that the address ~ code causes the generation of a binary one signal along line CWX~a) during the T3 timing state as opposed to causing the generation of a binary one signal along line CRX(a). Also, during the "writing" opera-tion a binary zero signal is transmitted along line CD0(a) to pin 13 of car call reset selector 438(a) as opposed to the "reading" operation during which a binary zero signal is trans-mitted along line CD0(a) from pin 5 o car call selector 430(a), as previously explained.
In response to the binary zero signal applied to pin 13 of selector 438(a) and the code corresponding to the 7th landing along lines CA0(a), CAl(a) and CA2~a) and the binary one signal along line CWX(a), selector 438(a) yenerates a signal along line 7CR(a) which is applied through the associated level converter 18A (FigO lSj to cause the exting-- uishment o~ the 7th landing car call tube 70(a) and accord-ingly the cancellation of the call.
It will now be ass~uned that a car call for the 7th landing is not registered ln car "a" but that the car pro-cessor CPU~a) (Fig. 11) has performed operations in accordance with a car position subroutine whereby ~he position of car "a"
as being located at stopping distance below the 7th landing as indicated by brush FPU(a~ (Fig, 17) engaging contact FPC7(a) is stored in a deined location in the car data stoxa~e means , CRAM(a), Also that the car processor CPU(a) has operated to establish the up direction of travel for car "a"~ As a con~
sequence a binary zero signal is applied along line AU(a) to the set coil SDG(a) whereby the direction rela~ is energized to maintain the up direction as the established direction of travel. Also assume that the group processor GPU (Fig. 4) has performed operations in accordance with a hall call subroutine and has received a signal indicative of the registration of an up hall call for the 7th landing. Also assume that in pro-ceeding in its step-by-step manner the group processor has operated to receive the car position information of car "a"
stored in its respective car data storage means CRAM(a) and has generated a signal to be transmitted to the car data stor-age means of car "a" to cause it to stop fo~ the registered lS 7th landing up hall call.
- In order to understand how t~e group processor unit GPU (Fig. 4) operates to receive signals directly from and to store ~signals directly into car data storage means CRAM(a) it will now be explained how the car position information of car "a" is received by t~e group processor unit and how a signal to cause car "a" to initiate a stop for a 7th landing hall call is transmitted from the group processor unit GPU (Fig. ~) to car data storage means C~AM(a).
The su~routine by which the group processor receives car position information from the car data storage means is initiated by the program counter internal to the group pro-cessor. As is well known a count is added to the program counter at the completion of each Tl timing state of operation of the group processor to enable the group processor operating in its step-by-step manner to recei~e the next instruction from its group program storage means GROM (Fig. 6). After receipt o~ this eight bit instruction in the well known manner the group processor uses it and ~he sixteen bit address code signals including those indicating the location in car cata storage means CR~M(a) in which the data of interest i5 stored - 49 ~

to acquire that data.
l~he address code signals in group processor GPU
(Fig. 4) are transmitted -through bus drivers 54 and 56 along lines GD~ to GD7 Eor storage in registers 58, 62, 60 and 64 in two timing cycles Tl and T2, in the standard manner ex-plained by the manufacturer's specification Eor the processor.
During the last quarter of the Tl timing state, the binary zero signal along line GTl (Fig. 9A) causes Nand gate 178A to produce a binary one signal at its output. During the second half of the T2 timing state, a binary one signal is applied along line G01 and a binary zero signal is applied along line GSYNC. ~s a result ~and gate 170B applies a binary one signal to pin 1 of ~lip-flop 172A. At the same time, a binary zero signal is applied along line GD5 to pin 16 and to complement is applied to pin 4. T~hen the last ~uarter of T2 timing state begins, a binary zero signal is applied along line GT2 to cause the output of gate 178A to transfer to a binary zero signal. As a consequence, a binary zero signal is also applied to pin 1 of flip-flop 172~ and ik produces a binary zero signal along line GSUS
The signal along line GSUS is applied to pin 17 of group processor GPU to cause it to suspend its standard se-~uence of operations at the end of the timing s-tate T2. This suspension continues Eor four W~IT states before the processor is permitted to enter its T3 timing state. In this way, re-gardless how out of synchronism the group and car processor ~; may be, the group processor waits a suf~icient time period to ensure that be-Eore ik enters its T3 state~the operation of the car processor has been suspended at t~e end of one of its T2 ~ ~ 30 timing states as will be explained.
;~ In the meantime, in response to the application of the address code signals along lines GD~ to ~D7 outputs are pro-duced along lines GA0 through GA15 and GA8 through GA15, the signals along the latter being the complements of the sig~als ; 35 along lines GA8 to GA15. These signals are produced by regis-~ . .
, -50-,. . .

, ., ., ~ ~fi~

ters 58, 60, 62 and 64 in the standard manner described ~y the manufacturer's specification. The binary one signal on ~ine GA13 causes dual two to Eour line decoder 74 and Ana gate 80D
to produce a binary one signal along line GRSE and line GSS.
These signals are applied to pins 18 and 19 of group data storage means GR~M (Fig. 6) and prevents the group memory from responding to the address signals along lines GA0 - GA7.
Since group processor GPU is to receive signals from car data storage means CR~M~a) of car "a~, the three sig-nals along lines G~8, GA9 and GA10 are coded to identify car'la" as the car selected to provide signals. These three sig-nals together with the binary one si~nals along lines GAll and GA13 and the binary zero signal along line GA13 cause three to eight line decoder 190 (Fig. 9B), data selectors 19~ and 194 and line driver 196A to opera-te to produce a binary one signal along line XCRD~(a)~ This isgnal is applied to differential line receiver 210 ~Fig. 10) and causes it to pro-duce a binary zero signal along line CSUSta) which is applied to pin 17 of car processor cPU(a) (Fig. 11) of car "a" causing it to suspend its operation at the end of its next T2 timing state.
Prior to the production of the ~inary zero signal along line GSUS (Fig. 9A) which caused the suspension of group processor GPU (Fig. 4), the signal along line GSUS was of the opposite state. At that time, that signal and a sirilar sig-nal along line GA13(Fig. 9A) (the signal along line GA13 is always a binary one except when the group processor is in communication with car equipment) caused the application of binary zero signals to pins 3 and 8 of J-K flip flop 180A and 180B. This produced a binary zero along line GCDT. While this signal continues and afker the signal on line GA13 beco.~es a binary zero, the address signals along lines GAl - GA7 (Fig. 4 are transmitted by daka selectors 100 and 102 along lines GCDl - GCD7 to the four differential drivers 126, 128, 130 and 132 shown in Figure 7.

_ ~L '~ 6 t 3 ~ ~

At this time, a binary zero signal is applied along line G8B (Figs. 7 and 9B) because the binary zero signals along lines GA13 and ~CDT (Fig. 9B) cause the binary one sig-nal applied along line L10 to input pin 11 of data selector 200 to be applied to line G8B and it~ complement to line G3B.
Similarly, the signal applied along line L10 to input pin 14 is applied to line GCTE.
As a consequence of the binary zero signals applied along lines GA13 and G8B, the signal from pin 4 o~ selectGr 100 (Fig. 7) which is applied to pin 3 of sel~ctor 116 and pins 2, 5, 11 and 14 of both selectors 116 and 118 is trans-mitted along lines GCD0(a) - GCD~(h)~ These si~nals are applied to the input pins of the dual differential line drivers 122, 123, 124 and 125 shown in Figure 7. In re~ponse to these signals and the binary one signal applied along line GCTE
these line drivers apply corresponding and complemen~ar~ sig-nals along lines DT0(a) and DT0(a) to DT0(h) and DT0(h).
In response to the signals applied along lines GCDl -GCD7 and the binary one level signal applied along line GCTE
dual dif~erential line drivers 126, 128, 130 and 132 apply signals along lines DT1 and DTl - DT7 and DT7 to khe second - set of ~ual differential line receivers 236, 238, 240 and 242 shown in Figure 10. It is to be understood that the signal lines DTl, DTI, DT2 .., DT7 are common to the dual differen-tial line receivers associated wi~h carina" shown in Figure 10 as well as those line receivers associated with additional cars ; ~ (not shown) but similar to those of Figure 1~ and provided for each additional car. Of course, lines DT0(a) and DT0(a) -DT0(h) and DT0(h) of each of these cars are connected only to the line receivers associated with their individual cars `
,, .,~ , _, ,~ _ .

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fi~3~
The dual differential line receivers 236(a), 238(a), 240(a) and 242(a) transmit an 8-bit binary signal correspond-ing to the address signal along lines GCB0(a) - GCB7(a) to the input pins oE a pair of bistable latches 224(a) and 226(a) shown in Figure 10. T~e corresponding equipment for the other cars operates similarly and will not be discussed further.
During the time interval in which the 8~bit address signals are being transferred from the bistable latches 58 and 62 shown in Figure 4 to the bistable latches 224(a) and 226(a) shown in Figure 10 as described, group processor GPU continues to apply signals along the line GS~NC to pin 2 of selector 200 (Fig. 9B). In response to each of these pulses, a similar pulse is applied along line GTP from line driver 204A. The second of these pulses causes line receiver 216(a) (Fig. 101 and flip-flops ~14A(a) and 214B(a) to apply binary one signa~s to their associated inputs of ~and gate 218A(a). As a result, - inverter 212A(a) applies a binary one signal to latches 224(a)and 226(a) to enable them to store the eight ~it address siy-nal applied to their input pins. This causes these latches to apply the eight bit address signals representing the address of the location in the car data storage means CRAM(a) along line GCA0(a)-GCA7(a) to the paix of data selectors 408~a) and 410(a) shown in Figure 13. --In the meantime, the binary zero signal along line -~ 25 GAll (Fig. 9B) has causea Mand gate 202B, selector 200 and line driver 204B to produce a binary one signal along line GDC. This is applied throug~ receiver 216(a) (Fig. 10) to pin 2 of latch 222(a) in which it i5 stored as a result of the binary one signal produced by inverter 212A(a~ as previousl~
described. At the end of the pulse along line GTP which caused inverter 212A(a) to produce the binary one signal, flip-flop 214B(a) (Fig. 10) produces a binary zero signal along line DTS (a) . At the same time, a binary one is produced at pin 11 of flip-flop 214B(a). This toyether with the binary one along line GDC causes And gate 220B(a) to produce a binary - 53 _ ~L~ ~.fri~

one signal. (The end of the pulse along line GSYNC which causes the pulse along line GTP to cease also caused flip-flop 180B ~Fig. 9A) to transfer the signal along line GCDT to a binary one. This caused the blnary one signal produced along ~ine GDC (Fig. 9B~ by the binary one signal along line GAll to cease. However, it is replaced by a binary one signal pro-duced as a result of the binary one signal along line GA14. ) rhe binary one signal from gate 220B(a) is applied to pin lO of line driver 228(a) and to one input of And gate 220A(a). The other input is also receiving a binary one sig-nal and as a result, input pins 7 and lO of drivers 230(a), 232(a) and 234(a) and input pin 7 of driver 228(a) also re-ceives binary one signals. Each of drivers 228(a), 232(2) and 234(a), consequently are prepared to transmit along lines DT0(a) and DT0(a)-DT7(a) and DT7(a) signals applied to them along lines CGD0(a) - CGD7(a).
;~ The signal on line DT0(a), as shown is applied to ; ~he input pin o dual differential line receiver 160 which ~; applies that signal to 3-to-8 line decoder 164 shown in Fig.
;; 20 ~he c~bit binary coded signal applied along the lines &A8, GA9 and GAlO causes the 3-to~8 line decoder 164 to select the binary signal applied along line CGB0~a) to its input pin and to apply a corresponding ignal from its output pin 5 along line CGB0 to input pin 3 of data selector 156 (Fig~ 8).
(If another car was the selected one the signals along lines GA8, GA9 and GAlO would select the signal for that car to be applied along line CGB0.) In addition, the signals on lines DTl to DT7 arQ applied along line CGBl to CGB7 to the input pins of data selectors 156 and 158 (Figc 8). Signals corres~
ponding to the signals applied along lines CGB~ to CGB7 to the input pins 3, 6, lO and 13 will be applied to the output pins 4, 7, 9 and 12 respectively of the pair of data selectors 156 and 158 in a manner to be describadO As shown, the output pins of the pair of data selectors 156 and 158 are connected by lines GD0 to GD7 to pins of the bidirectional bus drivers 54

- 5~ -J ~ d ,~i and 56 shown in Figure 4 to apply the binary signals repre-senting the data stored in the data storage means CR~(a}
to the data bus pins of group processor GPU.
At this time flip~flop 78B (Fig. 5) is producing a 5 binary zero signal along line GWX. This is the result of the flip-flop having been reset at the end of the last T3 timing state of group processor GPU (Fig. 4) b~ the binary one sig-nals along line GT3 and G01. The binary zero signal along line GWX together with the previously mentioned binary one lO signal along line GCDT (Fig. 9B) produces a binary zero along line GTP. This maintains the output from And gate 220C~a) (Fig. lO) along line GWD(a) at a binary zero.
The binary zero signals along lines DTS(a), GWD(a)-and HLl cuase data selector 416(a) (Fig. 13) to produce binary 15 zero outputs at its pins 49 7 and 9O These cause data selec-tors 408(a) and 410(a) to apply the address signals along lines GCA0(a) to GCA7(a) to car data storage means C~A~(a). As a - result of ~he output signals from data selector 416(a) the car data storage means CRAM(a) produces the signals stored in the 20 memories addressed by the address along lines CDO~(a)-CDO7(a).
These signals while applied to the car equipment o~ Figure 11 are ineffective to produce a result at least becaus~ the car processor unit is in a WAIT state and will not accept s~gnals even if applied thereto and because latches 35~3(a), 362(a), ,; .
~25 360(a) and 364~a) are rendered inoperable by binary zero sig-.~
nals applied along lines CTl(a) and CT2ta).
~ The signals along lines CDO0(a) tQ CDO7(a) are also `~ applied to And gates 412(a) and 414(a) ~Fig. 13). As a result of t~e binary zero Bignal applied along line DTS(a) these gates 30 apply these signals to lines CGD0~a) and CGD7(a). These sig-nals are transmitted to line driver~ 228ta)~ 230la), 232(a) and 234(a) (Fig. lO) and applied to lines DT~(a) to DT7 (a) .
Group processor unit GPU (Fig. 4) continues t~ pxo-i~ duce pulse~ along line GSYNC. At the end of the fixst of 35 these to be produced after the application of the binary zero ., i , !

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signal along line DTS(a) flip-flops 180~ and 180B ~Fig. 9A) apply binary one signals to input pins ~ and 13 of Nand gate 174A. Upon the production of the next pulse along line GSYMC, ~and gate 174A applies a binary zero signal to pin 3 o flip-5 flop 172A. rrhis causes a binary one signal to be produced on line GSUS which is applied to group processor GPU (Fig. 4) to enable it to leave its WAIT state and advance to a T3 timing state.
Before group processor GPU ~Fig. 4) entered its WAIT
state and at the end of its preceding T2 timing state a binary zero signal, as is well known, was applied along line ~T2 (Fig. 5) to pin 3 of flip-1Op 76A causing it to produce a binary one signal at its pin 5. This signal is combined in gate 80C with the pulse applied along line-GSY~C when the group processor enters its T3 timing state to produce a binary one signal along line GT3A. This signal together with the binary one signal of the operational code along line GA14 of the complement of the signal of the operational code along line GA14 causes gate 80A to produce a binary one along line GRX. This signal is applied to input pin 9 of Nand ~ate 174C
(Fig. 9A). In addition Nand gate 174C receives binary one level signals applied to it along lines GA13 and GCDT from pin 11 of flip-flop 180B and produces a ~inary æero level signal~
This is applied along line GRCE to the enable input pin~ 15 of the pair o~ data selectors 156 and 158 (Fig. 8) to enable the data selectors to operate.
m e binary one signal along line GCDT also causes the binary one signal appIied to input pin 6 of selector 200 (Fig. 9B) to be applied along line G8B. This input signal and consequently the signal along line G8B are binary one si~nals as a result of the binary one signal of the operational code along line GA14. The binary one level signal applied along line G8B actuates the pair of data selectors 156 and 158 (Fig. 8) so that the signals applied to input pins 3, 6, 10 and 13 are transmitted to the output pins 4, 7, 9 and 12 _ 56 _ ~3 ~

respectively. Consequently, .in response to the binary zero signal to them along line GRCE the data selectors 156 and 158 (Fig. 8) apply binary signals representing the data to be received by the group processor along lines GD0 to GD7 to the bidirectional data bus pins of the bidirectional bus drivers 54 and 56 shown in Figure 4. The bidirectional bus drivers txansmit the complements of the signals applied to them along lines GD0 to GD7 to the input pins of the group processor upon receipt of a binary one signal applied along line GDIEN in conjunction with the binary zero applied along line GCS.
The signal along line GCS at this time is a binary zero because at the end of the last T2 timing sta-te a binary zero pulse was applied along line GT2 to pin 11 of flip-flop 76B (Fig. 5) and caused a binary zero to be applied along line GCS. The binary one signal along line GDIE~ is produced in response to the binary one level signal from And gate 80C
(Fig. 5) being combined with the binary one level signal from the output pin 7 of three to eight line decoder 74 applied along line GPCW to produce a binary one level signal along line GDIEN. The signal along line GPCW is a binary one be--~ cause a "readingl' operation is being undertaken and as the manufacturer's specification teaches during such time the signals along line GA14 and GA15 are to be in the binary zero and binary one states, respectively. With the blnary zero along line MLl it is well known that these signals will pro duce a binary one along line GPCW from decoder 74.
As a result of the application of the binary one signal along line GDIEN and the binary zero signal along line GCS the data signal indicative of the position of car "a" has now been transmitted to group processor GPU. Car processor - CPU(a) can now be restored to operation, This is accomplished because during the next Tl and T2 timing states of group pro-cessor GPU a binary zero signal is applied along line GA13.
This causes line driver 196A (F.ig. 9B~ to produce a binary zero signal along line XCRDY(a) which is applied to receiver 210(a) (Fig. 10). As a result, a binary one signal is applied along line CSUS(a) to pin 17 o~ car processor CPU(a) (Fig. 11) re-lieving it from its W~IT state. Simultaneously, inverter 212D
(Fig. 10) applies a binary zero signal to reset pins 3 and 8 o~ ~lip~flops 214A(a) and 21~(a) to produce a binary one sig-nal along line DTS(a) to enable the car processor CPU(a) to communicate with its car data storage means CRAM(a) once again.
At the same time a binary zero signal is produced along line GCDT in response to binary one signals along lines GSUS and .
GA13 as previously described.
From the foregoing, it is to ~e understood that group processor GPU can employ the information concerning the location of car "a" to determine whether the car should be stopped in response to registered hall calls. It can do ~his by acquiring information concerning the registration o~ such calls from the equipment of Figures 3A and 3B in a manner si-` milar to that explained in which car "a" acquired the informa-tion concerning the registration of the car call for the 7th landing from the equipment of Figure 14. Also, group proces-sor GPU would acquire information ~oncerning the direction of travel of car "a" in a manner similar to that explained in which it acquired the information concerning the location o~
car "a". Upon determining that the location o~ car "a" and that its direction of travel was proper for causing it to stop in response to a registered hall call that information c~n be ~ .
transmitted to the car data storag~ means of car "a" in order for its processor unit CPU(a) to use it to initiate the stop-ping of car "a" in a manner similar to that explained for initiating the stvpping o~ car "a" in response to the 7th landing car call. To do this, a signal must be transmitted by group processor GPU to a particular location in car data ,~ storage means CRAM(a) (Fig. 13). This is performed in a man-ner similar to that explained by which group processor GPU
obtained information ~rom car data storage means CRAM(a).

i3 The operation of "storiny" or "wri-ting" data in car data storage means CRAM~a) proceeds in the same mannex as the previously described operation of "retrieving" or "reading"
data therefrom up to the transmittal of the address oE in-terest of the data storage means along lines GCA0(a)-GCA7(a) to selectors 408(a) and 410(a) (E`ig. 13). Becaus~s this operation comprises the "storing" of data the signal along line GAl4 of the address code is a binary one as opposed to the binary zero it was during the described "reading" operation. Conse-quently, the complement along line GAl4 (Fig. 9B) is a binaryzero signal. Thus, instead of a binary one signal being applied along line GDC (Fig. 9B) subsequent to ~he application of a binary one signal along line GCD~ to selector 200, a binary zero signal is applied along that line. Gates 220B(a) and 200A
- 15 (a) (Fig. lO), therefore do not produce binary one signals to enable drivers 228, 230; 232 and 234 to operate as described in the "retrieving" operation. Instead binary zero signals ` are applied to the pins 7 and lO inputs to prevent the opera-tion of these drivers which prevents these drivers from inter-ferring with the "retrieve" operation~
Also, the hinary one signal along line GAl4 pro duces a binary one signal along line GCTE during the group processor WAIT state to enable drivers 122 through 130 to operate during the "storing" operation in contrast to ~he binary zero signal which had been produced along line GCTE
during the "retrieving" operakion to prevent khese drivers from operating and interferring with that operation.
Also, the binary zero signal along line GAl4 causes the production of a binary zero signal along line GRX (Figs.
5 and 9A) during the "storing" operation as opposed to the binary one produced therealong during the '~retrieve" opera-kion. As a conse~uence of this change a binary one signal is applied along line GRCE (Fig. 9A). ~his disables selectors 156 and 158 (Fig. 8) from applying signals along lines GD~ -GD7 and interferring with khe "storing" operation.

6~ 3 Consequently, when group processor GPU enters its T3 state, as previously explained for the "retrieve" operation, it now places the data signals to be transmitted to car data storage means CRAM(a) on bus lines GD0 - GD7 (Fig. 4) in typical fashion since it is per~orming a "storing" operation.
These signals are transmitted through selectors lOO, IO2, 116 and 118 (E'ig. 7) onto lines GCD0(a) - GCD0(h) and GCDl - GCD7 to drivers 122 - 130. (Since only car "a" is to receive these signals only its equipment will be hereafter referred to.) These drivers transmit corresponding signals along lines DT0(a) and DT~(a)~ D~7 and DT7 to receivers 236(a)-242(a) (Fîg. lO).
Corresponding signals are applied along lines GCB0(a)-GCB7~a) by these receivers to data selectors 400(a) and 402(a) (~ig 13)~
Since the binary one signal along lin~ GA14 has pro-duced a binary zero signal along line GPCW ~Fig~ 5), when t~e T3 timing state reaches its last quarter, the binary zero sig~
nal along line GT3 (Fig~ 5~ causes flip-flop 78B to produce a :~ binary one signal along line GWX. This signal causes selector ~:~ 200 ~Fig. 9B) to produce a binary one signal along line GTP forapplication to receiver 216(a) (E'ig. lO). In the meantime, dur-ing the WAIT state as previously explained for the "retrieve"
operation, flip-flop 214B(a) (Fig.lO) has produced a binary one signal from its pin 11. This in combination with the bi.
nary one signal produced ~rom pin 2 of receiver 216(a) as a result of the siynal applied along line GTP causes gate 220C(a) to produce a binary one signal along lin~ GWD(a)v ~he binary zero signal along line DTS~a) (Fig. 13) : which was produced during ~he W~IT state as explained ~or the "retrieve" operation in combination with the binary on~ signal : 30 along line GWD(a) causes selector 416(a~ to appl~ a binary onesignal to inv2rter 418~(a) (Fig 13)~ This causes a binary zero signal to be applied to pins 20 of the car data sto~age means CRAM(a) and pins 15 of selectors 400(a) and 402(a~. In the : meantime, during the WAIT state the binary zero signal along line DTS(a) in combination with the binary zero signal alon~
,~ .
., , ~, line HLl has caused selectors 408(a) and 410(a) to apply the ad-dress signal to car data storage means CRAM(a). ~s a consequence the data signals on lines GCB0(a) and GCB7(a) are transmitted into car data storage means CRAM(a) for storage therein.
The car processor CPU(a) is released from its suspen-ded state in the same manner as explained for its release Erom that state after the "retrieval" operation. It should be under-stood from the foregoing how the information that the car is to initiate a stop in response to a hall call can be employed by car processor CPU(a) to have the car control equipment perform such an operation and consequently or purpo~e~ of brevity this operation will not be described~ -As described the group processor GPU operating in ac~
cordance with its group program o~ instructions is operable to cause the suspension of its sequence of operations and the se~
quence of operations of a single selected car processor CPU(a) in order to receive car data signals from or ko transmit group data signals to its associated car data s~orage means CRAM(a~.
It is to be understood, however, that in the constructed embodi--ment the group processor does not operate to ~ransmit 8-bits of useful information simultaneously to a single carls data s~orage means. Rather, only that information contained in a particular one of the 8-bits is use~ul to a given car~ When :it is desired to transmit information to car "a" ~hat information .is placed along line GD0 w~ich will xesult in a signal correspondin~ to that information being applied along line DT0~a~. Similaxl~, in-formation fox car "b" is placed along line GDl resulting in a signal on line DT0(b), and so forth~
Also, in the constructed embodiment, the group proces-sor operates in a manner similar to the manner described with re-spect to car "a" but causes the simultaneous suspension of the sequence o~ operation of all car processors in order to receive car data signals from or to transmit group data signals to asso~
ciated car data storage means CR~M(a)~Fî~13) and CRA~(b) throu~h CRAM(h)(not shown). Since the operation in which the group pro-cessor receives car data signals from or transmits group data signals to the car data storage means CRAM(a) is similar to the operation in which it simultaneously receives car data signals Erom or transmits group data .s.ignals to each of the car data storage means only the diffe.rences be-tween these two operations will hereinafter be described.
It will be assumed that the group processor receives an instruction to receive car data signals from the car data storage means associated with each car. The group processor operating in accordance with -this instruction applies an address code signal to la~ches 58, 62, 60 and 64 in the manner previously described which causes the group processor to suspend its se~uence of operations. In accordance with this assumed instruction latch 60 applies a hinary zero signal along line GAll and a binary one signal along line GAll as . opposed to the binary one and zero signals applied therealong signifying data transmission between the yroup processor and . the car data storage means associated with a single car as . previously described~ ~
The binary zero signal on line GAll causes data selectors 192 and 194 (Fig. 9B) to apply ~he complements of the siynal applied to their input pins 2, 5, 11 and 1~ to drivers 196A, 196B, 198A and 13~B and to the additional dri-~: -vers associated with cars c through g (not shown). As ~ re-; ~ 25 .sult driver 196A applies a binary one signal along line ~ XCRDY(a) to receiver 210(a) (Fig. 10) to cause it to apply a ; suspension signal to car processor CPU(a) (Fig. 11~ as pre-~: viously described. Similarly binary one signals are simul-taneously separately applied along lines XCRDY ~) through XCRDY(h) to the circuitry similar to that shown in Figure 10 associated with each car to cause that c.ircuitry to apply a sus-pension signal to the car processor with which it is associated.
Subse~uent to the application of the suspension signal to each car processor the address .signals are to be applied along bidirectional signal transmission lines DT0(a), - ~2 -- . -3~

DT0(a), through DT0(h), DT0(h) and DTl, DTl through DT7 and DT7 to the equipment associated with each of the cars in the manner in which the address signals were applied along lines DT0(a), DT0(a) and DTl, DTl through DT7 and DT7 to the circuitry associated with car "a". However before these address signals can be transmitted the drivers associated with each car processor which are similar ko drivers 228(a), 230(a), 232(a) and 234(a) associated with car "a" shown in E'igure 10 must be prevented from interferring with those address signals. Consequently, signals on lines GA8, GAg and GA10 are chosen to cause decoder 190 (Fig. 9B) to apply a binary one level signal to ~and gate 202B(a). In response to this signal and the binary one signal on line GAll Nand gate 202~(a) causes a binary zero signal to be applied from pin 7 of selector 200 to driver 204B(a). As a result driver 204B(a) applies a binary zero signal along common line GDC instead o~
the binary one signal previously described. This binary zero ~gnal is applied to receiver 216A(a) (Fig. 10) which applies it to register 222(a) for storage therein when Nand gate 218A
(a) causes a binary one signal to be applied thereto as pre-viously described. In addition the binary zero signal is also stored in registers similar to register 222(a) associated with each car. As a result register 222(a) shown in Figure 10 , for car "a" and similar registers apply a binar~ zero signal t:o ~nd gate 220A(a) and similar gates associated with the ; other cars to prevent drivers 228(a), 230(a~, 232(a) and 234(a) associated with car "a" and similar drivers~from interferring with the signals on lines DTl, DTl through DT7 and DT7. In addition the binary zero signal on line GDC causes a binary zero signal to be applied to And gate 220B(a) and similar gates,not shown, to prevent driver 228~a) and similar drivers associated with the remaining cars from interferring with the address signals to be transmitted to the circuitry associated with each car.
As previously described in the "reading operation"
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the address signals are applied through data selectors lOO and 102 (Fig. 7) to data selectors 116 and 118 and along lines GCDl through GCD7 to drivers 126, 128, 130 and 132. At this time the least significant bit (LSB) of the first eiyht bits of the address signal is applied through selectors 116 ana 118 along lines GCD0(a) through GCD0(h) to drivers 122, 123, 124 and 125. Drivers 122 through 125 apply the LSB of the first eight bits of the address along lines DT0(a) and DT0(a) individually to receiver 236(a) shown in Figure lO and along lines DT0(b), DT0(b) through DT0(h) and DT0(h) individually -to similar receivers associated with each car. Drivers 126, 128, 130 and 132 apply the seven most significant bits of the a~dress along lines DTl, DTl through DT7 and DT7 to receivers 236(a), 238(a), 240(a) and 242(a) and to similar receivers associated with each car. As a result in view of the prior description in which the address signals are applied to the car data storage means CRAM(a) it is to be understood that the similar circuitry asso-ciated with each of the cars operates in the same manner to apply the first eight bits oE the address signal to the car data storage means CRAM(b) through CRAM(h) (not shown).
It will now be ass~med that the data stored in the locations of each car data storage means identified by the address signal applied thereto is to be received by the group processor. As previously described this is also Xnown as a "reading" operation and as previously described during a "reading" operation the drivers 122 through 130 (Fig. 7) are prevented from interferring with signals applied along lines DT0(a), DT0(a) through DT0(h) and DT0(h) and DTl ~hrough DTl through DT7 and DT7.
During this reading operation a single bit of data will be received by the group processor from the car data storage means associated with each car processor as opposed to the reading operation previously described in ~hich up to eight bits of data were received by the group processor from the car data storage means CR~M(a) associated with car processor CPU(a).

The single bit of data to be received from the circuitry associated with each car is to be transmitted along lines DT0(a), DT~(a) through DT0(h) and DT0(h) to the receivers 160, 161, 162 and 163 shown in Figure ~. Al-though the follow-ing description is directed to the circuitr~ associated with car ''a" which applies the single bit of data along lines DT~(a) and DT0(a~ it is also applicable to the circuitry associated with the remaining cars (not shown) which apply a single bit oE data along lines DT0(b), DT0(b) through DT0(h) and DT0(h).
As previousl~ described during a "read" operation selector 200 ~Fig. 9B) applies the binary one signal on line -GA14 to driver 204B which transmits 1-hat s.ignal along common line GDC to receiver 216ta) ~Fig.10). I~ response to the binary one signals from receiver 216~a) and flip-flop 214B(a) And gate 220B applies a binary one signal to pin 10 of driver 228(a) which transmits the signal it receives from.the car data storage means CRAM(a) along lines DT0(a) and DT0 (a3 to receiver 160 (Fig. 8). The circuitry associated with the additional cars similarly tran~mit the data signals along lines :.~ DT0(b), DT0(b) through DT0(h) and DT0(h~ -to receivers 160, 161, 162 and 163. These data signals are applied along lines CGB0(a) through CGB0(h) to salectors 156 and 158. At khis time selector 200 applies the binary one signal from ~and gate 202~ (Fig. 9B) along line G8B to selectors 156 and 158 which - operate to apply the slgnals applied thexeto along lines CGB0(a) through CGB0(h~ to lines GD0 throug~ GD7 connected to : bidirectional bus drivers 54 and 56 ~Fig. 4) for kransmission to group processor GPU.
If the address code is such as to cause the group processor unit to ~ransmit a single bit of data to each car the first eight bits of the address are first applied to the car data storage means associated with each car, as described.
During the time period T3 of the group processor the data is applied along lines GD0 to GD7 through selectors lOQ and 102 - ~5 ~

~3 ~

(Fig. 7) to selectors 116 and 118~ At this time the binary one signal from And gate 202B (Fig. 9B) is inverted and applied along line G8B to data selectors 116 and 118 (Fig. 7) to cause them to apply signals corresponding to the signal on pin 4 of data selector 100 along lines GCD0(a) through GCD0(h) to drivers 122, 123, 124 and 125. The remaining _ircuit operation is similar to that described during a "write" opera-tion in which data is transferred to the car data storage means CRAM(a) associated with car "a".
~ t is understood that various modifications to the above described arrangement of the invention will become evident to those skilled in the art and ~hat the arrangement described herein is for illustrative purposes and is not to be considered restrictive.

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Claims (10)

What is claimed is:

1. A control system for use in an elevator in-stallation having a plurality of cars serving a plurality of floors, said installation having group control equipment com-mon to said plurality of cars including hall call registration means producing hall call signals and car control equipment individual to each of said cars for controlling its associated car, each said car control equipment including car operating apparatus, car call registering means and car position signi-fying means, the latter two producing car call and car posi-tion signals, respectively, said control system connected to both said car control equipment and said group control equip-ment for receiving therefrom car call and car position signals and hall call signals, said control system comprising:
program storage means storing control programs of instructions therein including a car program of instructions for each car and a group program of instructions;
car processing means connected to said program storage means, said car processing means sequentially perform-ing a first set of operations by following in a step-by-step manner each car program of instructions to produce first car control signals in response to said associated car call and car position signals and to apply said first car control sig-nals to the associated car operating apparatus to cause it to operate its associated car in a particular manner; and group processing means connected to said program storage means and to said car processing means, said group processing means sequentially performing a second set of operations by following in a step-by-step manner said group program of instructions to produce group control signals in response to selected first car control signals and hall call signals and to apply said group control signals to said car processing means;
said car processing means operating to produce second car control signals in response to said group control signals and to apply said second car control signals to said individual car operating apparatus to cause said car operating apparatus to operate said associated cars in response to said hall call signals as a supervised group; wherein said car processing means includes a separate car processor and separate car logic circuitry associated with each of said cars, said separate car logic circuitry connecting each car processor to said program storage means, said group process-ing means and the car control equipment individual to its associated car, each car processor performing in accordance with the car program of instructions for its associated car to produce said first and second car control signals in re-sponse to said car call and car position signals and said group control signals and to apply said first and second car control signals through said connected car logic circuitry to said associated car operating apparatus to cause it to operate said associated car as a member of the supervised group, and wherein said group processing means includes a group processor and group logic circuitry connecting said group processor to said program storage means, said group control equipment and through said separate car logic circuitry to each said car processor, said group processor in sequentially performing said second sequence of operations in accordance with the group program of instructions producing group control signals in response to said hall call signals and selected first car control signals from each said car processor, said group con-trol signals being applied to said group control equipment and through said group logic circuitry to each said car processor to control the operation of said associated cars as a super-vised group.

2. A control system according to claim 1, wherein said group logic circuitry includes a group suspension signal generator connected to said group processor, said group pro-cessor in sequentially performing said second set of operations receiving a particular group instruction that it is to receive a first or second car control signal from or that it is to transmit a group control signal to a particular car processor, said group processor operating in response to said particular group instruction and causing said group suspension signal generator to produce a group suspension signal which is ap-plied to said group processor to cause it to suspend the se-quential performance of its second set of operations.

3. A control system according to claim 2 , wherein said group logic circuitry includes a car suspension generator connected to each said car processor, when said group processor receives said particular group instruction it contains an ad-dress code including a car selection signal identifying a se-lected car, said group processor applying said car selection signal to said car suspension signal generator to cause it to produce a car suspension signal for said selected car, said car suspension signal generator applying said car suspension signal to said selected car processor to cause it to suspend the sequential performance of its first set of operations.

4. A control system according to claim 3, wherein each said logic circuitry includes associated car data storage means for receiving and storing associated first and second car control signals and group control signals, and wherein said group logic circuitry include a separate data transfer signal generator associated with each car, each data transfer signal generator connected to its associated car's logic cir-cuitry and to said car suspension signal generator, each said data transfer signal generator operating in response to a car suspension signal for its associated car to produce a data transfer signal signifying that said associated car logic circuitry is conditioned so that a first or second car control signal can be supplied from said associated car data storage means to said group processor or that said group processor can transmit a group control signal to said associated car data storage means.

5. A control system according to claim 4, wherein each car's logic circuitry includes car data switching means, each connecting its associated car processor to its associated car data storage means to enable said associated car processor to apply first and second car control signals to said associa-ted car data storage means for storage therein and to retrieve said stored first and second car control signals therefrom, each said car data switching means operating in response to its associated data transfer signal to disconnect its asso-ciated car data storage means from its associated car proces-sor and to connect said storage means to said group processor to enable a first and second car control signal to be supplied from said associated car data storage means to said group processor or to enable said group processor to transmit a group control signal to said associated car data storage means.

6. A cortrol system according to claim 5, wherein when said particular group instruction is received by said group processing means it contains address signals identifying a location in said selected car's data storage means in which is stored a particular first or second car control signal that said group processor is to retrieve or in which a particular group control signal is to be stored, said address signals being transmitted from said group processor to said car data storage means through said car data switching means in response to the connection and disconnection operation caused by the generation of the associated data transfer signal.

7. A control system according to claim 6, wherein said particular first or second car control signal is re-trieved from or said particular group control signal is stored in said car data storage means by said group processor by transmission through said car data switching means in response to the connection and disconnection operation caused by the generation of the associated data transfer signal.

8. A control system according to claim 7, wherein when said group processor receives said particular group instruc-tion that address code it contains can identify a plurality of cars as being selected, and said group processor can retrieve a first or second car control signal from the car data storage means of each of said selected cars simultaneously or store the same group control signal in the car data storage means of all of said cars simultaneously.

9. A control system according to claim 4, wherein said program storage means includes a group program storage means storing said group program of instructions and a plur-ality of car program storage means each storing a car program of instructions for an associated car, each said car program storage means including instructions for the associated car processor to store first and second car control signals in identified locations in its associated car data storage means for retrieval by said group processor, and said group program storage means including instructions for the group processor to store group control signals in identified locations associated car data storage means for retrieval by the associated car pro-cessor, said group program storage means also including instruc-tions for the group processor to retrieve first and second car control signals from associated car data storage means.

10. A control system according to claim 3, wherein said group logic circuitry includes a group register, said group processor applying said address code including said car selection signal to said group register for storage therein, said car register operating to apply said car selection signal to said car suspension signal generator until said group processor in operating in response to the sequential performance of said second set of operations applies another address code to said group register.