NO311630B1 - Customizable data equalizer with frequency shift direction estimate - Google Patents

Description

The present invention relates to an adaptable data equalizer that can be used to reduce the degree of deterioration of data transmission at high bit rates in digital mobile communication when the transmission properties deteriorate to a significant extent due to waveform distortion caused by frequency-selective fading.

Until now, there have been baseband equalizers for waveform adaptation, which are able to track a fast time-varying channel, such as in mobile communication, and whose initial setting can be affected by a learning process for a short period of time. An example of known adaptive equalizers of this type is a decision feedback adaptive equalizer discussed by Nakajima and Sampei in the article "Performance of a Decision Feedback Equalizer under Frequency Selective Fading in Land Mobile Communications" in the publication "Transaction of the Institute of Electronics, Information and Communication Engineers" (B-ll), J72-B-II, No. 10, pages 513 - 523 (October 1989).

Fig. 3 of the accompanying drawings is a block diagram of the adaptive data equalizer with feedback decision, which is discussed in the above-mentioned publication and which is designed for use in a system where the received signal is a QPSK modulation signal (with a (bit rate of 2/T bits per sec., where T is the symbol time).

In said figure, the reference numeral 1 denotes a feedforward transversal filter (hereinafter referred to as the "FF part"), where the tapping interval is a predetermined time delay Tp (seconds) and the number of tappings is L, while the reference numeral 2 denotes a feedback transverse filter (hereinafter referred to as the "FB part" ), where the tap interval is a predetermined time delay T (seconds) and the number of taps is (M - L). An addition section 3 adds together the output data from parts 1 and 2, respectively. FF and FB. A decision circuit 4 identifies a data sequence emitted from the addition link 3 every T seconds and makes a hard decision on this basis. An update circuit 5 for tapping coefficients determines the tapping coefficients for the FF part 1 as well as the FB part 2 for each number of T seconds. A switching circuit 6 operates so that either the data sequence emitted from the decision circuit 4 or a reference data sequence is selectively supplied to the FB part 2. The reference number 7 indicates an input port for a received signal to the adaptive data equalizer with feedback, while the number 8 indicates an input port for a reference sequence and the number 9 specifies an output port for the adaptive equalizer.

Fig. 4 shows an example of the signal burst format for signals used for mobile communication.

The signal burst format shown in fig. 4 comprises a unique data word (UW - Unique Word) 13 which is used for learning an adaptive equalizer with decision feedback and for creating frame synchronization, random data a (bits of information) 14, a color code (hereinafter referred to as "CC" - Color Code) 15 which used to identify a base station or as a learning sequence for the equalizer, as well as random data b (bits of information) 16.

The operation of the prior art adaptive equalizer with decision feedback will be further explained below.

In the adaptive data equalizer with decision feedback shown in FIG. 3 and which is performed for a system where the received signal is a QPSK modulation signal, the received signal is converted to a baseband signal by a demodulator, and the channel characteristics are evaluated using the unique data word (UW) 13 (shown in Fig. 4). which is located at the beginning of each signal burst, thus causing the tapping coefficients to converge (learning mode). The signal supplied to the FB part is at this point without decision error, i.e. a reference data sequence determined by the unique data word (UW) 13. The equalization is then performed on the arbitrary data a 14, CC 15 and the arbitrary data b 16 (following -mode).

For the arbitrary data a 14 and b 16, the signal emitted from the decision circuit 4 constitutes the input to the FB part 2 in the form of a received signal sequence. With regard to CC 15, a reference data sequence determined by CC 15 constitutes the input to FB part 2.

The tapping coefficient update circuit 5 provides for updating the tapping coefficients of the FF part and the FB part 1 and 2 for each symbol in accordance with a tapping coefficient updating algorithm, e.g. The Kalman filter algorithm (RLS algorithm) by utilizing the received signal sequence supplied to the adaptive data equalizer with decision feedback, the reference data sequences determined by the various known learning sequences for the unique data word (UW) 13 and the color code (CC) 15, the output data sequence from the decision circuit 4 and the output data from the addition stage 3.

As an example of an update algorithm for tapping coefficients, the Kalman filter algorithm (RLS algorithm) will be briefly explained below.

It is assumed that the signal vector applied to the equalizer at time t = nT (n = 0, 1,2, ...) is XM(n), the tapping coefficient is CM(n), the output of the equalizer is l(n), the desired output is d(n) and the error is e(n).

Here XM(n), CM(n), l(n) and d(n) are complex numbers comprising one component (or channel) in phase and one in quadrature.

It is now assumed that the number of taps in the FF part 1 of the adaptive equalizer with decision feedback is L, while the total number of taps is M. Then the above factors can be represented as follows:

In the above equations, * represents a complex conjugate transpose matrix (or vector).

In addition, d(n) is a known learning sequence in learning mode, while in tracking mode it is an output data sequence that is obtained from the decision circuit 4 as a result of a hard decision made on the result of equation 3. The desired value is in this algorithm the tap- coefficient CM(n) which reduces to a minimum the estimation function e which is represented by:

where X represents the forgetting factor (0 < X < 1).

The CM(n) that gives the minimum value of equation (5) is given by:

where 8 is a positive constant.

The algorithm for iteratively deriving CM(n) at a time t = nT from CM(n-1) and P(n-1) at a time t = (n - 1 )T is as follows:

where K(n) is the Kalman gain, P(n) is the covariance matrix for the tapping coefficient error and I is the identity matrix.

It should be noted that the tap coefficient update algorithm is described in detail by S. Haykin in "Introduction to Adaptive Filters", Chapter 5, Gendai Kogaku-Sha (1987), translated by Tsuyoshi Takebe, and by J.G. Proakis in "Digital Communications", Chapter 6.8, McGraw-Hill (1983).

In the foregoing, an adaptable equalizer with decision feedback has been described, as shown in fig. 3, which is designed for a system where the received signal is a QPSK modulation signal. In the following, consider a case where the received input signal to the above adaptive data equalizer is a 7t/4 shifted QPSK modulation signal (with a bit rate of 2/T bits per sec, where T is

the symbol time).

Here, as an example of 7t/4-shifted QPSK modulation, the coding scheme specified in EIA document IS-54, "Cellular System Dual-Mode Mobile Station Compatibility Standard" (December 1990), will be shown, and the reference signal for an adaptive data equalizer with this code scheme will also be explained.

Fig. 5 is a block diagram showing an embodiment of equipment for coding a transmission data sequence in accordance with the above-mentioned coding scheme.

In fig. 5 it is shown that a transmission data sequence bm is sequentially reshaped from the first data, by reshaping from series to parallel in such a way that odd numbered data is reshaped into a data sequence XK, while even numbered data is reshaped into another data sequence YK. The sequences XK, YK are then transformed into a transmission data sequence (lK,QK) by differential coding in accordance with equations 13a and 13b:

The phase change A<j> is given in accordance with the table shown in fig. 6.

If it is assumed that the reference point (I.,, Q.,) is (2<1/2>, 0) and that the transmission data sequence bm (1,-1,1,-1,1,-1,-1,1, -1,-1,-1,1,1,1,-1,1,1,1,1,-1,-1,1,-1,-1,1,-1,1,-1) is processed in accordance with the coding scheme mentioned above, it will be transformed into the differently coded data sequence (1K, QK) which is indicated in the table in fig. 7.

Consequently, when the transmission data sequence bm is UW 13 or CC 15, the data sequence (1K, QK) shown in the table in fig. 4 be used as the reference data sequence for the adaptive data equalizer shown in FIG. 3.

The decision circuit in the known adaptive data equalizer will now be explained.

In the adaptive data equalizer with decision feedback shown in FIG. 3, a decision is made in the decision circuit 4 on the basis of the output from the addition term 3, using the method explained below: First, the output (l'(K), l<Q>(K)) from the addition term 3 is sorted depending on whether K is an odd number or an even number (where K here represents the output data from the addition term 3 for the K-th symbol): (a) When K is an odd number, the output (l'(K),l<Q>(K)) from the addition term 3 subject to an arithmetic operation for a phase rotation of n/ 4, and the phase-shifted data (l''(K), l<Q>'(K)) is considered to determine a decision value (d'(K), d<Q >(K)) depending on whether the sign of (l'(K), lQ (K)) is positive or negative, as shown in fig. 8(a). (b) When K is an even number, the output (l'(K),l<Q>(K)) from addition term 3 is assumed to determine a decision value (d'(K), d<Q>(K)) depending on the sign for (l'(K), l<Q>(K)) is positive or negative, as shown in fig. 8(b).

Furthermore, the above stated decision value (ie the output from the decision circuit 4) is differentially decoded to obtain an equalized data sequence.

When the received input signal to the adaptive equalizer shown in fig. 3 is a 7t/4-shifted QPSK modulation signal, as described above, the output (l'(K), l<Q>(K)) from the adder 3 is sorted according to whether K is an odd number or an even number. When K is an odd number, the output (l'(K), l<Q>(K)) from the addition term 3 needs an arithmetic operation for the phase rotation of 7t/4. The number of arithmetic operations required in the decision circuit 4 therefore increases, and the arrangement becomes complicated.

Common receivers used for time-division multiplexed (TDM) communication or communication with time-division multiplexed access (TDMA) include e.g. the receiver discussed by Yamamoto and Kato in "TDMA Communications", The Institute of Electronics, Information and Communication Engineers (1989).

It is an object of the present invention to produce an adaptable data equalizer which is designed so that even when the received signal has a frequency shift, the deterioration of the equalization properties due to this frequency shift will be reduced to a minimum.

The invention thus relates to an adaptable data equalizer with a transversal filter, a decision part, an updating part for updating the transversal filter's tapping coefficients in accordance with an updating algorithm for such coefficients, and a memory arranged in front of the transversal filter and arranged to store a received signal.

On this background of principally known technique, in particular from the article "Design of an Adaptive Kalman Equalizer and Its Performance Over Fading Multipath Channels" by

K. Murakami et al. on pages 564 - 570 of the publication from the "40th IEEE Vehicular Technology Conference", May 6 - 9, 1990, Orlando, U.S.A., the adaptive data equalizer according to the invention then has as a distinctive feature that it further comprises: - equipment for estimating for each signal burst a frequency shift direction by utilizing the inner product of the most recently updated tapping coefficients for a unique data word (UW) in

the received signal stored in the memory,

- detector equipment to detect a frequency shift direction by deriving the mean value of the estimated frequency shift directions, and - compensation equipment to thus compensate for the frequency shift in a certain small process step.

In the adaptive data equalizer according to the invention, a frequency shift direction in the received signal is thus estimated for each signal burst and the frequency shift directions that are estimated over several signal bursts are averaged to demonstrate the frequency shift direction for the received signal, so that the estimation accuracy is improved. By compensating for the frequency shift, data smoothing is then improved.

The above-mentioned and other purposes, advantages and distinctive features of the present invention will appear more clearly from the subsequent description of preferred embodiments seen in connection with the attached drawings, where the same reference numbers indicate corresponding elements, and in which: Fig. 1 is a block diagram which shows an embodiment of the adaptive data equalizer i

according to the present invention,

fig. 2 is a flow chart showing the operation of the adaptive data equalizer shown

in fig. 1,

fig. 3 is a block diagram of a conventional feedback adjustable data equalizer

decision function,

fig. 4 shows an example of the signal burst format used in mobile communication, fig. 5 shows an example of equipment for coding a transmission data sequence based on

7i/4 shifted QPSK modulation,

fig. 6 is a table showing the phase change introduced by equations 13a and 13b in the equipment for differential coding of a transmission data sequence, as shown in fig. 5, Fig. 7 is a table indicating the result of differential coding of a transmission data sequence by means of the means shown in Fig. 5 and 6, and Fig. 8 illustrates a hard decision method that is utilized in a decision circuit for an adaptive data equalizer of the kind shown in Fig. 3, when the received signal is an rt/4 shifted QPSK modulation signal.

An embodiment of the present invention which corresponds to that shown in fig. 1, will now be described in more detail.

Fig. 1 is a block diagram showing a preferred embodiment of the adaptive data equalizer according to the present invention. In the figure, the same elements that are covered by prior art are indicated with the same reference number, and a detailed description of these has been omitted.

With reference to fig. 1, a memory 47 stores the received signal which is supplied to the adapted data equalizer. An address counter 48 generates addresses for writing and reading data to and from memory 47. A circuit 49 for estimating a frequency shift direction estimates a frequency shift direction for the received signal. A detector circuit 50 for indicating a frequency shift direction detects such a direction by taking the mean value of the values estimated by the circuit 49 for estimating the frequency shift direction. A frequency shift compensation circuit 51 compensates for a frequency shift of the received signal on the basis of the output from the detector circuit 50 for detecting the frequency shift direction. Reference numeral 52 denotes a complex multiplexer, 53 a COS/SIN generator which produces phase rotation data for the complex multiplexer 52, and 54 an address counter which provides the COS/SIN generator 53 with data to produce phase rotation data.

The operation of the adaptive data equalizer shown in FIG. 1, will now be explained below with reference to fig. 2 which is a flow chart showing the operation of the adaptive data equalizer shown in FIG. 1.

The compensation circuit 51 for frequency shift does not perform any frequency shift compensation, but emits the received signal as it is until a signal for compensation of a frequency shift is emitted from the detector circuit 50 for detection of frequency shift direction with respect to the received signal that runs in through the input port 7 for received signals.

The address counter 48 is reset by the start pulse which represents the beginning of the signal burst supply through the start pulse input port 20, and then generates addresses in synchronism with the incoming timing for the received signal which is supplied through the input port 7 for received signals and passes through the compensation circuit 51 for frequency shift.

The received signal emitted from the compensation circuit 51 for frequency shift is stored in the memory 47 in accordance with the output from the address counter 48.

After an input amount of data corresponding to a symbol at the beginning of the signal burst has been stored in the memory 47, the address counter 48 generates read addresses to cause data to be read out from the memory 47 and entered into the FF part 1, symbol by symbol .

The time interval during which data is read out from memory 47, symbol by symbol, is equal to or longer than the time interval during which the received signals are stored in memory 47, symbol by symbol.

For this input data, the data equalizer section comprising the FF part 1, the FB part 2, the adder 3, the decision circuit 4, the tap coefficient update circuit 34 and the switch circuit 6 updates the tap coefficients in the same way as when operating the normal adaptive data equalizer in learning mode (a), as explained in the section describing the operation of the conventional adaptive data equalizer implemented for QPSK modulation. After updating the tapping coefficients for the last UW data in the received signal, the updating circuit 34 sets the tapping coefficients for the FF and FB parts 1 and 2 to the last updated values, and further sends a signal of completion of learning to the address counter 48 .

On receipt of this signal, the address counter 48 brings the received signal data corresponding to UW 13 to be read out from the memory 38, to be sent again to the FF part 1, symbol by symbol. The data sequence which is supplied to the FB part 2 is at this point made up of the known learning sequence UW 13, which runs in through the input port 8 for the reference sequence.

The data entering the FF part 1 and the FB part 2 is subjected to a product/sum operation together with the determined tapping coefficients, and the result of this operation is then sent to the circuit 49 which is arranged to estimate the frequency shift direction.

This estimation circuit 49 for frequency shift direction derives a difference between the inner product obtained for each symbol and the value of UW 13, which is then known, to thereby calculate an error vector for each symbol, after which the thus obtained error vector values are summed.

If the received signal has a frequency shift, the result of the product/sum operation will be reflected on the error vectors, and it will therefore be possible to estimate the frequency shift direction (+ or -) of the received signal based on the sign of the result of the summation. The result of the direction estimate is sent to the compensation circuit 51 for frequency shift.

After the direction of the frequency shift has been estimated, the estimation circuit 49 for the frequency shift direction will send a signal to the address counter 48 that the direction of the frequency shift has been estimated. On receiving this signal, the address counter 48 causes the received signal data corresponding to the random data a 14, CC 15 and the random data b 16 to be read out from the memory 24, to be transmitted to the FF part 1, symbol by symbol.

The data equalizer section comprising the FF part 1, the FB part 2, the adder 3, the decision circuit 4, the update circuit 34 for tapping coefficients and the switch circuit 6 performs the data equalization of the above-mentioned data in order.

The frequency shift direction detector circuit 50 stores the result of the predicted frequency shift direction for each signal burst, and after the predicted results for a predetermined number of signal bursts have been stored, the circuit 50 calculates the proportion of frequency shift direction predicted results that show the same frequency shift direction for each predetermined number of signal bursts. If the calculated proportion exceeds a predetermined level, the frequency shift direction detector circuit 50 determines that there is a frequency shift in the relevant direction and emits a compensation signal for the frequency shift and the detected frequency shift direction to the frequency shift compensation circuit 51.

The compensation circuit 51 for frequency shift then performs a frequency shift compensation with regard to received signals, from the signal burst that follows the signal burst where the compensation signal for the frequency shift was emitted to the circuit.

The operation of the frequency shift compensation circuit 51 will be explained below.

After being reset by a start pulse representing the beginning of a signal burst through the start pulse input port 20, the address counter 54 outputs to the COS/SIN generator 53 an address for such phase shift data as produces a predetermined degree of frequency change in the direction for which the frequency offset is compensated, in accordance with the incoming timing for the received which is supplied through the input port 7 for received signals, from the signal burst that follows the signal burst whose compensation signal for the frequency shift is given to the circuit 51.

The complex multiplexer 52 then multiplies the received signal with fixed-turn data output from the COS/SIN generator 53 to give the received signal a phase shift of Af (Hz), thereby compensating for the frequency shift of the received signal fed to the adaptive data equalizer.

Claims (1)

Adaptive data equalizer with a transverse filter (1), a decision part (4), an updating part (34) for updating the tapping coefficients of the transverse filter in accordance with an updating algorithm for such coefficients, and a memory (47) arranged in front of the transverse filter (1) and arranged to store a received signal (7), characterized in that the data equalizer further comprises: - equipment (49) to estimate for each signal burst a frequency shift direction by utilizing the inner product of the most recently updated tapping coefficients for a unique data word (UW) in the received signal stored in the memory, - detector equipment (50) to detect a frequency shift direction by deriving the mean value of the estimated frequency shift directions, and - compensation equipment (51) to thus compensate for the frequency shift in a certain small process step.