NO20065466L - Apparat og fremgangsmate for a forbedre emuleringshastighet for hoynivasprak i emuleringssystemer pa brikker - Google Patents

Apparat og fremgangsmate for a forbedre emuleringshastighet for hoynivasprak i emuleringssystemer pa brikker

Info

Publication number
NO20065466L
NO20065466L NO20065466A NO20065466A NO20065466L NO 20065466 L NO20065466 L NO 20065466L NO 20065466 A NO20065466 A NO 20065466A NO 20065466 A NO20065466 A NO 20065466A NO 20065466 L NO20065466 L NO 20065466L
Authority
NO
Norway
Prior art keywords
debugging
emulation
combination
chips
module
Prior art date
Application number
NO20065466A
Other languages
English (en)
Inventor
Morten W Lund
Gaute Myklebust
Frank Langtind
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Publication of NO20065466L publication Critical patent/NO20065466L/no

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/36Preventing errors by testing or debugging software
    • G06F11/362Software debugging
    • G06F11/3648Software debugging using additional hardware

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

Fremgangsmåter og apparatur for å hoppe over og hoppe ut av funksjoner som en støter på ved programeksekvering på en målprosessor (120) under debuggingsoperasjoner er implementert innenfor en kombinasjon av en emulator (125) og en debuggingsmodul (140). Ved å ha en kommunikasjon og lagringsanordning (230, 235, 240, 255, 257, 260) tilgjengelig på debuggingsmodulen vil skritt og adressesammenligningsdetaljer bli gjennomført lokalt for prosessoren ved maskinvarehastigheter. Fremgangsmåten bestemmer korrekt nødvendige algoritmetrinn for å romme rekursive og nestede funksjons funksjonskall uten avbrudd ved en kombinasjon av vertsdebuggingsplattform og en debuggingsprogramvareapplikasjon. Dette forhindrer tidsmengden som ellers ville være nødvendig for å enklest kommunisere til debuggingsvertsnivået for å oppnå den samme prosessen. Overstyringsinstruksjoner (255) for målprosessoren kan bli innsatt og alternative minnelokasjoner kan hoppes til ved kontroll (245) av den samme debuggingsmodulen for derved å bruke maskinvareressursene på en effektiv måte.
NO20065466A 2004-04-29 2006-11-29 Apparat og fremgangsmate for a forbedre emuleringshastighet for hoynivasprak i emuleringssystemer pa brikker NO20065466L (no)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/837,483 US20050268195A1 (en) 2004-04-29 2004-04-29 Apparatus and method for improving emulation speed of high-level languages in on-chip emulation systems
PCT/US2005/014140 WO2005111801A2 (en) 2004-04-29 2005-04-26 Apparatus and method for improving emulation speed of high-level languages in on-chip emulation systems

Publications (1)

Publication Number Publication Date
NO20065466L true NO20065466L (no) 2007-01-29

Family

ID=35394794

Family Applications (1)

Application Number Title Priority Date Filing Date
NO20065466A NO20065466L (no) 2004-04-29 2006-11-29 Apparat og fremgangsmate for a forbedre emuleringshastighet for hoynivasprak i emuleringssystemer pa brikker

Country Status (6)

Country Link
US (1) US20050268195A1 (no)
EP (1) EP1743243A2 (no)
CN (2) CN100555218C (no)
NO (1) NO20065466L (no)
TW (1) TW200620114A (no)
WO (1) WO2005111801A2 (no)

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CN108267968B (zh) * 2017-01-03 2021-02-05 北京机电工程研究所 一种协同半实物仿真光纤数据交互安全性校验方法
CN106682370B (zh) * 2017-02-28 2020-07-28 苏州浪潮智能科技有限公司 一种仿真验证系统
US10395722B2 (en) * 2017-09-29 2019-08-27 Intel Corporation Reading from a mode register having different read and write timing
KR102467842B1 (ko) * 2017-10-13 2022-11-16 삼성전자주식회사 인스트럭션을 실행하는 코어 및 그것을 포함하는 시스템
CN108958801B (zh) 2017-10-30 2021-06-25 上海寒武纪信息科技有限公司 神经网络处理器及使用处理器执行向量最大值指令的方法
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CN111984521B (zh) * 2019-05-23 2022-11-29 核工业理化工程研究院 一种无需jtag介入的板级调试方法
US11537505B2 (en) * 2020-10-16 2022-12-27 Cadence Design Systems, Inc. Forced debug mode entry
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CN112199298B (zh) * 2020-11-02 2022-05-13 杭州安恒信息技术股份有限公司 一种单步调试的检测方法、装置和计算机可读存储介质
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Also Published As

Publication number Publication date
WO2005111801A2 (en) 2005-11-24
EP1743243A2 (en) 2007-01-17
WO2005111801A3 (en) 2007-08-09
US20050268195A1 (en) 2005-12-01
CN101084485A (zh) 2007-12-05
TW200620114A (en) 2006-06-16
CN101667154A (zh) 2010-03-10
CN100555218C (zh) 2009-10-28

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