NO146037B - SHAFT POSITION CONVERTER. - Google Patents

Description

The invention relates to an axle position converter with

a first code disc which is arranged on a first rotatable shaft, a second code disc which is arranged on a second rotatable shaft/electric sensing devices for sensing the disk's code indications, and a signal processing device which processes the sensing signals from the electrical sensing devices and brings them to indication, the first and the second rotatable shaft are connected to each other via a coupling. When it has previously been desirable to produce a signal representing the angular position of a shaft which rotates a number of times, it has been common to achieve high resolution and a large area to use a reduction gear with two rotatable position converters. One transducer is driven directly by the shaft to provide accurate resolution signals. The second converter is driven by the reduction gear and supplies the range signals. Previous devices of this nature have required great precision

and costly reduction exchange.

A device to reduce the requirements for a compli-

sert reduction gearing in connection with two rotatable position converters is described in U.S. Patent No.

2,944,159. This simplified exchange is used in U.S. Patent No. 3,885,209 in combination with two synchronous generators electrically cascaded to provide analog position signals. When the synchronous generators are used and a digital output signal representing the position of a shaft is desired, an analog-to-digital converter is required. The conversion to digital signals is difficult if both high resolution and a wide area are required by analogue equipment and

such equipment becomes expensive.

From DOS No. 2,553,815, an axle position converter with a rotatable axle and a first and a second code-

disk that turns in dependence on the shaft, each code disk being assigned a sensing device to determine the code

characters on the relevant code disc. By this well-known construc-

tion, however, the first and second code discs are not arranged on the shaft in such a way that the first code disc performs a first

number of revolutions while the other code disc performs a deviation

end number of revolutions. In other words, by this is known

construction the two code disks are not firmly connected to each other, but the connection only takes place on a small circumferential section of one of the two code disks. In one embodiment of the known construction, a sleeve is rotatably arranged on a fixed shaft, one end of which is equipped with a gear wheel whose teeth engage with teeth in a higher-order encoder disk and whose other end is equipped with a gear wheel which, when the gear wheel lies against the smooth circumference of the lower-order code disc, is arrested, i.e. the higher-order code disc in this state cannot turn or move with the disc. If a drive member comes into contact with the said gear wheel, the detent is canceled and a tooth on the gear wheel can engage in a tooth opening arranged in the drive member, so that this drives the gear wheel on its upper part sufficiently far.

From U.S. Patent No. 3,660,830, a digital coding device is known for a variable input quantity which is reproduced by turning a shaft and has two coding disks which are equipped with segment-shaped coding characters which are sensed by sensing devices. One of the two code discs is driven at a relatively low speed, while the other via a gear is driven at a lower speed, e.g. in the ratio 4:1. By comparison, this design requires an additional exchange device.

From German patent document No. 1,926,628, a device is known for producing a revolution-proportional direct voltage by means of an n-phase alternating voltage machine with a rotating inductor and a co-rotating operating element for a stator-fixed encoder which is in operative connection with electrical switches for cyclic forwarding of unipolar phase voltages to a common output line. The essential feature of this known device is that a disk with a multi-track code pattern is used as an operating element, and that each code track is scanned by a sensor. The code pattern can e.g. have four concentric code tracks, according to the Gray code, each of which is assigned to a fixed donor. The sensors' outputs deliver signals that can distinguish between 16 separate rotor positions.

Finally, from DAS No. 1,298,545, an electromechanical analog-digital converter with a planetary drive arranged between code discs and a tow contact adjustment set is known. The converter has a rotatable input shaft and two code discs that interact with a towing contact set rotating in a specific ratio of revolutions. One code disc rotates with the input shaft and the other is arranged on an output shaft arranged coaxially with the input shaft and connected to this via the planetary drive. planetclrev-

It is designed as an epicyclic drive and the output shaft is designed as a hollow shaft on the input shaft. This converter is comparatively very complicated and not suitable for high resolution.

The purpose of the invention is to provide an axle position converter of the type mentioned at the outset which is simple in structure and which unambiguously enables the angular position of one of the code discs to be determined extremely precisely.

This is achieved according to the invention by the combination of the following features: a) the first shaft is continuously connected to the second shaft in such a way that for a whole number of revolutions of the first shaft, the second shaft is turned a number of revolutions that differ only slightly from the first shaft revolutions,

b) the signal processing device processes the sensing signals from the electrical sensing devices in such a way that the indication

is a function of the difference between the angular position of the two code discs.

Further features of the invention will appear from claims 2-5.

The invention will be explained in more detail below with reference to the drawings. Fig. 1 shows a side view of some mechanical elements in the device according to the invention. Fig. 2 shows a block diagram of an embodiment of the apparatus according to the invention. Fig. 3 and 4 together show circuit elements that are used in the device in fig. 2. Fig. 5 shows a block diagram for another embodiment of an apparatus according to the invention. Fig. 6 shows circuit elements that are used in the device in fig. 5. Fig. 7 shows a block diagram for a third embodiment of an apparatus according to the invention. Fig. 8A and 8B show circuit elements used in the apparatus of fig. 7. Fig. 1 shows an input shaft 101 which is provided with a first gear 10 2 and a rotatable position converter 103. In engagement with the gear 102 is a second gear 104 which, together with a second rotating position converter 105, is arranged on a second shaft 106.

In the first of the three embodiments to be described here, the converters 103 and 105 are digital encoders which each provide for each revolution of the converter 2048 separate output signals each consisting of 11 signal bits. In this first embodiment, the first gear wheel 102 has one tooth less than the second gear wheel 104, namely 255 teeth or 256.

In the other two embodiments, the converters 103 and 105 are rotatable signal generators. Here, the first converter 103 supplies 1024 periods of an electrical signal in each of two channels during each revolution. In addition, an index signal is supplied which will be described in more detail below with reference to each of the two designs. The second converter 105 only supplies index signals as will be described in more detail below. In these embodiments, the first gear wheel 102 has one tooth less than the second gear wheel 104, namely 156 teeth or 257 teeth.

Fig. 2 shows the resolution part and the area part in the apparatus according to the first embodiment. In respective references to the various input and output lines connecting the blocks of fig. 2 corresponds to the circuit elements in fig. 3 and 4.

The resolution part in this apparatus comprises a first register AREG which receives output signal bits from a first coder which delivers than 11 bits of gray code on the lines EAO-EAlO and the output of the register is connected to the input of a gray code - binary converter ACON which delivers binary coded output signals. These signals are fed to gate circuits GAA and a selector SWA whose function will be explained in more detail below. The output signals from the converter ACON are also supplied to a storage register 1ST0.

The area part in the embodiment in fig. 2 comprises a selector SWB which receives the 11 bit gray coded output signals from a second encoder. These signals are supplied on lines EB0 to EB10. The selector SWB also receives input signals on wires SO to S10 from a circuit to be described in more detail below.

The output of the selector SWB is connected to a register BREG whose output is in turn connected to the gray code binary converter BCON.

The output of the converter <B>C0N, the gate circuits GAA

and the selector SWA is supplied to a subtraction circuit SUBT which supplies signals representing the number of revolutions of the shaft 101. These signals are supplied to a second storage device 2ST0 and the inverter SWB. A timing device TSIG delivers timing pulses on the lines CLOA, MA, MB and CLOB.

Fig. 3 shows that the register AREG comprises 11 flip-flop circuits which each receive a time control pulse from the time control device TSIG on the line CLOB. When a timing pulse occurs on the line CLOB, each of these flip-flop circuits can deliver an output signal on the respective output lines AGO-AG10 in accordance with the input signal on the respective input lines EA0-EA10. Two of these flip-flop circuits which receive the input signal on wires EA3 and EA10 provide a second output signal on wires ~KU~ 5 and AG10 which is inverse to the output signals on wires AG3 and AG10. The inverted output signal AG3 together with the first output signal on the lines AG0-AG2 and AG4 to AG10 are supplied to 10 NOR gate circuits which form the gray code binary converter ACON.

The outputs from the converter ACON on the lines CAO - CA3 are the inverted four least significant bits of each binary coded number corresponding to each gray code number supplied to the register AREG on the lines EAO - EA10. The seven most significant bits in the binary coded numbers correspond to the gray code numbers that are supplied to the register AREG on lines AG10 and CA9 to CA4. The signals on the lines CA8 and CA9 are supplied to the inputs inverters 18 and 19 which supply output signals on the lines CA8 and CA9.

The selector SWA comprises a 4-bit AND/OR selector which receives the inverted four least significant bits in each binary number on lines CA0-CA3 together with the signals on lines AG10, CA9, CA8 and E1+. The signal on wire E1+ is a constant positive DC voltage equivalent to the voltage representing binary "1" in the apparatus and is derived from any suitable source (not shown). The inverter SWA produces output signals on the wires A0-A3 corresponding to the input signals on the wires CA'0-CA3 or the wires E1 + , AG10, CA9 and CA8 depending on whether a pulse is applied to the inverter on the wire MA or MB.

The gate circuits GA comprise 7 NAND gate circuits which

on wires CA4-CA9 and AG10 receive input signals and deliver signals on wires A4~-A10 when a pulse occurs on wire MA. The signals on the wires CAO - CA3, CA4-CA9

and AG10 is also supplied to a first storage device 1ST0 containing 11 flip-flop circuits. Upon receipt of a timing pulse on line CLOB, each of these flip-flop circuits provides an output signal on lines R0-R10 in accordance with the supplied input signal.

The timing control signal generator TSIG in fig. 3 comprises 2NAND gate circuits NI and N2 which together with resistors RI and R2 and the capacitor Cl form a free-running multivibrator which

22

delivers pulses with a frequency of 2 : Hz. These pulses are supplied

100

of a flip-flop circuit Dl and NAND gate circuits N3 and N4 to supply pulses on lines MA, Mb, CLOA and CLOB. As shown in the timing diagram next to the generator TSIG, the pulses on the wire CLOA have a frequency corresponding to the free-running multivibrator with a pulse width equal to half a period. This frequency is chosen because it is fast enough that at least four complete periods are delivered on line CLOA during each output signal from converter 101 on lines EAO-

EA10 at the inverter's highest rational speed. The pulses

on wires MA and MB are complementary and have a frequency half that of the free-running multivibrator and a pulse width of half a period. The pulses on the line CLOB also have a frequency equal to half that of the free-running multivibrator but a pulse width equal to 3/4 of a period.

Fig. 4 shows the area part in the apparatus according to the first embodiment. The selector SWB comprises three 4-bit AND/OR selectors which receive signals in gray code from the other 11-bit encoder via wires EBO-EB10. It also receives the input signal on wires S1-S10 and delivers output signals on wires BGO-BG10 corresponding to one or the other set of input signals depending on whether a pulse is supplied to the selector via wire MB or MA.

The output signals from the inverter SWB on the lines BGO-BG10 are supplied to registers BREG comprising 11 flip-flop circuits which supply output signals on the lines SBO-SB10 in accordance with the input signals they receive on the lines BG0-BG10 when the timing pulses appear on the line CLOA.

The output signals from the register BREG on the lines SBO-SB10 are fed to one set of inputs in the converter BCON.

This comprises three 4-bit AND/OR selectors and serves two

functions. When signals appear on the lines E1+ and MA, it transforms the signals on the lines SBO-SB10 that are supplied to one set of inputs from gray code to equivalent binary code and delivers binary coded signals on the output lines BO-B10.

During this half period of the signal appearing on the wire MA. when no pulse is present, the inverter BCON works i

match the voltage applied constantly on the wire E1+

which selects and transmits the input signals supplied from the lines SBO-SBIO to the output lines BO-B10.

The output signals from the converter BCON on the lines BO-B10 are supplied to one set of inputs in the subtraction circuit SUBT which comprises three 4-bit summing circuits. As previously mentioned, the second set of inputs of the subtraction circuit SUBT receives the signals on the lines AO-A10 via the inverter SWA and the gate circuits GAA from the resolving part of the apparatus. When no pulses from line MB occur at the input of the subtraction circuit SUBT, this supplies signals on the output lines S0-

S10 which represents the sum of the input signals on the two

set inputs. During half of each period of the signals applied on line MB when a pulse occurs, the subtraction circuit SUBT supplies signals on the output lines representing the sum of the input signals on the two sets of inputs

times plus a binary pulse that indicated with the pulse on led-

the MB. The summing inputs KOI and K02 in the first two summing stages are connected to the summing inputs KI2 and KI3 in the second and third summing stages as shown.

The eight most important output signals from the subtraction circuit SUBT are fed via lines S3-S1.0 to the second register 2ST0. As previously mentioned, all the output signals from the subtraction circuit SUBT are supplied to the selector SWB. The other

register 2ST0 comprises eight flip-flop circuits each operating in accordance with a received pulse via line CLOB for over-

routing the signals on wires S3-S10 to wires R11-R18.

As shown in fig. 5, two signal generators PG1 and PG2 are used in the second embodiment, which correspond to the converters 103 and 105. The signal generator PG1 produces equal pulse signals in two channels. The signal in one channel is supplied via output line X and the signal in the other channel along output line Y. Depending on the direction of rotation, the signal on line Y is either in front or behind..the signal on line X is 90° or 1/4 period. As mentioned earlier, 1024 periods of each signal occur on each wire X and Y for each revolution of the signal generator PG1. In addition to this, the signal generator PG1 supplies a first index pulse on the line IMI every time the first reference point on the shaft 101 is in a first angular position.

The output signals from the signal generator PG1 on lines X and Y are supplied to the signal processing circuit C0ND1 which supplies signals on lines UD, 4DN and 4U which cause counting in both directions of the counter CN1 to supply the output signal on lines PP0-PP11 representing the angular position of the first reference point on the shaft 101 .

The counter CN1 also supplies a signal on the wire

CO when it is reset to the initial position as a result of

that it receives a predetermined number of signals from C0ND1 sufficient to fill the counter. The signal on line CO is fed to counter CN2 and causes it to deliver

signals on the wires PP12-PP19 which represent the number of times the first reference point on the axis 101 has passed the previously mentioned first angular position.

The signal generator PG2 delivers a second index pulse

on wire IM2 every time the second reference point on

shaft 106 passes a second angular position. A pulse signal on the line IM2 which is supplied to the counter CN2 causes it to deliver signals which it receives on the lines PP4-PP11 from the counter CN1 to the lines PP12-PP19 so that if signals corresponding to each other do not already appear on the latter lines, then they will appear then.

Fig. 6 shows the signal processing circuit C0ND1 and the counters CN1 and CN2 in fig. 5- The signal processing circuit comprises an oscillator OSC which supplies pulses on the line CLO

and complementary pulses on the line CLO with a frequency of 122.9. kHz with a pulse width of half a period. The signal processing circuit also comprises a number of flip-flop circuits which receive signals from the signal generator PGN on the lines X and Y.

These flip-flop circuits are used to produce the signal

on lines XI and X2 and Yl and Y2 in accordance with the signals appearing on lines X and Y. The signal on lines XI, X2, Yl and Y2 is applied to three NOR gate circuits NOI, N02 and

N03 whose output signals are supplied to a binary coded decimal-

decodes BCD. The decoder BCD together with a pair of NOR and inverter gate circuits Ul, U2, Dl and D2 supply signals on the lines 4U, 4DN and 4DN. Depending on the direction of rotation, four pulses are produced on lines 4U or 4DN for each period of the signal on lines X and Y from the generator PG1. The signals on wire 4DN are complementary to the signals on wire 4DN. The signals on wires 4U and 4DN in conjunction with 2N0R gate circuits NAI and NA2 supply signals on the wire

OUT.

The counter CN1 which counts in both directions includes

three 4-bit binary up and down counters BC1, BC2 and BC3 which are connected in series The counter CN2 comprises two such 4-bit binary up-down counters BC4 and BC5. Each of the four wires P1-P4 from the counters BC1 - BC3 is connected to earth potential ...' and their signals are supplied to the output wires from the counter CN1 when a signal is supplied to the respective counter on the wire IMI.

The eight most important output lines PP4-PP11 from the counter TN1 are shown connected to the data lines P1-P4 in each of

the counters BC4-BC5 which contain the counter CN2 which counts in both directions. The signals on the latter wires to-

the output wires from the counter CN2 are fed when a signal, to-

is fed to the counter on line IM2. The counters.BC1-BC5 are also-^series connected.

Fig. 7 shows another external form of up-

the invention. Here, signal generators PG3 and PG4 are used

which corresponds to converters 103 and 105. The signal generator PG3

supplies output signals on two channels as X3 and Y3. These signals are similar to the signals on wire X and Y from the pulse gene-

the rotor PG1 which is described in connection with fig. g. In to-

add, the signal generator PG3 supplies an index signal on the line IM3 which switches from a first level to a second level each time

the first reference point on the shaft 101 is in the first angular position and switches from the second level to the first level every time the first reference point on the shaft

101 has turned 180° from the first angular position. This index signal is supplied on line IM3 to the signal processing circuit C0ND2 together with the signals appearing on lines X3 and Y3.

The signal generator PG4 supplies an index signal on the wire IM4 which switches from a first level to a second level every time the second reference point on the shaft 106 is in the second angular position and switches from the second level to the first level every time the second reference point on the shaft 106 is turned 180° from the second angular position. This index signal is supplied via line IM4 to the signal processing circuit C0ND2.

The output signals from the signal generator PG3 on the lines X3, Y3 and IM 3, and the output signals from the signal generator PG4 on the line IM4 are fed to the signal processing circuit C0ND2 which supplies signals on the lines 3011, IM3BSTB, UIO and 4XUD to the counter CN3 which counts in both directions. In addition to this, the signal processing circuit C0ND2 supplies signals which are supplied via the lines BE, BE and IM4BSTB to gate circuits X0R8 and N0G4 and to the counter CN4 which counts in both directions. The signal on the line UIO is also supplied to the counter CN4.

The output signals from the counter CN3 representing the angular position of the first reference point on the shaft 101 are supplied to the lines 3PO-3P11. The counter CN3 also supplies a sum signal which is supplied via the line CO30 to the counter CN4 when the counter CN4 is reset to the initial position by receiving a predetermined number of pulses. This reset takes place in the same way as previously described for the counter CN1 in fig. 5 and 6. The signal on wire 3PH is also supplied to gate circuit N0G4 and cooperates with the signal on wire BE to deliver an output signal from gate circuit N0G4 which is supplied via wire C040 to summing device ADD1. The adding device ADD1 supplies signals on the lines 4P4-4P10 to the counter CN4. In addition to this, the summing device ADD1 supplies a signal which is supplied via line 4P11A to gate circuit X0R8. The gate circuit X0R8 supplies, in accordance with these signals on the lines 4P11A and BE, an output signal which is fed to the counter CN4 via the line 4P11.

The counter CN4 responds to the sum signals supplied on line C030 and supplies output signals on lines 3P12-3P19 which represent the number of received sum signals. Moreover, the signal supplied to the counter CN4 on the line IM4BSTB causes the supply of signals received ai' on the lines 4P4-4P11 from the summing device ADD1 and the gate circuit XC-R8, to the lines 3P12-3P19 so that if corresponding signals do not already appear on the latter lines they perform then.

Fig. 8A shows the elements of the signal processing circuit C0ND2. This contains a number of buffer amplifiers Bl, B2, B3, BH which receive signals from the pulse generators PG3 and PG4

via wires X3> Y3, IM3 and IM4. The amplifiers Bl and B2 supply a pulse on the wire X3B or Y3B for each period of the signal on wires X3 and Y3. The amplifiers B3 and B4 deliver a pulse on the wires IM3B and IM4B for each signal on the wires IM3 and IM4. The signal processing circuit contains a number of 4-bit registers DIC1 and DIC2 which supply signals on lines X3B1, X3B2, Y3B1, Y3B2 and lines IM3B1, IM3B2, IM4B1, IM4B2 as a result of signals on lines X3B, Y3B, IM3B, IM4B.

As shown in fig. 8A and 8B, a number of NOR gate circuits X0R1-X0R8, a number of NAND gate circuits NND2-NND3, a number of NOR gate circuits N0G1-N0G4 and inverting amplifiers IA3-IA5 are arranged.

The signals on the wires IM3B1 and IM3B2 from the register DIC1 are fed to the gate circuit X0R1 whose output signal is fed to the counters BUD1-BUD3.

Oscillator 0SC2 is free-running and delivers pulses with a frequency of 131 kHz which are applied to lines CL01 and CL01. The pulses on wire CL01 are complementary to the pulses on wire CL01. The wire CL01 is connected to the counters BUD1-BUD5. Line CL01 is connected to registers DIC1. At least four pulses are produced on the line CL01 during each quarter period of the signal on the lines X3 and Y3 at the greatest speed of the signal generator PG3 to produce four pulses as a result of each period as will be described in more detail below.

As also shown in fig. 8A supplies the NOR gate circuit X0R3 which receives signals on lines X3B1 and Y3B2 from the register DIC1, signals which are applied to input B of the binary coded decimal decoder BCD3. This also receives signals on inputs A and C via wires Y3B1 and X3B2 from register DIC1. The signals on wires 1 and 4 from the decoder BCD3 are fed to the input of the NOR gate circuit N0G1 and the signals from wires 2 and 7 from the decoder BCD3 are fed to the input of the NOR gate circuit N0G2. The signals from the NOR gate circuits N0G1 and N0G2 are supplied via the lines 4XU and 4XD to the inverting amplifiers IA3 and IA4 which deliver signals on the lines 4XU and 4XD which are multiplied four times in relation to the signals on the lines X3B and Y3B. The signal on the wire 4xU is also supplied to an input of the NAND gate circuit NND2 whose second input is connected to the wire D10 to supply a binary signal which via the wire UIO is supplied to the counters CN3 and CN4. Similarly, the NAND gate circuit NND3 receives signals via lines 4XD and UIO and supplies signals on line D10.

The NOR gate circuit N0G3 combines the signals supplied on lines 4XU and 4XD and delivers signals via line 4XUD to the input of the first of three binary up-down counters BUD1, BUD2 and BUD3 containing the counter CN3. The NOR gate circuit X0R5 receives signals on the lines IM3B2 and D10 and produces a signal which is applied to one input of the 'NOR gate circuit X0R6 whose other input is connected to ground.

The NOR gate circuit X0R6 is connected with the output line 3QH to the counter CN3. The remaining input wires 3Q.0-3Q10

in the counter CN3 each is connected to ground.

The counter CN3 is connected in series with the counter CN4, which comprises a pair of series-connected up/down counters BUD4 ob BUD5, by means of the line C030. In addition to supplying signals on the lines 3PO-3PH representing the angular position of the first reference point on the shaft 101, the counter CN3 supplies the eight most significant bits via the lines 3P4-3PH to the binary adder ADD1.

The binary adder ADD1 comprises two series-connected 4-bit adders ADDA and ADDB.

Looking shown in fig. 8B, the inputs A1-A8 of the summing device ADD1 are connected to ground. The adding device ADD1 is supplied with a summing signal on line C040 from the output of the NOR gate circuit N0G4. Gate circuit N0G4 receives signals from wires 3PH and BE. The signal on wire BE is provided by the inverter IA5 and is complementary to the signal produced by the NOR gate circuit X0R7 as a result of the signals supplied to the gate circuit via wires IM4B2 and D10.

As a result of a pulse signal being supplied to the counter CN4 via the line IM4BSTB, the counter delivers the signals it receives on the lines 4P4-4P11 to the lines 3P12-3P19 if corresponding signals do not already appear on these lines. The signal on wire 4P11 which is supplied by the NOR gate circuit X0R8 in accordance with the signals supplied to it. the wire BE and 4P11A and the remaining signals on the wires 4PO-4P10 on directly from the summing circuit ADD1 in binary form the number of revolutions of the first reference point on the shaft 101.

The operation of the described embodiments of the device according to the invention follows below. It is assumed that the first and second reference points on the shafts 101 and 106 are calculated for the first design example according to fig. 2.3

and 4 and have a first and a second angular position, binary encoders corresponding to converters 103 and 105 delivering output signals in gray code equivalent to zero. From the foregoing it appears that the encoder on the shaft 101 delivers 2048 separate 11-bit signals for each revolution of the associated gear 102 with 255 teeth or 360°. The encoder on the shaft 106 also provides 2048 separate output signals for each revolution of its gear 104 or 360°. However, this gear has 256 teeth and for each revolution, of the gear 102 with its 255 teeth, the gear 104 will rotate 255 teeth, i.e. one less than 360° for the gear 104. As a result, the encoder on the shaft 106 will deliver eight fewer output signals than the encoder on the shaft 101 for each revolution of its shaft.

From the foregoing it also appears that because of the separated characters in the output signals from the encoders on the shafts 101 and 106, the signals from the encoders will be out of synchronism with each other with the exception of each time the first reference point on the shaft 101 is in its first angular position. This synchronism between the signals from the encoders is compensated for so that the correct indication of the angular position of the reference point on the shaft 101 will occur at each position of the shaft in each of its revolutions. The explanation of the operation is based on a specific position of the shaft 101 in order to show how an accurate indication of the angular position of the first reference point on the shaft 101 occurs.

As the gear 104 moves one tooth less than the gear 102 for each revolution of the gear 102, it is clear that with each subsequent revolution of the shaft 101 the angular position of the second reference point on the shaft 106 will decrease progressively in relation to the angular position of the first reference point on the shaft 101 if the rotation of the shafts starts with the first and second reference points in the first and second angular positions respectively. This sag angle increases to the same extent for each revolution and thereby indicates the number of revolutions of the shaft 101.

In the embodiment in fig. 3 and 4, the angular position of the first reference point on the shaft 101 is indicated by assuming that the shafts 101 and 106 start their rotation with the first and second reference points in the first resp. second angular position. It is further assumed that the shaft 101 is in a certain revolution and that the first reference point has moved more than 7/8 of a rotation from the first angular position.

Under these conditions, the signals on the wires EAO-EA10 are supplied to the register AREG which indicates in gray code the angular position of the first reference point on the shaft 101

in this particular revolution. At the same time, the signals supplied to the wires EBO-EB10 will be selected by the selector SWB which indicates in gray code the position of the second reference point on the shaft 106.

It is also assumed that the time signal generator TSIG has delivered a new pulse on line CLOA and that the corresponding pulse on line MA has not yet been delivered. As. as a result, a pulse still occurs on the line MB and the selector SWB is supplied with signals via the lines EB0 - EB10 to the lines BGO-BG10. When a pulse occurs on the line CLOA and the flip-flop circuits in the register BREG as a result of the signals on the lines BGO-BG10, signals indicating the angular position of the first reference point on the shaft 106 will appear on the lines SBO-SB10 and are supplied to a set of inputs in the graycode-to-binary encoder BCON. Consequently, when sufficient time has elapsed for the time signal generator TSIG to deliver a pulse on the line MA, the converter BCON will deliver signals on the lines BO-B10 in binary code indicating the angular position of the second reference point on the shaft 106.

After the delivery of the pulse on line MA, the timing signal generator TSIG will also deliver a pulse on line CLOB. As a result, the flip-flop circuits in the register AREG will cause the .11-bit gray code signal to be supplied to them via the lines EAO-EA10 for supply to the lines AGO-AG10. In addition to this, the complementary signals to the signals on the wires EA3 and EA10 will appear on the wires AG3 and AG10. The three least significant bits of the signal in the gray code indicate the angular position of the first reference point on the shaft 101 and are supplied via the wires AG0-AG2 to the gray code- the binary encoder ACON These signal bits together with the complement of the four least significant bits are supplied via wire AG3

to the converter ACON for on the lines CÅ0-CA3 and deliver the complement of the four least significant bits in the binary code corresponding to the four least significant bits in the gray code. The seven most important gray code bits supplied by the encoder on the shaft 101 are supplied via the lines AG^-ApiO to the converter ACON for on the lines CA4-CA9 and supply the five to ten most important bits in the binary code corresponding to the bits in the gray code which indicate the position signal . The 11th or most significant bit does not need to be converted from gray code to binary code because it is always the same in both cases. This most significant bit on wire AG10 together with the next six most significant bits on wires CA4-CA9 are supplied to gate circuits GAA which, in the presence of a pulse on wire MA on wires AT-AlO, deliver the complement of the seven most significant bits of the signals in binary code which indicates the position of the first reference point on the shaft 101.

At the same time, the signals on the wires CAO-CÅ3 supply to the selector SWA which when no pulse appears on the wire MB

and a pulse appears on the wire MA transmits these four signals indicating the complement of the four least important

bits in the binary coded signal indicating the position of the first reference point on the shaft 101 of the output

nings A0-A3.

The complements of the 11 binary coded signal bits

which indicates the position of the first reference point on the shaft 101 is supplied via the lines AO-A10 to the second set of inputs in the subtraction circuit SUBT. As previously mentioned, the subtraction circuit SUBT at the same time also receives binary coded signals from the lines BO-B10 on the second set of inputs. These signals indicate the angular position of the second reference point on the shaft 106. If a pulse on the line MB is missing, the subtraction circuit SUBT works as a summing circuit and adds the signals on the line BO-B10 to the signals on the lines AO-A10. The signals on wires AO-A10 are the complements of the binary signals representing the angular position of the first reference point on shaft 101. Accordingly, the subtraction circuit SUBT on wires SO-S10 will provide binary signals indicating the difference between the signals representing the angular position of the second reference point on shaft 106 and the signals representing the angular position of the first reference point on the axis 101, or the angle by which the angular position of the second reference point on the axis 106 lags with respect to the first reference point

the axle 101.

With the shaft 101 in the last eighth of any rotation as mentioned above, synchronism between the signals from the two encoders causes the differential signals on the wires S0-S10 to indicate an incorrect number of revolutions of the shaft 101. This happens because in this position when the encoder on the shaft 101 delivers a signal before the generation of the corresponding sig-

nal from the encoder on the shaft 106, the latter encoder will have delivered eight more signals by this rotation of the shaft 101

than the latter codes. From the preceding explanation, it appears that the eight signals are equivalent to one tooth on the toothed wheel 104. Accordingly, these eight signals indicate that the second reference point on the shaft 106 sags in relation to the first reference point on the shaft 101 by an angle equal to a second full revolution. As this happens before the rotation is complete, it must be prevented that the difference between the two signals

which is supplied to the subtraction circuit SUBT, gives incorrect indi-

kering the number of revolutions of the first reference point on the shaft 101 beyond the first angular position. The selector SWB, the register BREG, the converter BCON, the subtraction circuit

SUBT and the selector SWA then work as a compensation circuit

during the presence of the pulses on the line MB so that the correct indication is given in this time period.

To achieve this compensation, the starting sig-

the nals from the subtraction circuit SUBT on wires SO-S10 to-

led the second set of inputs in the selector SWB. Before the reception of a pulse on the wire MB and while a pulse appears on the led-

ning MA, has the output wires BGO-BG10 from the selector SWB

supplied these sag angle signals from the subtraction circuit SUBT. When a pulse is produced, on the wire CLOA at the end

of the pulse on line MA, the 11 flip-flop circuits in register BREG produce the complements of the sag angle signals applied to lines SBO-SB10. These sig-

nals are supplied to the converter BCON which, when no signal appears on the line MA, works as a selector and transfers these complementary signals to the lines BO-B10.

When the pulse on line MA is gone and the pulse on line MB has begun, gate circuit GAA is blocked and thus a binary "1" is applied to each of lines AT-A10. In addition, in accordance with the pulse on wire MB, the selector SWA will select the input signals on wires E1+, AG10, CA9 and CA8 and over-

lead these signals to the output wires A0-A3. The signals on wires CA8, CA9 and AG10 represent the complement of the three most significant bits of the binary number indicating the position of the first reference point on the shaft 101. During each revolution of the shaft 101 when its first reference point passes a final 1/8 of the rotation towards the first angular position, the signals representing these three most important bits comprise a compensating signal of sufficient amplitude that when subtracted from the sag angle signal produced during the pulse MA prevents asynchrony between the generation of the signals from the two encoders and produces a sag angle-

signal that gives an incorrect indication of the position. This subtraction is achieved by the binary signals on the wires A10-A"4~

and on wire A3 which is due to binary "l" signal on the wire

E1+ together with the signals on the wires A0-A2 indicating the complement of the three most significant bits in the binary coded signal representing the position of the first reference point of the associated set of inputs in the subtraction circuit SUBT. With these signals on one set of inputs and the complement of the sag angle signal supplied to the other set of inputs via wires BO-B10, the subtraction circuit SUBT will, in the presence of a pulse on wire MG, deliver the difference between the sag angle signal on wires SO-SIO. The eight most important bits on lines S3-S10 are supplied to the eight flip-f]op circuits in register 2ST0. On the next generation of the pulse on the line CLOB, these will result in output signals on the lines R11-R18 which accurately indicate the number of teeth on the gear wheel 104 by which the angular position of the second reference point on the shaft 106 lags behind the angular position of the first reference point on the shaft 101. As previously mentioned, this number of revolutions of the first reference point on the shaft 101 indicates that the first angular position has been passed because the assumed starting position in which the first reference point and the second reference point appeared simultaneously in the first and second angular positions. When the binary number representing the eight bits on the wires R11-R18 is combined with the 11 bits on the wire RO-R10, a digital number is produced that represents the angular position of the first reference point on the shaft 101 and the number of rotations of the shaft 101.

It is clear that although the pulse on line MB ceases and the signal on line MA starts substantially simultaneously with the generation of the pulse on line CLOB, the operation time of the subtraction circuit SUBT is sufficiently slower to bring its output from the compensated sag angle signal to the uncompensated signal in accordance with the pulse on line MB ceasing that the compensated signal is delivered on lines R11-R18 as output signals of the eight flip-flop circuits in register 2ST0.

The operation of the embodiment example in fig. will be explained below. 5 and 6 for indicating the angular position of the first reference point on the shaft 101. It is assumed that the first and second reference points on the shafts 101 and 106 are in their first and second angular positions and that the pulse generator PG1 and the pulse generator PG2 simultaneously deliver their index pulses to the wires IMI and IM2. It is further assumed that the shafts 101 and 106 are rotated in a direction in which the binary counters CN1 and CN2 increase their count value with increasing angular rotation of the shaft 101. From what has been previously explained, the pulse generator PG1 will deliver 1024 electrical pulses on each of the wires X and Y for each revolution of the shaft 101. With the rotation of the shaft 101 to increase the count value in the counters CN1 and CN2, the pulses on the wire Y will have a head start on the pulses on the wire X as previously mentioned.

It is understood that the pulses produced by the oscillator OSC on the lines CLO and CLO have such a relationship to the maximum speed at which the pulse generator PG1 rotates that at least four pulses appear on each of the lines CLO and CLO between each pulse delivered on the line X and each pulse on wire Y. As a result, for each pulse on wires X and Y, flip-flop circuits 1X,2X,1Y and 2Y will provide output signals on wires XI, X2,Y1 and Y2. These signals are supplied to the NOR gate circuits NOI, N02 and N03 whose outputs are on

in turn supplies three input signals to the decoder BCD. When generating the pulses in the Y channel 90° before the pulses in the X channel, the pulses appear on the wires in the following order Yl, Y2, XI and X2. The generation of a pulse on wire Yl causes the NOR gate circuit NOI to supply a signal to the A input of BCD. As a result, a corresponding signal appears on output 1 in the decoder. This signal is transmitted to the associated NOR gate circuits Ul and U2 and causes the production of a pulse on line 4U. Likewise, a pulse on wire Y2 will cause the NOR gate circuit N02 to supply a signal to input B of the decoder BCD but without effect at this time because the output 3 of the decoder BCD which supplies the output signal when the input signals are applied to the inputs A and B is not connected in the circuit. The production of a pulse on the line XI causes the NOR gate circuit N03 to supply a signal on the input C of the decoder BCD. With the input signals at inputs A, B and C, the decoder BCD delivers an output signal at output 7. This signal is fed to the associated NOR gate circuits Ul and U2 and results in a second pulse on line 4U.

When the pulse on line X2 is applied to the NOR gate circuits NOI, N02 and N03, each of these will stop supplying a signal. Then, a time pulse on the line CLO will cause the flip-flop circuit 1Y to remove the pulse signal from the line Y1. This causes the NOR gate circuit NOI to again supply a signal to the input A in the decoder BCD. As before, this will cause a pulse on wire 4u. In a similar way, missing pulse signals on the wires Y2 and XI will cause a signal to be produced on the output 7 of the decoder BCD and another pulse will appear on the wire 4U. In this way, each period of signals on wires X and Y will result in four pulses on wire 4u, so that each revolution of the signal generator PG1

in the assumed direction results in the generation of 4096 pulses on the line 4u, which means that 16 such pulses are generated for each angle of rotation equal to one tooth on the gear wheel 102.

Each pulse on line 4U causes the NOR gate circuits NAI and NA2 to deliver corresponding pulses on line UD. These pulses enable the binary up-down counters BC1 - BC5 to increase their count value every time a pulse is supplied to the input CI1 of the counter BC1 from the NOR gate circuit N04 as a result of a pulse on the wire 4U.

The output signals are supplied via the wires PP0-PP11

in accordance with the number of pulses supplied to the input CI1 of the counter BC1 and corresponding inputs CI2 and CI3 of the counters BC2 and BC3 as a result of the previous counters BC1 and BC2

are filled. After delivery of 4096 pulses on line 4U, all counters BC1 - BC3 are filled with the result that an output signal is delivered from output C03 in counter BC3. This is supplied via a wire CO to the input CI4 in the counter BC4 - which, together with the counter BC5, supplies output signals on the wires PP12-PP19 in accordance with the number of input signals supplied via the wire C~0 to the input CI4.

At each new occurrence of the first reference point on the shaft 101 in the first angular position, 4096 pulses are produced on the wire 4U, so that the counters BC1-BC3 are reset to the initial position in which they deliver the count value zero on the wires PP0-PP11. In order to ensure that the counters BC1-BC3 are reset to the initial position upon the new occurrence of the first reference point on the shaft 101 in the

first angular position regardless of one or more pulses

is not counted, an index pulse will appear on the wire Ml when the first reference point on the shaft 101 is in the first angular position. This index pulse is delivered on the wire IMI to the input PE in each of the counters BC1-BC3 and causes

that earth potential on the lines P1-P4 in each counter is transferred to the output lines PP0-PP11 for resetting the counters to the starting position if they have not already been brought to this position.

With each rotation of the shaft 101, the angular position of the reference point will progressively lead in front of the angular position of the second reference point on the shaft 106, because there is one more tooth on the gear wheel 104 than on the gear wheel 102. Each time the second reference point on the shaft 106 reappears in the second angular position , and the signal generator PG2 supplies an index pulse on the line IM2, the first reference point on the shaft 101 is past the first angular position by exactly one tooth more on the gear 102. This effect is cumulative and with the arrangement of binary counters BC1-BC3 each supplying four output signal bits together with 16 pulses applied to line U4 for each angle of rotation of shaft 101 equal to one tooth on gear 102 each time the index pulse from generator PG2 is applied to line IM2, counters BC2 and BC3 contain a number equal to the number of teeth that gear 102 has rotated since the first reference point on the shaft 101 was last time in the first angular position. This number is equal to the number of revolutions of the shaft 101. This is transferred to the output lines PP12-PP19 of the counters BC4 and BC5 as a result of the second index pulse on the line IM2 to the input PE of the counters BC4 and BC5. The supply of such pills causes the signals on the lines PP4-PP11 to be transferred to the lines PP12-PP19 so that if corresponding signals do not already appear on the latter lines, they will appear now.

From the foregoing it appears that if the counters BC4

'and BC5 does not count the sum signals from the counter BC3 via the line CO in the correct way, the count value in the counters BC4 and BC5 will be corrected as soon as the signal generator PG2 delivers its index pulse as a result of the second reference point on the shaft

106 reappears in its second angular position. If, in a similar manner, the electrical energy source is dropped by one revolution of the shaft 101, a correct indication of the total number of revolutions that the shaft has made from the point when the first and second index pulses were produced will be synchronous with a correct indication of the angular position of the first reference point on this axis, will be provided by the first generation of the second index pulse on line IM2 after a first index pulse on line IMI after restoration of the supply of electrical energy from the source.

In this embodiment, as a result of rotation

of the shafts 101 and 106 so that the counters decrement the stored 'numbers therein in accordance with the generation of pulses on the line 4DN which are supplied in a similar manner to those supplied to the line 4U in accordance with the signals on the line X having a lead on the signal on the line Y In this case, the counters BC1-BC5 will decrease the count value in accordance with the occurrence of pulses on the line UD.

In the embodiment of fig, 7, 8A and 8B for

to indicate the angular position of the first reference point on the shaft 101, it is assumed that the first and second reference points on the shafts 101 and 106 are in the first and second angular positions. It is also assumed that as a result of these positions of the reference points on the axes 101 and 106, the signal generators PG3 and PG4 provide signals which are transferred simultaneously from a first logic level represented by binary "1" to a second logic level represented by binary "0". In addition, it is assumed that the signal supplied on the wire IM3 remains at the binary level "0" until the first reference point on the shaft 101 is rotated 180° from the first angular position clockwise and the signal supplied on the wire IM4 remains at the binary level zero until the second reference point on shaft 106 is rotated 180° from its second angular clockwise position, at which position of shafts 101 and 106, the signals on lines IM3 and IM4 are transferred to a logic level represented by binary "1". It is clear that because the gear 102 has one less tooth than the gear 104, the second reference point on the shaft 106 will progressively drop relative to the first reference point on

the shaft 101 and this effect will increase with each revolution of the shaft 101.

If it is assumed that when the shaft 101 rotates a

rotation of 360°, the signal generator PG3 will deliver 1024

periods of an electrical signal on the wires X3 and Y3 and in addition to this when the shaft 101 rotates clockwise, the signals on the wire Y3 will have a lead on the signals on

wire X3 at 90°. At each revolution of the shaft 101

360° clockwise, the signal generator PG3 will also deliver 1024 periods of the signal on each of the wires X3 and Y3 while the signals on the wire Y3 will lag the signals on the wire X3 by 90°. From this phase relationship between the signals supplied to the lines X3 and Y3, the signal processing circuit C0ND2 determines the direction of rotation of the shaft 101 when it rotates and in accordance with the assumed rotation with ur-

the pointer of the shaft 101 deliver binary signal pulses "1" on the out-

time of the NAND gate circuit NND2 in a manner to be described below. These signals are supplied via the line UIO in order to

cause the up and down counters CN3 and CN4 to increase the count value in accordance with pulses supplied to the counter CN3 via the line 4XUD when the angular position of the shaft 101 rotates clockwise. If the assumed rotation of the shaft 101 is reversed, the NAND gate circuit NND2 will supply a binary level signal "0" to the counters CN3 and CN4 as a result of the signals supplied on line Y3 lagging behind the signals on line X3

and the count value in these counters will decrease in accordance with the pulses supplied to counter CN3 via line 4XUD.

As a result of the assumed output position, signals with the binary level "0" are supplied via the wires IM3 and IM4

to the inputs of differential amplifiers B3 and B4 which supply binary signals "1" via lines IM3B and IM4B to registers DIC2. Before rotation of the shaft 101 from the starting position is

no signals present on wires 4XU and 4XD and consequently the output signal from the NOR gate circuit X0R4 will be binary "0"

and the signals on the wires IM3B and IM4B are not entered in the register DIC2. As a result of binary "0" on lines IM3B1, 1M3B2, IM4B1 and IM4B2, the NOR gate circuits X0R1 and X0R2 will both supply a binary signal "0".

Before the shaft 101 begins to rotate clockwise, the signal generator PG3 supplies the negative half of the first period of the signal on the wire Y3 to the input of the differential amplifier B2. This results in the amplifier delivering a binary signal "1" via wire Y3B to register DIC1. This register responds to this signal on wire Y% B and a timing pulse on wire CLO1 and supplies a; signal on wire Y3B1 which is fed to the binary-to-decimal converter BCD3. This signal causes a binary output signal "1" from output 1 in the shaper which is supplied to the corresponding input in the NOR gate circuit N0G1. This gate circuit supplies a binary signal "0" via wire 4XU to the inverter IA3 so that a binary signal "1" appears on wire 4XU. Each binary signal "1" on line 4XU is applied to the NAND gate circuit NND2 which supplies a binary signal "1" on line UIO. Each binary signal "1" on wire 4XU is also applied to the NOR gate circuit X0R4. The first of these which is supplied to the register DIC2 causes a binary signal "1" on the lines IM3B1 and IM4B1 as a result of the binary signal "1" on the lines IM3B and IM4B. These binary signals "1" on lines IM3B1 and IM4B1 are applied to N0R gate circuits X0R1 and X0R2 which supply binary signals "1" on lines IM3BSTB and IM4BSTB.

The binary signal "1" on the line 4XU is also supplied to the NOR gate circuit N0G3 which supplies a binary signal "1" on the line 4XUD which is supplied to the input CIN1 of the counter BUD1. This signal has no effect at this time because the binary signal "1" supplied via the wire IM3BSTB to the input PE in the counters BUD1-BUD3 causes ground potential or binary signal "0" supplied to each of the wires 3Q0-3Q10 to be supplied to the wires 3P0-3P10. At the same time, a binary signal "0" is also applied to line 3Q11 as a result of binary signals "0" being applied via lines IM3B2 and DiO to the NOR gate circuit X0R5. This signal is transferred via line 3Q11 to line 3P11 of counter BUD3 as a result of a binary signal "1" supplied via line IM3BSTB.

Lines 4P4-4P11A receive the signals supplied via lines 3P4-3P11 from summing circuits ADDA and ADDB as a result of the input signal on line C040 being a binary signal "0". This condition prevails as a result

binary signal "0" on the wire 3Pll-N0R gate circuit N0G4

and the binary signal "1" which is supplied to it via the line BE. The latter signal is in binary state "1"

as a result of the supply of the binary signals "0" on the lines IM4B2 and D10 to the NOR gate circuit X0R7- Consequently, the signal on the line BE is binary "0". This signal and the binary signal "0" on line 4P11A are both applied to the NOR gate circuit X0R8 and cause a binary signal "0" to be applied to line 4P11. The appearance of a binary signal "1" on the wire IMB4STB as previously mentioned causes, under these conditions, that

■counters BUD4 and BUD5 deliver binary signals "0" on lines 3P12-3P19- With binary signals "0" on all lines 3P0-3P19, counters BUD1-BUD5 are in the initial position. Additional pulses on line CL01 are without significant effect because shaft 101 remains stationary. The first additional pulse applied via line CL0.1 causes the register DIC1 to provide a binary output signal "1" on line Y3B2 as a result of the binary signal "1" on line Y3B1. This is fed via the NOR gate circuit X0R3 to input B in the converter BCD3 which causes the binary signal "1" on input 1 to be returned to binary "0". This causes the'NOR gate circuit

N0G1 delivers a binary signal "l" on line 4XU and a binary signal "0" via inverter IA3 to line 4XU. This binary signal "0" causes the NOR gate circuit X0R4 to supply a binary signal "0" without effect.

It is then assumed that the shaft 101 has started its clockwise rotation. As mentioned, under this condition the signals on wire Y3 will have a lead on the signals on wire X3 by 90°.

Por to understand how the signals from the generators

PG3 and PG4 bring the counters BUD1-BUD5 to deliver output signals indicating rotation of the shaft 101, it will be described below how the generation of the pulses on the line 4XUD takes place.

The next important time pulse. supplied via the line

<CL01> to register DIC1 when a binary signal "1" is applied to the register on wire X3B. This time pulse causes the register DIC1 to deliver a binary signal "1" via line X3B1 to the second input in the NOR gate circuit X0R3. As a result

of this, this delivers a binary signal "0" to input B

in the converter BCD3. It is understood that the binary signal "1" is still supplied via wire Y3B1 to input A

in the converter BCD3. As a result, the converter delivers BCD3

a binary signal "1" via output line 1 to the NOR gate circuit N0G1 so that a binary signal "1" appears on line 4XU and a binary signal "0" on line 4XU. This binary signal "1" on line 4XU is applied to the NOR gate circuit X0R4 and causes the register DIC2 to apply the binary signal "1"

on wires IM3B1 and IM4B1 to wires IM3B2 and IM4B2. These latter signals cause binary signals "1" on lines IM3BSTB and IM4BSTB to be transferred to binary signals "0" to enable counters CN3' and CN4 to count pulses supplied on line 4XUD.

The next time pulse applied to the register DIC1 causes a binary signal "1" to be applied via the line X3B2 to the input X of the converter BCD3. As a result of the binary signal 1 on the input C, the converter BCD3 supplies binary signals "0" to each of the output lines 1,2,4 and 7. As a result of the binary signal "0" on the line 4XU is transferred to binary "1 " and the binary signal "1" on the line XU is transferred to binary "0".

As a result of the signals supplied via wire Y3 having a lead over the signals supplied on wire X3 as a result of the assumed direction of rotation, it is clear that at the end of the first half period of the signal supplied via wire Y3 to the amplifier'B2, the amplifier delivers a binary signal "0" via wire Y3B to register BIC1. The first time pulse which is supplied to the register DIC1 after the binary signal "0" has been supplied via the wire Y3B causes the supply of the binary signal "0" on the wire Y3B via the wire Y3£1 to the input 1 of the converter BCD3. At this time

e- it is understood that the binary signal "1" is supplied to each input of the NOR gate circuit X0R3 via the wires Y3B2 and X3B1 and in addition a binary signal is supplied via the wire X3B2

to input C in converter BCD3. As a result of the signals supplied to the converter BCD3, this delivers a binary signal "1"

its output 4 to the NOR gate circuit N0G1 which causes a binary signal "1" to appear on line 4XU. The next time pulse

causes register DIC1 to supply a binary signal "O" on wire Y3B1 to wire Y3B2. As a result, the NOR gate circuit X0R3 supplies a binary signal "1" to the input B

in the converter BCD3 which delivers a binary signal "0" to each of its outputs 1,2,4 and 7-

It is further understood that as a result of continued clockwise rotation, a binary signal "0" is delivered via line X3B to register DIC1 from amplifier Bl. The next time pulse applied to register DIC1 causes the binary signal "0" to be applied to line X3B via line X3B1

to an input in the NOR gate circuit X0R3. At this point, it is understood that the binary signals are supplied via wire Y3B2 to the second input of the gate circuit X0R3 and via wire Y3B1 to the converter BCD3. At the same time, a

binary signal "l" via the line X3B2 to the input C of the converter BCD3 which, as a result, supplies a binary signal "1" from the output 4 to the one input of the NOR gate circuit N0G1. As a result, a binary signal "l" is supplied to line 4XU. When the next time pulse is applied to the register DIC1, the register will supply the binary signal "0" on the wire X3B1 via the wire X3B2 to the input C of the converter BCD3. As a result of that

binary signal "0" which is supplied to each of the inputs A,B,C and D

in the converter BCD3, this will deliver a binary signal "0" on the output lines of the NOR gate circuits N0G1 and N0G2.

From the foregoing it appears that as a result of each

binary signal "l" applied to the NOR gate circuit N0G1, a corresponding binary signal "l" will be applied to line 4XU. When the signals on wire Y3 have a head start on the signals on. wire X3 is consequently supplied with four pulses on wire 4X0 for each period of the signal on wire Y3 to amplifier B2.

In the same way when the signals on wire X3 have a lead

on the signals on wire Y3, four pulses will be supplied via wire 4XD for each period of the signal via wire X3 to the amplifier Bl.

The signals on wires 4XU and 4XD are applied as shown

on fig. 8A the input in the NOR gate circuit N0G3- As a result of what has been explained above, it appears that the NOR gate circuit M003 delivers 4096 pulses per rotation of the shaft 101 via the line 4XUD to the input in the counter CN3 regardless of the direction of rotation of the shaft 101.

It is clear that the output signal from the counter CN3 indicates the position of the first reference point on the shaft 101 and the counter CN4 indicates the number of revolutions of this shaft. When the shaft 101 rotates in the assumed direction, the counter CN3 responds to signals supplied to it via line 4XUD while the counter CN4 responds to the sum signals supplied to it via line C030 to accumulate the pulses in the usual way, as explained for counters CN1 and CN2 in in connection with the execution of fig. 5 and ,6. However, it should be shown that if one of the counters incorrectly indicates the position of the first reference point on the shaft 101, corrections will be applied to each of the counters during each revolution of the shaft 101.

In order to illustrate the behavior of the correction signal used, it is assumed that the first reference point on the shaft 101 rotates through an angle of 180° from the assumed starting position where it was in the first angular position. • It is therefore understood that 2048 pulses are supplied via line 4XUD

to the input in the counter CN3. As a result of the counting of each of these 2048 pulses, the counter CN3 supplies pulses on the wires 3PO-3P11 which represent in binary form the equivalents of the decimal number 2048.

If for the same reason the signals on the wires 3PO-3PH representing the number of pulses received by the counter CN3 are not correct, these signals will be corrected when the reference position of the shaft 101 is rotated 180° from its first angular position on. the following way.

Each time the shaft 101 is rotated 180° clockwise

from its first angular position, the pulse corresponding to this is supplied via the wire 4XUD to the input of the counter CN3 approximately simultaneously with the signal on the wire IM3 from the pulse generator PG3 as previously mentioned, and is brought from binary "0" to binary "1". As a result, the differential amplifier B3 supplies a signal level "0" via the wire IM3B to the register DIC2. The binary signal level "1" on the line 4XU at this time is applied to the NOR gate circuit X0R4 and causes the register DIC2 to transfer the signal level "0" on the line I<M>3B to the output line IM3B1. As can be seen from the above, a binary signal "1" will appear on wire IM3B2 at this time due to the continued presence of binary "1" on wire IM3B during rotation of shaft 101 by 180°. The binary signal level "1" on

the line IM3B2 and the binary signal level "0" on the line IM3B1 causes the NOR gate circuit X0R1 to produce a signal which via the line IM3BSTB is supplied to the counter CN3 and causes ground potential or the binary signal level "0" on the lines 30,0-3010 to be supplied to the lines 3PO- 3P10. At this time, the binary signal level "1" on the line IM3B2 is also supplied to the NOR gate circuit X0R5 which together with the gate circuit X0R6 produces a binary signal level "1" which via the line 3Q11 is supplied to the counter CN3. This binary signal level "1" on line 3QH together with the binary signal level "0" on lines 3QQ-3°10 is transferred to the output lines from the counter. CN3 using the signal supplied to the counter via wire IM3BSTB so that if corresponding signals do not already appear on these output wires, they will now appear. As a result, the counter will present the number correctly in binary form

pulses applied to its input via wire 4QUD during a 180° turn. Counter CN3 is prepared to continue counting on the next pulse on line 4XU which transfers the binary level "1" on line IM3B2 to a binary level "0" causing a binary level "0" to appear on line IM3BSTB. This latter signal resets the counter CN3 to the state in which it can count pulses received on the line

4XOUT.

Each time the first reference point on the axis 101

occurs-in the first angular position, the counter CN3 will similarly be corrected to indicate the count value zero. Meanwhile, the signal on wire IM3 can change from binary "1" to binary "0". This is entered into register DIC2 in response to the simultaneous occurrence of a pulse on line 4XU and causes the production of binary "1" on lines IM3B1 and IM3BSTB. The signal on this latter line causes the transfer of the ground potential or the binary level "0" on the lines 3Q0-3Q10 to the lines 3PO-3P10. A binary level "0" also appears on line 3QH as a result of both lines IM3B2 and D10 having binary level "0V at this time. Consequently, all lines 3PO-3PH will have binary signal level "0" indicating the count value "zero.

The counter CN4 also has its count value corrected if necessary every time the second reference point on the shaft 106 is in the second angular position and 180° turned from this position. The first of these corrections takes place in the same way as described with reference to fig. 5 and 6. In order to provide the correction in the event of a rotation of 180°, extra equipment is provided, the operation of which will be explained in connection with both correction steps.

When the second reference point on the shaft 106 is in the second angular position, the signal level on the line IM4 is brought from binary "1" to binary "0"; This results in binary "1" appearing on wire IM4B1' as a result of the simultaneous pulse on wire 4XU. Binary "1" on wire IM4B1 causes similar binary "1" on wire IM4BSTB to be produced. As previously mentioned, this means that the signals

on the wires 4P4-4P11 appears on the wires 3P12-3P19 for the counter CN4, so that the previous signal will appear there if corresponding signals do not already appear there. From the description in connection with fig. 5 and 6, it appears that when the second reference point on the shaft 10-6 is in the second angular position, the count value in the counter CN3 on the output lines 3P4-3PH will indicate the number of times that the first reference point on the shaft 101 has passed the first angular position. This number is the correct number on the output of the counter CN4 during each revolution of the shaft 101 and is transferred to the counter CN4 as a result of the binary signal "1" on the wire IM4BSTB if this number is not already present. This happens because the summing circuit ADD1 receives the binary signal level "0" from the NOR gate circuit N0G4 and the NOR gate circuit X0R8 receives a binary signal "0" from the line BE. Accordingly, the signals on the lines 3P4-3P11 are simply transferred to the lines 4P4-4.P11 for further transfer of the counter CN4 to the lines 3P12-3P19- The signal on the line BE is binary "0" when the second reference point on the shaft 106 is in the second angular position because the signals on the lines IM4 B2 and D10 are binary "0" at this time for the assumed direction of rotation. With the signals on wires 3P4-3PH transferred to wires 3P12-3P19, the count value is corrected.

The next pulse on wire 4XU causes a binary "1" on wire IM4B2 and transfers the signal on wire IM4BSTB to binary "0". Accordingly, the count value in the counter CN4 will be maintained until the reception of the next sum signal on the line C030 as a result of the counter CN3 having completed a count of 4096 pulses or until the reception of the next correction pulse on the line IM4BSTB.

To understand how the counter CN4 is corrected every time the second reference point on the shaft 106 passes the angular position 180° turned from the second angular position, it is assumed that the rotation of the shaft 101 has caused the shaft 106 to be in this position. When this occurs, the signal from the pulse generator PG4 via the wire IM4 which is fed to the amplifier B4 will change from binary "0" to binary "1". As a result, the next simultaneous pulse on line 4XU applied to register DIC2 will cause it to apply the binary signal "0" from amplifier B4 on line IM4B to its output line IM4B1. It appears from the foregoing that the presence of the binary signal "1" on line IM4B up to this point has caused a signal level "1" on line IM4B2. The binary signal "0" on the wire IM4B1 is supplied to an input in the NOR gate circuit X0R2 when it is combined with the binary signal "1" which is supplied via the wire IM4B2 to the other input in the gate circuit which delivers a pulse which is supplied via the wire IM4BSTB the counter CN4.

When ■ the second reference point on the shaft 106 is rotated 180° from the second angular position, the count value in the counter CN3 indicated by the signals on the wires 3P4

to 3P11 represent the number of times that the first reference point on the shaft 101 has passed the first angular position from the initial position plus a number indicating the angle that the shaft 111 has turned in accordance with the 180° that the shaft 106 has turned from the second reference point it was in itself in the other angular position. This angle causes the signal on line 3P11 to be the complement of the desired number to be transferred to counter CN4 when the second reference point on shaft 106 is 180° from its second angular position. The NOR gate circuit X0R8 compensates for this by causing the signal on wire 4P11 to be brought to binary value "1" when the signal on wire 3P11 is binary "0"

and vice versa. This happens because the signal on the wire BE is binary "1" when the second reference point on the shaft 106 is turned

146037 <32>

180° in relation to the second angular position as a result of binary signal level "1" still appearing on the line IM4B2 during the rotation of the second reference point on the shaft 106 from the second angular position to a position 180° rotated in relation to this in the assumed direction of rotation .

With binary "1" on line BE, binary "1" on line 3PH and consequently 4P11A occupies so that the NOR gate circuit X0R8 supplies binary signal level "0" on line 4P11. Conversely, binary "0" on wire 3P11 and 4P11A will cause gate circuit X0R8 to supply a binary signal level "1" on wire 4P11. Consequently, during the generation of the signal on line IM4BSTB, the presence of the complement on line 3P11 will ensure that the number transferred to counter CN4 is not incorrect so that the correct signal is transferred to line 4P11.

From the above, it appears that the signal generated by the pulse generator PG4 and fed to the signal processing circuit C0ND2 via the wire IM4 progressively slows down in relation to the signal generated by the pulse generator PG3 and fed to the signal processing circuit C0ND2 via the wire IM3 with further rotation of the shaft 101. This progressive slowing reaches the reference point on the shaft 101 is rotated in relation to the starting position 128 and half a revolution the logic level of the wire IM3 will change from every binary "0" to binary "1" and at the same time the signal on the wire IM4 will change from binary "1" to binary "0" . As will be explained below, when the first reference point on the shaft 101 is rotated

beyond 129 revolutions from the starting position, the signals on the wires 4P4-4P11 when applied to the counter CN4 give an incorrect indication of the number of revolutions of the first reference point. Accordingly, the summing circuit ADD1, the gate circuit X0R7, the gate circuit X0R8 and the inverter IA5 will act as a detector and ensure that the signals on the lines 4P4-4P11 correctly represent the number of revolutions of the first reference point on the shaft 101 when these signals are applied to the output lines 3P12-3P19 from the counter CN4.

As a result of the progressive sag between shafts 101 and 106, the first reference point on shaft 101 is moved closer and closer to the first angular position for each further position of the second reference point on. the shaft 106 in angular position 180° from the other angular position. Nevertheless, the signals supplied by the counter CN3 on lines 3P4-3P10 and applied to line 4P11A by the OR gate circuit X0R8 will approach the second reference point of

the shaft 106 is turned 180° correctly indicated by the number of revolutions of the first reference point on the shaft 101 beyond the first angular position. "This continues until the 127th revolution of the shaft 101 when its first reference point is half a tooth from the first angular position and the second reference point of the shaft 106 is 180° from the second angular position. During the next revolution of the shaft 106, 257 teeth of the gear 104 , the first reference point on the shaft 101 will therefore pass the first angular position twice because its gear 102 with its 256 teeth also

must rotate 257 teeth. This brings the first reference point half a tooth past the first angular position. Accordingly, when the second reference point on the shaft 106 reaches the position 180° from the second angular position as a result of its rotation, the count value in the counter CN3 representing the number of times the first reference point has passed the first angular position should be equivalent to two or more than :.it was at the previous passing of the second reference point on the shaft 106 in the position 180° from the second angular position. However, the count value in the counter CN3 seems to indicate that only such a rotation of the shaft 101 beyond the first angular position has occurred. To provide an additional count value, the NOR gate circuit N0G4 supplies a binary level "1" to the summing circuit ADD1; during this and each subsequent passage of the second reference point on the shaft I06 in the 180° rotated position.

In each such case, the signal on line IM4B2 will be binary "1" and cause binary "0" on line BE.

Also because the position of the first reference point on the shaft 101 in relation to the first angular position below this and each subsequent passage of the second reference point on the shaft 106 is turned 180°, the signal on the line 3P11 each time will also be binary "0". This causes binary "1" on wire C040 which summed to the signals on wires 3P4-3P10 and together with the signals on wire 4P11 during such revolutions are transferred to wires 3P12-3P19 the signals indicating the number of times that the first reference point has passed the first angular position to correct the output signal from counter CN4 if there should be an error in this number.

From the foregoing, it appears that if the counter CN3 or CN4 does not emit correct signals indicating the position of the first reference point on the shaft 101 and the number of times the first reference point on the shaft 101 has passed the first angular position, the output signal from these counters will be corrected each time logic levels for the signals produced by the signal generators PG3 and PG4 are changed from a first level to another level or from another level ti.1 a first level. The level change which causes correction of the counter CN3 during each revolution of the shaft 101 is chosen to occur when the first reference point on the shaft 101 is in its first angular position and again when the first reference point is rotated 180° from the first angular position. The level changes which cause correction of the counter CN4 during each revolution of the shaft 101 have been chosen to occur when the second reference point on the shaft 106 is in the second angular position and again when the second reference point is rotated 180^

in relation to the other angular position.

The operation of this embodiment example as a result of rotation of the shafts 101 and 106 is such that the counter decreases the stored number in accordance with the fact that signals supplied on the wire 4XUD occur when there is no signal on the wire UIO. This happens when the signals on the wires X3 lead the signals on the wire Y3.. It should be noted that if the direction of rotation of the shafts is reversed, the signals on the wires IM3B2 and IHHB2 will have the wrong level to give the desired effect of the OR gate circuit X0R8 and NOR -the gate circuit N0G4 as previously described. To remedy this, input signals are supplied via wire D10 to the OR gate circuits X0R5 and X0R7, and these signals provide the operation as do the signals on wires IM3B2 and IM4B2 for rotation in the opposite direction.

Claims (5)

1. Shaft position converter with a first code disk arranged on a first rotatable shaft, a second code disk arranged on a second rotatable shaft, electrical sensing devices for sensing the code indications of the disks, and a signal processing device that processes the sensing signals from the electrical sensing devices and brings them for indication, as the first and second rotatable shafts are connected to each other via a coupling, characterized by the combination of the following features: a) the first shaft (101) is continuously coupled to the second shaft (106) in such a way that at a whole number of revolutions of the first shaft (101) the second shaft (106) is turned a number of revolutions that differ only slightly from the revolutions of the first shaft, b) the signal processing device processes the sensing signals from the electrical sensing devices in such a way that the indication is a function of the difference between the angular position of the two code discs (103,105). 2. Converter according to claim 1, characterized in that each code disc (103,105) has a complete absolute position code, and that the signal processing device has aids (SUBT) for subtracting the absolute position code signals (CAO-CA9) from the first code disc (103) the code signals (BO-B10) from the second code disc (105). 3. Converter according to claim 1, characterized in that the signal processing device comprises a counting device with a section (CNZ;CN4) of higher order and a section (CN1;CN3) of lower order, each of which contains several parallel data inputs (P1-P4 ) and a parallel order input (PE) and emits output signals of which the section (PB0-PP11; 4P4-4P11) of lower order indicates the rotational position of one disc and the section (PP12-PP19; 3P12-3P19) of higher order indicates the relative rotational position between the first and second readable reference numbers, so that an indication of the number of revolutions of the code disks is obtained, that the parallel data inputs for the section of higher order in the counting device are connected to the outputs (PP4-PP11; 3P4-3P11) in the section of lower order, for in the higher-order section to enter a count value that indicates the relative rotational position of the code discs, as the outputs of the counting device emit both an indication of the rotational position of one code disc, and a subordinate indication of the relative rotation between the first and second code disc which in turn forms an indication of the number revolutions that one code disc has turned. 4. Converter according to claims 1 and 3, characterized in that the first code disk (103) is rotatable in relation to the second code disk (105) in such a way that the first code disk performs a first binary number of 2<n>+1 revolutions, while the second encoder disk (105) performs a second binary number of 2n revolutions. 5. Converter according to claim 4, characterized in that the first code disc (103) has readable reference numbers that indicate a first reference position for the first code disc and a reference position 180° offset from the first reference position, and that the second code disc' (105) has readable reference number indicating a second reference position for the second code disc and a reference position offset by 180° from the second reference position.