FI64998B - MAETVAERDEOMVANDLARE FOER ROTATIONSPOSITION AV EN ROTERANDE AXL - Google Patents

Description

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(32) (33) (31) Requested privilege — Bajird prloritat l8.12.7 5 USA (US) 6 ^ 1798 (71) Otis Elevator Company, One Financial Plaza, Hartford, Connecticut ΟβίΟΙ, USA (US) (72) Marvin Masel , Teaneck, New Jersey, Ralph J. Meehan, Wayne, New Jersey,

The present invention relates to a rotary shaft rotary position measuring transducer having a first coded disk with a first coded plate, which is a rotary shaft rotational position measuring transducer with a first encoded plate. to the first rotating shaft, a second coded plate adapted to the second rotating shaft, circuitry for detecting and displaying the identification signals produced by the electronic sensing devices for detecting the coding indicia of the plates, the first rotating shaft and the second rotating shaft being connected to each other by a clutch transmission.

When it has previously been desired to generate a signal indicating the angular position of a rotating shaft several times, it has been standard practice to use a reduction gear with two rotary position transducers, if necessary, with a high resolution and a wide measuring range. The shaft directly drives the second transducer, resulting in good signal resolution. The second transducer is operated in a reduction gear and provides measuring range signals. Early devices of this type required extremely precise and expensive reduction gears.

U.S. Patent No. 2,944,159 discloses a device for reducing the complexity of a reduction gear used with two rotary position transducers. This simplified gear unit is used in U.S. Patent No. 3,885,209 in conjunction with two synchronous, or resolver, 2 64998 cascades to generate an analog position signal. When a digital output signal indicating the position of the axis is desired when using the syncs or resolvers used in this latter patent, analog-to-digital conversion devices are required. Conversion to a digital signal is difficult if both high resolution and wide measurement range are desired from analog equipment, and as a result, such equipment is expensive.

It is an object of the present invention to provide a device which produces digital signals indicating the angular position of an axis and is simpler than previous devices.

The measured value converter according to the present invention is characterized in that the first coded plate is rotated relative to the second coded plate so that the first coded plate rotates 2 ° +1 revolutions of the first binary number while the second coded plate rotates 2n revolutions of the second binary number, where n is greater than zero integer. The signal processing circuitry processes the identification signals produced by the electronic detection devices so that the display is a function of the difference in the angular position of the coded plates.

The signal processing switching device of the measured value converter according to the invention comprises: a calculator having an upper level part and a lower level part, each containing a plurality of parallel data inputs and a parallel command input, this calculator generating output signals from which the lower level part indicates the second plane rotation the relative rotational position between the detectable reference characters, so that the number of revolutions of the coded plates is indicated, that the parallel data inputs of the top-level portion of the calculator are combined with the outputs of the lower-level portion of the calculator the relative rotation between the first and second coded plates, which in turn is an indication of the number of revolutions ka one of the encoded discs has rotated.

Three different embodiments of the invention are described. In the first disclosed embodiment, the first and second rotation signal generators are absolute coding devices. Thus, when the power is turned on after it is turned off, each immediately develops its output signal, whereby the logic circuits immediately generate a rotation position signal that correctly represents the correct angular position of the first axis.

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In the second and third present embodiments, incremental signal generating devices are used as the first and second rotational signal generators. However, both of these embodiments are arranged in such a way that they do not have one of the disadvantages of previous positional transducers using growing devices. When the power is turned on after it is turned off, earlier cultivating-type transducers require a return to the initial state or an external reference value to develop the correct angular position of the first reference point and the correct number of revolutions of the first shaft.

The second and third embodiments presented herein have the advantage that they do not require either of the reset settings required by earlier breeding type transducers. As a result, they combine the simplicity of breeding equipment in this respect with the advantage of an absolute device. In another embodiment, the correct angular position of the first fixed point and the correct number of revolutions of the first shaft are obtained during the two revolutions of the first shaft after the power is turned off. In a third embodiment, this recovery is achieved during one such round.

Those skilled in the art will also appreciate from these embodiments how modifying them will obviously provide even faster recoveries.

Other objects, features and advantages of the invention will become apparent from the following description and appended claims, taken in conjunction with the accompanying drawing, in which Figure 1 is an overview of some mechanical parts of the invention, Figure 2 is a block diagram of one embodiment, Figures 3 and 4 together show Figure 2. circuit elements, Fig. 5 is a block diagram of a second embodiment of the invention, Fig. 6 shows an arrangement of circuit elements of the embodiment of Fig. 5, Fig. 7 is a block diagram of a third embodiment of the invention, Figs. 8A and 8B show an arrangement of circuit elements used in the embodiment of Fig. 7.

Referring now to the drawing, Fig. 1 shows a drive shaft 101 on which a first gear 102 and a rotary position transducer 103 are mounted. A second gear 104 is mounted in contact with the gear 102 and is mounted on a shaft 106 together with a second rotary position transducer 105.

In the first of the three embodiments described below, the transducers I03 and 105 are digital encoders, each of which generates 2048 separate output signals for each revolution of its axis, each of which is 11 signal bits long. In this first embodiment, the first gear 102 has one tooth less than the second gear 104. In particular, the gear arrangement 102 has 255 teeth and the gear 104 has 256 teeth.

In the second of the two embodiments described below, each of the transducers 103 and 105 are rotational signal generators. In each of these embodiments, the first transducer 103 generates 1024 electrical signal cycles on each of the two channels at each round. In addition, it generates index signals, which are described in more detail below for each embodiment separately. The second transducer 105 of each embodiment generates only index signals, which are described below for each embodiment separately. Also in these embodiments, the first gear 102 has one tooth less than the second gear 104. In the arrangements described, in particular, the first gear 102 has 256 teeth and the second gear 104 has 257 teeth.

The block diagram of Fig. 2 shows a part of the resolution and measurement range of the device according to the first described embodiment of the invention. The various input and output lines in this figure are marked with indicia indicating the similarity between the blocks of this figure and the circuit elements of Figures 3 and 4.

The resolution part of this device has a first register AREG which is connected to the multi-bit output signal of the first encoder of the Baldwin period encoder series 5V200 or the like (previously mentioned as corresponding to the transducer 103 but not shown in detail). The encoder selected for this embodiment becomes 11-bit gray-coded output signals on the EAO-EAIO lines, and as a result, the AREG output of the register is connected to the ACON input of the gray-binary code converter to provide binary-coded output signals. The ACON output signals of the converter are also input to the ISTO memory register.

The measuring range part of the embodiment shown in Fig. 2 has a selector switch SWB which receives 11-bit gray-coded output signals from another encoder, which is also a Baldwin period encoder series 5V200 (previously mentioned as corresponding to transducer 105, but not shown in detail). These signals are imported along lines EB0-EB10. The SWB also receives input signals along lines S0-S10 from the device described below. The output of the switch SWB is connected to the register BREG, the output of which in turn is connected to the gray binary code transformer ECON.

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The outputs of the gates GAA of the converter ECONt and the selector switch SWB are input to the subtraction circuit SUBT, which generates signals indicating the number of revolutions of the shaft 101 (Fig. 1) in this embodiment. These signals are fed to another memory device 2ST0 and a switch SWB. Figure 2 also shows a device TSIG generating timing signals, from which output pulses are output on the lines OLOA, MA, MB and CLOB.

Figure 3 shows that the register AREG consists of 11 D-type flip-flops model Motorola MC14013 or equivalent. Each of these receives a clock pulse from the signal generator TSIG via the CLOB line. As is well known, when a clock pulse appears along the line CLOB, each of these flip-flops is able to generate an output to the corresponding output line AG0-AG10 according to the signal coming to its corresponding input EA0-EA10. Also, two of these flip-flops, whose input signals come from lines EA3 and EA10, develop second outputs to lines AG3 and AGIO, which are the inverse values of the first output signals to lines AG3 and AGIO. The inverted output signal AG3 and the first output signals to lines AG0-AG2 and AG4-AG10 are input to ten exclusive OR ports as shown in the figure, and these ports form the gray binary converter ACON. These exclusive OR ports are Motorola MC14507 or equivalent.

The output signals to ACO lines CAO-CA3 of the converter are the inverse of the four least significant bits of each binary coded number corresponding to the gray code number imported into register AREG along lines EA0-EA10. The seven most significant bits of the binary coded numbers corresponding to the gray code numbers imported into the AREG register are imported on the lines AGIO and CA9 via CA4 *. The signals of lines CA8 and CA9 are applied to the inputs of inverters 18 and 19; these inverters are model Motorola MC14049 or similar and their output signals come on lines CA8 and CA9.

The selection switch SWA, which consists of a Motorola MC14519 or equivalent 4-bit AND / OR selection circuit, comes with the four least significant bits of the binary numbers generated on lines CAO-CA3, inverted together with the signals of lines AGIO, CA9, CA8 and E1 +. The signal on line E1 + is a positive constant DC voltage, the magnitude of which corresponds to the binary one of the equipment under consideration and is obtained from any suitable source (not shown). The switch SWA generates output signals for the output lines AO-A3, and these signals correspond to the signals from the lines CAO-CA3 if the switch receives a pulse from the line MA, or from the lines E1 +, AGIO, CA9 and CA8 if the switch receives a pulse from the line MB. Gates GA consisting of seven models of the Motorola MS14011 or equivalent EI-AND element 6 64998 will receive input signals along lines CA4-CA9 and AGIO, and will generate signals for output lines A4-AIO and AGIO, and will generate signals for output lines A4-A10 when a pulse comes from line MA. The signals of lines CAO-CA3, CA4-CA9 and AGIO are also imported into the first memory unit ISTO consisting of 11 models of Motorola MCI4OI5 or equivalent D-type flip-flop. When these flip-flops receive a clock pulse from line CLOE, each of them sends an output signal corresponding to its input signal to lines R0-R10.

The timing signal generator of Figure 3 has two models of Motorola MC14011 or equivalent AND-NO gates N1 and N2, which together with resistors R1 and R2 and capacitor C1 form a freewheeling multi-vibrator that generates pulses at 2/100 Hz. These pulses are used to generate pulses on lines MA, MB, CLOA and CLOB on the D-type flip-flop D1 (MC14013 or equivalent) and on the AND-EI gates N3 and N4 (MC14011 or equivalent). As shown in the timing diagram next to the generator TSIG, the frequency of the pulses in the CLOA line is the same as that of a freewheeling multivibrator with a pulse width of half a cycle. This frequency is selected fast enough for the line CLOA to have at least four complete pulse cycles during the output signal sent to the lines EAO-EAIO of each transducer 101 at the maximum speed of the transducer. The pulses of the lines MA and MB are complementary to each other, and their frequency is half the frequency of a freewheeling multivibrator whose pulse width is also half a period. Also, the frequency of the line CLOB pulses is the same as half the frequency of a freewheeling multivibrator, but their pulse width is three-quarters of one period.

Figure 4 shows a measuring area part of the first described embodiment. The selector switch SWB, which consists of three 4-bit AND / OR selection circuits (model Motorola MC14159 "or equivalent), receives gray-coded input signals from lines EB0-EB10. It also receives input signals from lines S0-S10 and sends output signals to lines BG0-BG10; signals correspond to either group of input signals depending on whether a pulse comes from the line MB or MA to the switch selection circuits.

Outputs to switch SWB lines BG0-BG10 are brought to register BREG, which consists of eleven type D flip-flops (model Motorola MC14013 or equivalent). These flip-flops output signals to lines SBO-EBIO according to the signals from lines BG0-BG10 whenever a clock pulse is applied to line CLOA.

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The signals output from register BREG to lines SB0-SB10 are input to one set of gray-binary code converters BCON. This unit has three 4-bit AND / OR selection circuits (model Motorola MC14519 or equivalent) and works in two ways. When signals are received from lines E1 + and MA, it converts the signals from lines S30-SB10 to its second input group from the gray code to the corresponding binary code and sends these binary code signals to its output lines B0-B10. During each half-cycle of the signal of the line MA, when no pulse occurs, the converter BCON acts as a selector switch according to the voltage continuously coming from the line E1 + and transmits the signals from the lines SB0-SB10 to its output lines B0-B10.

The signals output to the BCON lines B0-B10 of the converter are input to one input group of the subtractor SIJBT, this subtractor consists of three four-bit totalizer circuits (model Motorola MC14008 or equivalent). As mentioned above, the reducer. SUBT The second input group receives the signals sent by the device's resolution section switch SWA and gates GAA to lines A0-A10.

When there is no pulse from line MB to the SUBT input of the subtractor, it generates signals S0 to S10 on its output lines, which denote the sum of the input signals of its two input groups. During each half-cycle of the line MB signal at which a pulse occurs, the subtractor SUBT generates signals on its output lines denoting the sum of the input signals of its two input groups plus a binary one according to the pulse of the line MB. The "memory" outputs KOI and K02 of the first two adder stages are connected to the "memory" inputs KI2 and KI3 of the second and third adder stages as shown in a known manner.

The eight most significant outputs of the subtractor SUBT are imported via lines S3-S10 to the second register 2ST0. All SUBT outputs of the subtractor are input, as mentioned above, to the selector switch SWB. The second register 2ST0 consists of eight D-type flip-flops (model Motorola MCI4OI3 or equivalent), each of which operates when it receives a pulse from line CLOB and transmits the signals from lines S3-SIO to lines R11-R18.

The block diagram of Figure 5 shows a second embodiment described in the order of the invention. In this embodiment, there are two signal generators PG1 and PG2 of the model TRU-Rota DC-1024-D-11-M-SD-12V, so that PG1 corresponds to transducer 103 and PG2 to transducer 105. · Signal generator PG1 generates similar pulse-shaped output signals for the two channels. The signal of the second channel is brought along the output line X and the signal of the second channel is brought along the output line Y. Depending on the direction of rotation, the signal of line Y is either 90 ° above or below the signal of line X, i.e. a quarter of the period of signals 8 64998. As previously described, 1024 signal cycles are applied to each line, X and Y, during each cycle of the signal generator PG1. In addition, the signal generator PG1 generates a first index pulse on the line IMI each time the first fixed point of the axis 101 is in the first angular position.

The output signals sent by the signal generator PG1 to lines X and Y are input to a signal shaping circuit C0ND1, which sends signals to lines TO, 4DN and 4U, which cause the bidirectional counter CN1 to send output signals to lines PP0 to PP11 indicating the first fixed point of the axis 101.

The counter CN1 also sends a signal to the line CO whenever it is reset by sending a predetermined number of signals from the modifying circuit C0ND1 to fill the counter. The signals of the line CO are fed to the counter CN2, which they cause to send signals to the lines PP12 to PP19, which indicate the number of times the first fixed point of the shaft 101 passes through the above-mentioned first angular position.

The signal generator PG2 sends a second index pulse to the line IM2 each time the second fixed point of the shaft 106 passes through the second angular position. The pulse signal from line IM2 to counter CN2 causes the counter to send to it signals from counter CN1 via lines PP4-PPH to lines PP12-PP19, so if these latter lines do not already have corresponding signals, now they do.

Fig. 6 shows the circuit elements forming the signal converter C0ND1 sB of Fig. 5 and the counters CN1 and CN2. The signal processor C0N1 has an oscillator OSC which transmits pulses to the line CLO and their complement pulses to the line CLO at a frequency of 122.9 kHz with a pulse width of half a period. The signal processor also has several D-type flip-flops of model Motorola ΜΘ14013 or similar, which receive signals from the signal generator PG1 via lines X and Y. These units generate signals for lines X1 and X2 and Y1 and Y2 in response to signals for lines X and Y. The signals of lines X1, X2, Y1 and Y2 are input to three exclusive OR ports N01, NO2 and N03 (model Motorola MC14507 or equivalent), the outputs of which are input to a binary coded decimal or decimal decoder BCD (model Motorola MC14028 or equivalent). The decoder BCD together with the NOT-OR and the inverter port pair UI, U2, D1 and D2 (model Motorola MC14001 and MC14049 or equivalent) send signals to lines 4U, 4DN and 4DN.

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Depending on the direction of rotation, four pulses are output to line 4U or 4DN for each period of signals coming from lines X and Y of signal generator PG1. Line 4DN signals are complements of line 4DN signals. The signals on lines 4TJ and 4DN together with the two NO gates NAI and NA2 (model Motorola MC14001 or equivalent) generate signals for line UK.

The bidirectional counter CN1 has three four-bit binary up-down counters BC1, BC2 and BC3 connected in series. The bidirectional counter CN2 has two such four-bit binary up-down counters BC4 and BC5. Each of the counters BC1-BC5 is a model Motorola MC14526 or equivalent. As shown, all four data lines P1-P4 of each counter BCI-BC3 are connected to ground potential, and these signals are applied to the output lines of counter CN1 whenever a signal from line IMI arrives at this counter. The eight most significant output lines of the counter CN1 are shown in the data lines P1-P4 of the counters BC-4-BC-5 formed by the connected bidirectional counter CN2. The signals coming along these latter lines are applied to the output lines of the counter CN2 whenever a signal from line IM2 enters this counter. As shown in the figure, each counter BCI-BC5 is connected in series in a known manner.

Figure 7 is a block diagram of another embodiment of the present invention. In this embodiment, there are signal generators PG3 and PG4, of which PG3 corresponds to transducer 103 and PG4 to transducer 105. Signal generator PG3 transmits output signals to two channels, which are input to output lines X3 and Y3. These signals are similar to those sent by the pulse generator PG1 to lines X and Y (Fig. 5). · In addition, the signal generator PG3 transmits an index signal to line IM3 which moves from the first plane to the second whenever the first fixed point of the shaft 101 is in the first angular position and then moves from the second plane to the first. each time the first fixed point of the shaft 101 rotates 180 ° from the first angular position. This index signal is input via line IM3 to signal modulator C0ND2 as well as signals from lines X3 and Y3.

The signal generator PG4 sends to the line IM4 an index signal which moves from the first plane to the second each time the second fixed point of the shaft 106 is in the second angular position, and moves from the second plane to the first each time the second fixed point of the shaft 106 rotates 180 ° from the second angular position. This index signal is input via line IK4 to the signal modulator C0ND2.

The signals sent by the signal generator PG3 to lines X3, Y3 and IM3 and by the signal generator PG4 to line IM4 are applied to the C0ND2 circuits of the signal converter 10 64998, where they provide signals to the bidirectional counter CN3 of lines 3Q11, IM3BSTB, U10 and 4XTO. In addition, the signal generator C0ND2 also generates signals which are input via lines BE, 3ΪΓ, and IM4BSTB to ports X0R8 and K0G4 and to the bidirectional counter CN4. The signal of line U10 is also fed to the bidirectional counter CM4.

The output signals of the counter CN3, which show the angular position of the first fixed point of the shaft 101, are applied to the lines 3PO-3BH. Counter CN3 also receives a "memory" signal, which is applied via line CO3O to counter 0X4 each time counter CM3 returns to its initial state after receiving a predetermined number of pulses. This reset occurs in the same manner as shown for counter CN1 in Figures 5 and 6. Line 3PH the signal is also input to port M0G4 and interacts with the BE signal at line N0G4 to generate an output signal along port C040 to the total adder ADD1.The totalizer ADD1 generates signals input through the lines 4P4-4P10 to the bidirectional counter CN1. signals added through lines 4P4-4P10 to bidirectional counter CN4 In addition, the totalizer ADD1 generates a signal input through line 4PHA to port X0R8, signals from ports 4P11A and BE to port X0R8 cause it to operate, and it generates an output signal to line 4H to counter CN4.

The bidirectional counter CN4 responds to the "memory" signals from line 0030 by generating output signals for lines 3P12-3 = 19 indicating the number of received "memory1 signals. In addition, the signal input to the counter CN4 via line IM4 causes it to send from sum total ADD1 and port X0R8. The signals it receives via 4P4-4PH for lines 3P12-3P19 »so if these latter lines do not have similar signals before, now it is.

Figure 8A shows the circuit elements formed by the signal generator C0ND2. The signal generator C0ND2 has several buffer amplifiers of the model Fairchild "differential double line amplifiers", type AM96I5 or similar, which receive signals from the pulse generators PG3 and PG4 along the lines X3, Y3 »IM4. Amplifier B1 and B2 generate a pulse on line X3B and Y3B for each period of the signal applied to lines X3 and Y3 in a known manner. Amplifier B3 and B4 generate a pulse on lines IM3B and IM4B for each signal on lines IM3 and IM4. In addition, the signal processor 00ΝΌ2 has several "C0S / M0S 4-hit D-type registers" DIC1 and DIC2, which are model RCA CD4076BE or similar. Units DIC1 and DIC2 generate signals on lines X3B1, X3B2, Y3B1 and Y3B2 in response to signals from lines X3B, Y3B and IM3B and IM4B.

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Figures 8A and 8B also show a plurality of exclusive OR ports X0R1-X0R8 of Motorola's "Quad Exclusive Or" type MC14507 or equivalent; multiple AND gates NND2-NND3 of Motorola's "Quad Two Input Nand Gate" type MC14011 or equivalent; several Non-OR ports N0G1-N0G4 of Motorola "Quad Two Input NOR Gate" type MC14001 or equivalent, and inverting amplifiers IA3-IA5 of Motorola "Hex Inverter" type MC14049 or equivalent.

Signals from register DIC1 via lines IM3B1 and IM3B2 are input to the exclusive OR port X0R1 (Fig. 8A), the output signal of which is input to the counter BHDI-BUD3 (Fig. 8B).

The idle type oscillator 0SC2 generates pulses at a frequency of 131 kHz, which are applied to lines CL01 and CL01. The pulses of line CL01 are the complements of the pulses of line CL01. Line CL01 is connected to counter BUD1-BUD5 (Figure 8B). Line CL01 is connected to register DIC1. At least four pulses are generated for line CL01 for each quarter of the signals of lines X3 and Y3 at the maximum speed of the signal generator PG3, so that the equipment to be described later can generate four pulses as a result of each such period.

Figure 8A also shows an exclusive OR gate that receives signals from register DIC1 via lines X3B1 and Y3B2 and outputs signals to input B of a binary coded decimal / decimal decoder BCD3 (model Motorola MC14028 or equivalent). In addition, signals BIC3 receives signals from unit DIC1 (input A) and along line X3B2 (input C). As shown, the signals from the output lines No. 1 and 4 of the unit BCB3 are input to the input of the NO gate N0G1, and the signals of the output lines No. 2 and 7 of the unit BCD3 are input to the input of the NO gate N0G2. The signals generated by the NOT gates N0G1 and N0G2 are input through lines 4XB and 4XB to inverting amplifiers IA3 and IA4, which generate signals for lines 4XB and 4XD that are four times the signals of lines X3B and Y3B. The signal of line 4XB is also applied to one of the inputs of the NAND gate NND2; the second input of this port is connected to line U10 to generate a binary signal, and this signal is input along line U10 to counters CN3 and CN4. Respectively, signals come to the AND gate NND3 via lines 4XB and U10 to generate signals from line D10.

The OR gate NOG3 connects the signals input to it via lines 4XB and 4XB and sends signals via line 4XNB from the three binary UP / DOWN counters BUD1, BUD2 and BUD3 (Figure 8B, all Motorola MC14516 or similar) formed by counter CN3. As shown in Fig. 12 64998, signals are input to the exclusive OR gate via lines IM3B2 and D10, and the gate generates a signal to its output line which is applied to the second input of the exclusive OR gate X0B6 (the second input is connected to ground). The output line 3QH of the exclusive OR gate X0R6 is connected to the counter CN3 (Figs. 7 and 8B). The other input lines of the counter CN3 (Fig. 8B) are all connected to ground.

The bidirectional counter CN3 is connected on line CO3O to a series counter CN4 with a pair of UP / DOWN counters BUD4 and BUD5 connected in series. Each of the UP / DOWN counters BUD4 and BTJD5 is also a Motorola MC14516 or equivalent. In addition to generating signals for lines 3PO-3PII indicating the angular position of the first fixed point of the axis 101, the counter CN3 sends the eight most significant bits via lines 3P4-3BII to the binary adder ADD1.

The ADD1 binary totalizer has two series-connected "four-bit totalizers" ADDA and ADDB (model Motorola MC14008 or equivalent). As shown in Fig. 8B, the data inputs A1-A8 of the totalizer ADD1 are connected to ground. The summing ADD1 receives a "memory" signal along line C040 from the output of the OR gate N0G4. Signals are received at the OR gate N0G4 via lines 3B11 and BE. The signal coming through line BE is generated in the inverter IA5 and is the complement of the signal generated by the exclusive OR gate X0R7 (Fig. 8A) in response to the signals input thereto via lines IM4B2 and D10.

The counter CN4 responds to that pulse signal along the line IM4BSTB by exporting the signals received from the lines 4P4-4B11 to the lines 3P12-3P19 »if the latter lines do not already have corresponding signals. The signal on line 4 ^ 11 generated by the exclusive OR gate X0R8 in response to the signals input through lines BE and 4P1LA, and the rest of the signals on lines 4BO-4PII obtained directly from the adder ADD1, represent in binary form the number of revolutions made by the first fixed point of axis 101.

In order that the operation of all embodiments of the invention may be understood, a description of the operation of each is provided. Accordingly, it is assumed that when the first fixed point of the shaft 101 of the apparatus constructed according to Figs. 2, 3 and 4 is in the first angular position and the second fixed point of the shaft 106 is in the second angular position, the binary encoders corresponding to the transducers 103 and 105 both form a gray code output. which corresponds to zero. From the above, it can be understood that the encoder on the shaft 101 generates 2048 discrete 11-bit signals as its gear 102 passes through 255 teeth, or $ 60 degrees. The encoder of the shaft 106 also generates a separate output signal 2048 when its gear 104 rotates 3 ^ 0 degrees. However, this gear has 256 teeth, and each time the gear 102 rotates 283 teeth, the gear 104 also rotates 255 teeth, which is one tooth less than 360 degrees for the gear 104. Therefore, the encoder of the shaft 106 generates eight output signals less than the encoder of the shaft 101. for each revolution of the latter shaft.

From the above, it can also be understood that due to the discrete nature of the output signals of the encoders on the shafts 101 and 106, the signals of the encoders are out of sync with each other, except each time the first fixed point of the shaft 101 is in the first angular position. The asynchronity of the signal generation of the encoders is compensated so that the angular position of the fixed point on the shaft 101 is correctly indicated in all positions of this shaft as it rotates. The following functional description is presented for one specific position of the shaft 101 in order to understand how the embodiment accurately indicates the angular position of the first fixed point on the shaft 101.

Since the gear 104 travels one tooth less than the gear 102 for each revolution of the gear 102, it is also understood that the angular position of the second fixed point on the shaft 106 with each successive rotation of the shaft 101 increasingly lags behind the angular position of the first fixed point on the shaft 101 if is started with the first fixed point in the first angular position and the second fixed point in the second angular position. The pitch angle increases the same with each revolution and thus indicates the number of revolutions made by the shaft 101.

In order to understand how the embodiment of Figures 3 and 4 works in detecting the angular position of the first fixed point on the shaft 101, it is assumed that the shafts 101 and 106 are rotated so that the first fixed point is in the first and the second fixed point in the second angular position. It is further assumed that the shaft 101 is currently performing a certain rotation and that the first fixed point has traveled more than seven-eighths of the distance of that rotation since the first angular position.

Under these conditions, the AREG register receives, via lines EA0 to EA10, signals indicating by gray code the angular position of the first 14 64998 of its fixed point on this particular rotation. At the same time, signals are indicated on the selector switch SW3 via lines EB0-EB10, which indicate with a gray code the position of the second fixed point on the axis 106. It is also assumed that the timing signal generator TSIG has just generated a new pulse on line OLOA and that a corresponding pulse has not yet been generated on line MA. As a result, there is still a pulse on line MB, and the switch SWB brings the signals of lines EB0-EB10 to lines BG0-BG10. Similarly, when the OLOA signal was generated and the BREG D-type flip-flop of the register caused lines BG0-BG10 signals to be generated on lines SB0-SB10, signals indicating the angular position of the second fixed point of the shaft 106 are input to the second input group of the gray / binary transducer BOON. As a result, after a sufficient time, the timing signal generator TSIG generates a pulse on the line MA and the converter BOON generates signals on the lines B0-B10 which indicate with a binary code the angular position of the second fixed point of the shaft 106.

After generating the line MA, the pulse timing signal generator TISG also generates a pulse for the line CLOB. The register's AREG D-type flip-flops, in response to the CLOB pulse on the line, cause the 11 gray code signals input to them via lines EAO-EA10 to be generated on lines AG0-AG10. In addition, the complements of the signals of lines EA3 and EA10 of lines AGJ and AGIO are formed. The three least significant bits of the signal indicating the angular position of the first fixed point of the shaft 101 with the gray code are input along the lines AG0-AG2 to the gray binary converter ACON. These signal bits, together with the complement of the fourth most significant bit, which is input to the ACON converter via line 5 ^ 3, form the complements of the four least significant bits on lines CA0-CA3 with the binary code, which correspond to the four least significant bits in gray code. The seven most significant gray code bits generated by the encoder on the shaft 101 are input via lines AG4-AG10 to the ACON converter, which generates the most significant binary code bits for lines CA4-CA9 5-9 corresponding to the corresponding bits of the gray code position signal. The eleventh, or most significant, bit does not need to be converted from gray code to binary because it is always the same in both. The most significant bit of line AGIO and the next six most significant bits of lines CA4-CA9 are applied to gates GAA, which in the presence of a pulse from line MA form as binary codes for lines A4-A10 the seven most significant bits of signals indicating the first fixed on axis 101.

At the same time, the signals of the lines CAO-CA3 are applied to the selector switch EWA, which, when no pulse comes from line MB and pulse comes from line MA, transmits to these output lines AO-A3 these four signals corresponding to the four least significant binary code signals on axis 101. complements of the significant bit. The complements of the eleven binary code signal bits indicating the position of the first fixed point on the axis 101 are introduced through lines A0-A10 to the second input group of the subtraction circuit SUBT. As explained above, the subtraction circuit SUBT also simultaneously receives binary coded signals to its second input group from lines B0-B10. These latter signals indicate the angular position of the second fixed point on the shaft 106. When there is no pulse from line KB, the subtraction circuit SUBT acts as a summing circuit that adds the signals of lines B0-B10 to the signals of lines A0-A10. As already described, the signals of lines A0-A10 are complements of the binary signals indicating the angular position of the first fixed point on the axis 101. Therefore, the subtraction circuit SUBT generates a binary signal on lines S0 to S10 indicating the difference between the signals representing the angular position of the second fixed point on the axis 106 and the signals representing the angular position of the first fixed point on the axis 101, i.e., the angle by which the angular position of the second fixed point 106 is behind the angular position of the first fixed point on the shaft 101.

When the shaft 101 is in the last eighth of any revolution, as in the assumed situation, the asynchronousness of the signal generation of the encoders causes the difference signals on lines S0-S10 to indicate an incorrect number of revolutions on the shaft 101. This is because when the encoder on the shaft 101 generates a signal before the encoder on the shaft 106 has generated a corresponding signal, the former encoder has generated eight more signals on the shaft 101 than the latter encoder. It will be appreciated from the foregoing description that the eight signals correspond to one tooth of the gear 104. Therefore, these eight signals indicate that the second fixed point on the shaft 106 is behind the first fixed point on the shaft 101 at an angle corresponding to a full turn. Since this occurs before the end of the turn, it must be prevented from causing the inaccuracy of the number of turns performed by the first fixed point on the shaft 101 caused by the difference of the signals input to the subtraction circuit SUBT after the first angular position. The switch SWB, the register BREG, the converter BOON, the subtraction circuit SUBT and the switch SWA act as a compensating circuit when pulses come from the line MB in order to obtain correct readings at such times.

16 64998 To provide this compensation function, the output signals input from the subtraction circuit to the lines SO-SIO are input to the second input group of the switch SEB. Therefore, before a pulse comes from the line MB and when a pulse still comes from the line MA, the omission angle signals from the subtraction circuit SUBT are input to the output lines BG0-BG10 of the switch SWB. When a pulse is generated on the line CLOA at the end of the pulse of the line MA, the eleven D-type flip-flops of the BREG register cause the complementation of the omission angle signals to the lines SBO-äBlÖ. These signals are fed to the BOON converter. It acts as a selector switch and transmits these comps. BO-BIO.

When the pulse of the line MA has ended and the pulse of the line MB has started, the gates GAA are in the inhibit state and thus each of the lines A4-A10 becomes a bi-digital unit. In addition, the switch SWA selects the input signals of the lines E1 +, AGIO, CA9 and CA8 in response to the pulse of the line MB and transmits these signals to its output lines AO-A3 '. The signals of lines CA8, CA9, and AGIO represent the complements of the three most significant bits of the binary number indicating the position of the first fixed point on the axis 101. At each revolution of the shaft 101, as its first fixed point travels from the last eighth of the revolution to the first angular position, the signals indicating these three most significant bits form a compensation signal of a magnitude such that when subtracted from the omission angle signal generated during the MA pulse. synchronism is prevented from causing a omission angle signal that would give an inaccurate position indication. This subtraction is accomplished by applying the binary signals of lines A10-A4 and the binary signal of line A3 from the binary one signal on line E1 + together with the complements of the three most significant bits of the binary code signal representing the first fixed point position from lines A0-A2. When these signals are input to the second input group and the complement of the omission signal is input from lines B0-B10 to the second input group, and when a pulse comes from line MG, the subtraction circuit SUBT forms the difference between the omission signal and the compensation signal on lines S0-S10. The eight most significant bits on lines S3-S10 are input to the eight D-type flip-flops of register 2ST0. When the next pulse is generated on the CLOP line, these generate output signals for the lines R11-R18, which accurately indicate the number of teeth of the gear 104 by which the angular position of the second fixed point on the shaft 106 lags behind the angular position of the first fixed point on the shaft 101.

II

17 64998 positions. As mentioned above, this indicates the number of revolutions at which the first fixed point on the shaft 101 has rotated from the first angular position after the initial assumption that the first fixed point was in the first angular position and the second fixed point in the second angular position. When the binary number represented by the eight bits on lines R11-R18 is combined with the eleven bits on lines R0-R11, a number is obtained indicating the angular position of the first fixed point of the shaft 101 and the number of revolutions of the shaft 101.

It should be understood that although the pulse on line MB ends and the pulse on line MA begins at substantially the same time as the pulse on line CLOB, the subtraction circuit SUBT shifts its output from the compensated omission signal to the uncompensated signal in response to the termination of the MB pulse so much slower that the compensated signal register 2ST0 as outputs of eight D-type flip-flops.

In order to understand how the embodiment of Figs. 5 and 6 works in indicating the angular position of the first fixed point on the shaft 101, it is assumed that the first fixed point of the shaft 101 is in the first angular position and the second fixed point of the shaft 106 is in the second angular position, and that the pulse generators PG1 and PG2 form simultaneously their index pulses on lines IMI and IM2. It is further assumed that the shafts 101 and 106 rotate in the direction in which the binary counters CN1 and CN2 increase their readings as the angular rotation of the shaft 101 increases. From the above, it can be understood that the pulse generator PG1 generates 1024 pulses on both lines X and Y with each revolution of the shaft 101. Also, when the rotation of the shaft 101 increases the reading of the counters CN1 and CN2, the pulses of the line Y are the pulses of the line X as mentioned above.

It is to be understood that the ratio of the pulses generated by the oscillator OSC to the lines CLO and CLO to the maximum rotational speed of the pulse generator PG1 is such that both lines CLO and CLO receive at least four pulses between each pulse generated on line X and each line Y. As a result, for each pulse of the lines X and Y, output signals are generated in the D-type flip-flops IX and 2X and 1Y and 2Y for the lines X1, X2, Y1 and Y2. These output signals are applied to the exclusive OR gates N01, NO2 and NO3, the outputs of which in turn are applied to the three inputs of the decoder BCD. Since the signals of line Y are formed 90 degrees before the signals of line X, the signals come to lines Y1, Y2, X1, and X2, respectively. Pulse generation on line Y1 causes an exclusive OR gate N01 to bring signal 18 64998 to input A of decoder BCD A. This results in a corresponding signal to decoder output 1. This is sent to its own LI-OR and inverter ports U1 and U2, and causes pulse generation on line 4U. Correspondingly, generating a pulse on line Y2 causes the exclusive OR gate NO2 to generate a signal at input B of decoder BCD, which is irrelevant this time because output 3> of decoder BCD, which generates an output signal when input signals are applied to inputs A and B of decoder, is not connected. . Pulse generation on line X1 causes the off-gate OR gate NO3 to cause a signal at inputs A, B and C of the decoder BCD, it generates an output signal at its output 7 · This is applied to the respective NO-OR and inverter gates U1 and U2 where it causes 4U second pulse.

When the pulse of line X2 is applied to the OR gates NO1, NO2 and NO3, each of them stops generating an output signal. The clock pulse introduced along the line CLO then causes the D-type fli-flop 1Y to remove the pulse signal from the line Y1. This causes the exclusive OR gate NO1 to again generate a signal at input A of the decoder BCD. As before, this causes a pulse on line 4U. Deletion of the pulse signals from lines Y2 and X1 causes a pulse at the output 7 »of the decoder BCD, respectively, and a pulse is sent again at line 4U. In this way, each signal cycle to line X and Y corresponds to four pulses to line 4U, so that each rotation of the signal generator PG1 in the assumed direction causes 4096 pulses to line 4U, which means that 16 such pulses are generated during a rotation angle corresponding to one tooth 102.

Each pulse going to line 4U causes the NO gates NAI and NA2 to generate corresponding pulses to line UD. These pulses on the line UD are known to cause the binary up-down counters BC1-BC5 to increment their reading each time an exclusive OR gate N04 enters a pulse at the input of the counter BC1 CI1 as a result of the line 4U pulse.

The outputs are applied to lines PP0-PP11 according to how many pulses are applied to the input CI1 of the counter BC1 and the counters BC1 and BC2 are filled. When 4096 pulses have been generated on line 4U, all counters BC1-BC3 are filled with the result that an output signal is generated at the output CO3 of the counter BC3. This is applied along line CO to input CI4 of counter BC4, and this counter together with counter BC5 generates output signals for lines PP12 to PP19 via line CO according to the number of signals entering input C14.

Whenever the first fixed point on the axis 101 returns to the first angular position, the line 4U should have received 4096 pulses so that the counters BC1-BC3 have returned to their initial state, where they form a zero pulse on the lines PP0-PP11. To ensure that counters BC1-BC3 return to their initial state when the first fixed point on the axis 101 returns to the first angular position, regardless of whether one or more pulses are not read, an index pulse is generated on the line IMI when the fixed point of the axis 101 is in the first angular position. This index pulse is applied via the line IMI to the input PE of each counter BC1-BC3, whereby the ground potential of the counter lines P1-P4 is transferred to the output lines PPO-PP11, which resets the counters if they are not already in this state.

As will be appreciated, the angular position of the fixed point of the shaft 101 is increasingly ahead of the angular position of the fixed point of the shaft 106 with each rotation of the shaft 106, because the gear 104 has one tooth more than the gear 102. Especially each time the second fixed point of the shaft 106 returns to the second angular position and the signal generator PG2 sends an index pulse to line IM2, the fixed point of the shaft link 101 has passed the first angular position exactly the distance corresponding to one tooth of the gear 102. This phenomenon is cumulative, and arranging the binary counters BC1-BC3 to generate four output signal bits each, along with the fact that line 4U outputs 16 pulses during the rotation angle of the shaft 101 corresponding to one tooth of each gear 102 each time the signal generator PG2 and BC3 is a number corresponding to the number of gears the gear 102 has rotated since the first fixed point of the shaft 101 was last in the first angular position. This number corresponds to the number of revolutions of the shaft 101. It is transferred to the output lines PP12-PP19 of the counters BC4 and BC5 as a result of the second index pulse applied to the inputs of the counters BC4 and BC5 via the line IM2, since, as is known, the introduction of such a pulse transfers the signals of the lines PP4-PP11 to the lines PP12-PP19 so that corresponding pulses, so now they come.

It can be seen from the above that if the counters BC4 and BC5 do not count the "memory" signals from the counter BC3 via the line CO properly, the counters BC4 and BC5 are corrected as soon as the signal generator PG2 generates its index pulse in response to the second fixed point of the shaft 106 position. Correspondingly, if the electric current is lost in any revolution of the shaft 101, the correct number of revolutions made by this axis from the point where both the first and second index pulses were formed synchronously and the correct indication of the angular position of the first fixed point on this axis when the second index pulse IM2 after the line IMI in become the first index pulse after reconnecting the power.

This operation of the embodiment in such a direction of rotation of the shafts 101 and 106 that the counters reduce the numbers stored therein occurs as a result of pulses on line 4DN being generated in the same manner as signals generated on line 4N in response to line X signal above line Y signal. During this operation, the readings of the counters BC1 to BC5 decrease as a result of no pulses coming from the line UD. These functions will be apparent to those skilled in the art from the foregoing and will not be explained in detail herein for brevity.

In order to understand how the embodiment of Figs. 7, 8A and 8B operates in detecting the angular position of the first fixed point on the shaft 101, it is assumed that the first fixed point of the shaft 101 is in the first angular position and the second fixed point of the shaft 106 is in the second angular position. It is further assumed that due to the assumed positions of the fixed points of the axes 101 and 106, the signal generators PG3 and PG4 have generated signals which have simultaneously shifted from the first logic level corresponding to the binary one to the second logic level corresponding to the binary zero. Furthermore, it is assumed that the signal applied to line IM3 remains at this binary zero plane until the first fixed point of the axis 101 rotates 180 ° clockwise from its first angular position, and that the signal applied to line IM4 remains at this logical zero level until the second fixed point of the axis 106 rotates 180 ° from the second angle. from their counterclockwise position, and that in this position of the shafts 101 and 106 the signals going to the lines IM3 and IM4 move to the logic level corresponding to the binary unit. It can be understood that since the gear 102 has one tooth less than the gear 104, the second fixed point of the shaft 105 is increasingly lagging behind the first fixed point of the shaft 101, and this phenomenon increases with each revolution of the shaft 101.

It is assumed that as the shaft 101 rotates every 36Ο degree rotation, the signal generator PG3 generates 1024 electrical signal cycles on each of the lines X3 and Y3, and further that when the shaft 101 rotates clockwise, the signals of line Y3 are 90 ° ahead of the signals of line X3. It can be understood that when the axis 101 rotates counterclockwise J, S0 degrees, the signal generator PG3 again generates 1024 signal cycles on both lines XJ> tl 64998 and Y3, but now the signals of line Y3 are 90 ° behind the signals of line X}. From this phase ratio of the signals input to lines X3 and Y3, the signal shaping circuit C0ND2 determines the direction of rotation of the shaft 101 as it rotates, and in response to the assumed clockwise rotation of the shaft 101, it sends binary one signals to the output of the AND gate NND2 as described. These signals are applied via line U10 to bidirectional counters CN3 and CN4 which increase their readings in response to pulses coming to counter CN3 via line 4XUD when the angular position of the shaft 101 rotates counterclockwise. If the assumed direction of rotation of the shaft 101 were the opposite AND gate 1TND2 would have sent a binary zero signal to the counters CN3 and CN4 as a result of the signals coming to line Y3 lagging behind the signals of line X3, and the count of these counters would be reduced in response to counter 4

As a result of the assumed initial position, binary zero level signals are input to the inputs of the inverting differential amplifiers B3 and B4 (Fig. 8A) via lines IM3 and IM4, and these amplifiers send binary one signals to register DIC2 via lines IM3B and IM4B. Before axis 101 rotated from its assumed initial position, lines 4XN and 4XL had no signals, and therefore the output of the exclusive OR gate X0R4 was binary zero, and the signals of lines IM3B and IM4B were not input to register DIC2. Therefore, binary zeros were introduced on lines IM3B1, IM3B2, IM4B1, and IM4B2, which went further to the exclusive OR gates X0R1 and X0R2, each of which generates a binary zero signal.

Before the shaft 101 begins to rotate clockwise, the signal generator PG3 supplies the signal of the line Y3 to the input of the differential amplifier B2 inverting the negative half of the first period. This causes the amplifier to generate a single signal for data line Y3B to register DIC1. The register DIXC1 responds to this signal on line Y3B and on the clock pulse from line CL01 by generating a signal on line Y3B1 which is input to the binary-to-decimal converter BCD3. This signal causes a binary one signal to output 1 of the converter, which is applied to the corresponding input of the OR gate N0G1. This port, in turn, generates a binary zero signal on line 4X1, which is input to an inverter IA3, which sends a binary one signal to line 4XU. Each binary one signal of line 4XN is input to the AND gate NND2, which sends a binary one signal to line U10. Each binary one signal of line 4XN is also applied to the exclusive OR port X0R4. The first of these is introduced into the register DIC2 so that it generates a binary one signal on lines IM3BI and IM4B1 in response to lines IM3B and IM4B

22 64998 for binary one signals. These binary one signals of lines IM3BI and IM4B1 are fed to the exclusive OR gates X0R1 and X0R2, which form the binary one signals of lines IM3BSTB and IM4BSTB.

The binary one signal of line 4XU was also applied to the NO gate NOG3, where it caused a binary one signal to line 4XND, which is applied to the input CIN1 of the counter BUD1. However, this signal has no significance this time, because the binary one signal applied to the inputs PE of the counters BUD1-BUD3 via line IM3BSTB causes the ground or binary zero signal of lines 3Q0-3Q10 to also be applied to lines 3PO-3P10. At the same time, there is also a binary zero signal on line 3QH, which results in the entry of binary zero glass signals to OR gate X0R5 via lines IM3B2 and D10. Counter BUD3 transmits this line 3QH signal to line 31 * 11 in response to signal b3 coming from line IM3BSTB.

The adder ADDA and ADDB send the signals of lines 3 ^ 4-3 ^ 11 to lines 4P4-4B11 as a result of the signal coming from line C040 being in a binary zero state. This state is due to the fact that the binary zero signal comes from the line 3 ^ 11 to the NO gate N0G4, which also receives the binary one signal from the line 3E. This latter signal is in binary one state because binary zero signals come from lines IM4B2 and D10 to the exclusive OR gate X0R7. As a result, the signal on line BE is in binary zero state. This signal and the binary zero signal of line 4B11A are both input to the exclusive OR gate X0R8 (Fig. 8B), where they cause a binary zero signal to be sent to line 4P11. Under these conditions, the binary zero signal on the IMB4STB line causes the counters BUD4 and BTJD5 to send the binary zero signals to the lines 3P12-3P19 · When all lines 3PO-3PI9 have binary zero signals, the counters BUD1-BUD5 are all alkud-BUD5. The additional pulses from line CL01 have no significant effect as long as the shaft 101 remains stationary. The first such additional pulse from line CL01 causes register DIC1 to send a binary one signal to line Y3BI. This is input via the exclusive OR gate XOR3 to the 3-input in the converter BCD3, which returns the binary one signal of input 1 to binary zero. This causes the NO gate N0G1 to generate a binary one signal on line 4XB and a binary zero signal via inverter IA3 on line 4XB. This binary zero signal causes the exclusive OR gate X0R4 to generate a binary zero signal that has no effect.

23 64998

Assume then that the shaft 101 begins to rotate clockwise. As mentioned above, the signals of line Y3 are then J0 ° above the signals of line X. In order to understand how the signals of the generators PGJ and PG4 cause the counters MUD1-BUI> 5 to generate output signals describing the rotation of the shaft 101, the generation of pulses on the line 4XUD will be briefly described below.

The next significant skull pulse introduced to register DIC1 via line CL01 comes when a binary one signal from line X3B enters this register. This clock pulse causes register DIC1 to send a binary one signal via line X3B1 to the second input of the exclusive OR gate XOR3. As a result, the exclusive OR gate X0R3 sends a binary zero glass signal to the input B of the converter BCD3. It can be understood that the input A of the converter BCD3 still receives a binary one signal from the line Y3B1. As a result, the converter BCD3 sends a binary one signal to its output line 1, which is applied to the NO gate N0G1, where it causes a binary one signal to line 4XN and a binary zero signal to line 4TU. This binary one signal of line 4XU is applied to the exclusive OR port X0R4, which causes register DIC2 to send the binary one signals of lines IM3BI and IM4B1 to lines IM3B2 and IM4B2. These latter two signals cause the binary one signals of lines IM3BSTB and IM4BSTB to be converted to binary zero signals so that counters CN3 and CN4 can count the pulses coming to line 4XBB.

The next clock pulse in register DIC1 causes it to send a binary one signal via line X3B2 to input C of converter BCD3. In response to a binary one signal coming to input C, converter BCQ3 the binary one signal changes to binary zero.

Since the signals coming to line Y3 are signals of line X3 due to the above assumed direction of rotation, it can be understood that at the end of the first half cycle of the signal coming to amplifier B2 via line Y3, this amplifier sends a binary zero signal via line Y3B to register DIC1. After the binary zero signal coming through line Y3B, the first clock pulse coming to register DIC1 causes this register to send the binary zero signal of line Y3B via line Y3BI to input BCD3 of converter 1. It can be understood that 64998, and in addition, via line XJB2, a binary one signal goes to input C of converter BCD3. Thanks to the signals coming to the converter BCD3, the converter sends a binary one signal from its output line 4 to the OR gate R0G1, which sends a binary one signal to the line 4XB. The next clock pulse causes register DIC1 to send a binary zero signal on line Y3B1 to line Y332. As a result, the exclusive OR gate X0R3 sends a binary one signal to the input B of the converter BCR3, and this converter in turn generates a binary zero signal for each of its output lines 1, 2, 4 and 7 ·

It can be further understood that as a result of the continuous clockwise rotation, a binary zero signal is obtained from the amplifier B1 via the line X3B to the register DIC1. The next clock pulse entering the register DIC1 causes it to send a binary zero signal on line X3B to one of the inputs of the exclusive OR gate XOR3 via line X3BI. In this case, it can be understood that the binary zero signals come via line Y3B2 to the second input of port XOR3 and via line Y3BI to converter BCD3. At the same time, a binary one signal comes from the line X 1 B2 to the input C of the converter BCD3, and as a result, the converter sends a binary one signal from its output 4 to one input of the OR gate N0G1. As a result, a binary one signal is output on line 4XR. When the next clock pulse enters the register DIC1, it causes the register to send a binary zero signal on line X3B1 via line X3B2 to the input C of the converter BCD3. N0G1 and NOG2.

From the above, it can be understood that each binary one signal coming to the NO gate causes a corresponding binary one signal to be transmitted on line 4XU. Thus, when the signals of line Y3 are ahead of the signals of line X3, line 4XB receives four pulses for each signal period coming from line Y3 to amplifier B2. Correspondingly, when the signals of line X3 are above the signals of line Y3, four pulses are applied to line 4XD for each signal period coming from line X3 to amplifier B1.

As shown in Fig. 8A, the signals of lines 4XU and 4XD come to the input of the NOG3 port of the NO gate. As a result of the above, it can be understood that the NO gate sends 4096 pulses for each revolution of the shaft 101 via the line 4XUD to the input of the counter CN3 regardless of the direction of rotation of the shaft 101.

Il 25 64998

It is to be understood that the output of the counter CN3 denotes the position of the first fixed point on the shaft 101 and the counter CN4 denotes the number of revolutions of this shaft. As the shaft 101 rotates in the assumed direction, the counter CN3 responds to the signals from the line 4XND, while the counter CF4 responds to the signals from the line C030 in the normal manner of the pulse accumulators, as shown in the counters CN1 and CK2 of the embodiment of Figs. However, as will be shown, if either counter misrepresents the position of the first fixed point of the shaft 101, corrections are made to both counters with each revolution of the shaft 101.

To describe the operation of the correction signals, it is assumed that the first fixed point of the shaft 101 rotates 180 ° from the assumed initial position in which it was in the first angular position. It is now understood that line 20XUD has received 2048 pulses as the counter CNJ sends a binary number corresponding to the decimal number 2048 to lines 3PO-3PII as a result of counting each 2048 pulse.

If, for some reason, the signals on the lines 3 ^ 0-31 * 11 representing the pulses received by the counter CN3 are erroneous, these signals are corrected as follows when the fixed point of the shaft 101 is 180 degrees from its first angular position.

Whenever the axis 101 rotates 180 ° clockwise from its first angular position, a corresponding pulse travels along the line 4X1® to the input of the counter CN3 almost simultaneously as the signal from the pulse generator PG3 to line IM3 is changed from binary zero to binary one level as described above. As a result, the differential amplifier B3 (Fig. 8A) sends a zero-level signal to the data line IM3B of the register DIC2. At this time, the binary one signal of line 4XN coming to the exclusive OR gate X0R4 causes the register DIC2 to transmit the zero-level signal of line IM3B to its output line IM3BI. As will be understood from the above description, the line IM3B2 then has a binary one signal as a result of the line IM3B having a stagnant binary one signal as the axis 101 rotates 180 °. The binary one-level signal of line IM3B2 and the binary zero-level signal of line IM3BI cause the exclusive OR gate X0R1 to generate a signal which is input along line IM3BSTB to counter CN3, which sends a ground or binary zero signal from lines 3QO-3Q10 to line 3QO-3Q10. At this time, the binary one signal of the line IM3B2 also enters the exclusive OR gate X0R5 »which together with the port X0R6 forms the binary one signal via the line 3QH to the counter CN3.

26 64998 This binary one signal of line 3QH and the binary zero signals of lines 3Q0-3Q10 are applied to the output lines of the counter CN3 due to the signal from line IM3BSTE, so if these output lines do not already have similar signals, now they become. Therefore, the counter correctly displays in binary form the number of pulses entering its input via line 4XUD during a 180 degree rotation. The counter CTTJ is able to continue counting due to the next pulse coming from line 4XB, as it converts the binary one signal of line IM3B2 to a binary zero signal, which causes a binary zero to appear on line IM3BSTB. This latter signal returns the counter CN3 to a state where it can count the pulses it receives from the line 4XBD.

Similarly, each time the first fixed point of the shaft 101 returns to the first angular position, the display of the counter CN3 is also corrected to the initial zero reading. Under these conditions, the signal on line IM3 changes from binary one to binary zero. This is introduced as a clock in register DIC2 in response to a pulse coming from line 4XB at the same time, and a binary unit is output to lines IM3BI and IM3BSTB. The signal of the latter line allows the ground or binary zero signals of lines 3Q.0-3Q10 to come to lines 3PO-3PIO. The binary zero signal also comes to line 30.H »because both line IM3B2 and line D10 have binary zero signals at this time. Thus, all lines 3PO-3PII have binary zero signals denoting the original zero reading.

Correction of the reading of the counter CN4 is provided, if necessary, each time the second fixed point on the shaft 106 is in a second angular position and 180 degrees away from this position. The first of these remedies is similar to the embodiment of Figures 5 and 6. However, in order to perform the correction in the 180 degree position, there are additional devices in the apparatus, the operation of which is explained with respect to both correction functions.

Whenever the second fixed point of the axis 106 is in the second angular position, the signal of the line IM4 is changed from a binary unit to a binary zero. This causes a binary unit on line IM4B1 due to a simultaneous pulse on line 4XB. This binary one signal on line IM4B1 causes a corresponding binary one signal on line IM4XBSTB. As previously mentioned, this causes the signals of lines 4P4-4PH to be transferred to lines 3P12-3P19 of the counter CLT4, so the former signals come to these lines unless they already have corresponding signals. It will be apparent from the description of the apparatus of Figures 5 and 6 that when the second fixed point of the shaft 106 is in the second angular position, the reading of the counter CN3 represented by the output lines 3 ^ 4-3 ^ 11 indicates the number of times the first fixed point of the shaft 101 has passed the first fixed position. past the angular position. This number is correct as the output of the counter NN4 in each revolution of the axis 101, and is passed to the counter CIT4 in response to the binary one signal of the line IM4BSTB, unless it is already transmitting this number. This is because the adder ADD1 receives a binary zero signal from the OR gate N0G4 and the exclusive OR gate X0R8 receives a binary zero signal from the line BE. Thus, the signals of lines 3P4-3PH are simply transferred to lines 4P4-4P11, from which the counter CN4 forwards them to lines 3P12-3P19 · The signal of line BE is binary when the second fixed point of the axis 106 is in a different angular position, because the signals of lines IM432 and D10 are zero here. in the assumed direction of rotation. When the signals of lines 3P4-3PH are transferred to lines 3P12-3P19 »the reading is corrected.

The next signal from line 4ΧΠ causes a binary unit on line IM4B2 and the signal on line IM4BSTB to become a binary zero. The reading siiB of the counter CN4 is maintained until the next "memory" signal comes from the line C030 as a result of the counter CN3 completing the counting of the 4096 pulse or because the next correction pulse comes from the line IM4BSTB.

In order to understand how the counter CN4 is corrected each time the second fixed point of the shaft 106 passes through a point 180 degrees from the second angular position, it is assumed that the rotation of the shaft 101 has brought the shaft 106 to this position. When this occurs, the signal generated by the pulse generator PG4 and input to the amplifier B4 via line IM4 changes from binary zero to binary unit. As a result, the next simultaneous pulse from line 4XB to register DIC2 (Fig. 8A) causes the register to transfer the signal from amplifier B4 via line IM4B to its output line IM4B1. As understood from the above, line IM4B has hitherto had a binary one signal, which has caused a binary one signal for line IM4B2. The binary zero signal of line IM4B1 is applied to one input of the exclusive OR gate X0R2, and combined with the binary one signal from line IM4B2 to the other input of this port so that a pulse signal is generated along line IM4BSTB to the counter CN4 ·

It is to be understood that whenever the second fixed point of the shaft 106 is 180 degrees from the second angular position, the reading of the counter CN3 indicated by the signals on lines 3P4-3PH represents the number of times the first fixed point of the shaft 101 has passed through the first angular position from the assumed initial position , which shows 28 64998 the angle at which the shaft 101 has rotated while the shaft 106 has rotated 180 ° since its second fixed point was last in the second angular position. This counter angle causes the signal of line 3P11 to be the complement of the number desired to be transferred to the counter CN4 when the second fixed point of the axis 106 is 180 degrees from the second angular position. The exclusive OR gate X0R8 compensates for this by causing the signal on line 4P11 to be binary when the signal on line 3P11 is at binary and vice versa. This occurs because the signal on line BE is linear when the second fixed point of the axis 106 is 180 degrees from the second angular position, because the line IM4B2 has a continuous binary one signal as the second fixed point of the axis 106 rotates from the second angular position to the point 180 degrees therefrom. from the assumed direction of rotation.

When line BE has a binary unit, line 3ίΊ1 and thus also line 4P11A has a binary unit, and the exclusive OR gate X0R8 forms a binary zero for line 4PH · On the other hand, the binary zeros on line 3 ^ 11 and line 4P11A As a result, during the generation of the signal coming to the line IM4BSTB, the number transferred to the counter C1T4 does not become incorrect even if the complement of the signal transmitted to the line 4P11.

From the above, it is to be understood that the signal generated by the pulse generator P + 4 and input to the signal shaping circuit C0ND2 via line IM4 continuously lags behind the signal generated by pulse generator PG3 and introduced along line IM3 to signal processing circuit 00111) 2 as the shaft 101 continues to rotate. When the fixed point of the axis 101 has shifted from its initial position of 128 1/2 turns, as a result of this increasing omission, the signal coming along line IM3 changes from a binary zero signal to a binary unit signal and the signal coming along line IM4 at the same time changes from binary unit to binary zero. As will be explained, when the first fixed point of the shaft 101 rotates more than 129 revolutions through its first angular position, the signals applied to the data lines 4P4-4PH of the counter CN4 as shown would incorrectly represent the number of revolutions of the first fixed point. The totalizer AUDI, gates X0R7 and X0R8 and the inverter IA 5 thus act as a signal converter which ensures that the signals of the lines 4P4-4PII correspond correctly to the speed of the first fixed point of the shaft 101 whenever these signals are applied to the output lines 3P12-3P19 of the counter CN4 ·

Due to the increasing gap between the shaft 101 and the shaft 106, the first fixed point of the shaft 101 moves closer and closer to the first ground position 29 64998 each time the second fixed point of the shaft 106 again passes a point 180 degrees from the second angular position. However, the counter CLT3 from lines 3P4-3P10 and OR gate X0R8 to line 4-L11A correctly indicate the number of revolutions of the first fixed point of the shaft 101 past the first angular position when the second fixed point of the shaft 106 is in the 180 degree position.

This will continue until the shaft 127 · round, the first reference point is a half of the tooth from the first angular position of the reference point 106 and the second axis is 180 degrees away from the second angular position. The next time the shaft 106 rotates by the tooth of the gear 104 257, the first fixed point of the shaft 101 thus passes twice through the first angular position, since the gear 102 with 256 teeth must also travel this distance corresponding to 257 teeth. This brings the half fixed tooth of the first fixed point past the first angular position. Thus, when the second fixed point of the shaft 106 arrives at a position 180 degrees from the second angular position due to this rotational movement, the count of the counter CN3 showing the number of times the first fixed point has passed through the first angular position should be two more than it was immediately the last time the second fixed point of the shaft 106 arrived at a point 180 degrees from the second angular position. However, the reading of the counter CN3 appears to indicate that only one such rotation of the shaft 101 through the first angular position would have occurred. To provide an additional reading, the NO gate N0G4 appears as a binary one from the adder ADD1 when the second fixed point of the axis 106 arrives at its 180 degree position this and each subsequent time.

At each such arrival, line IM4B2 has a binary one, causing a binary zero signal for line BE. Also, due to the position of the first fixed point of the shaft 101 with respect to the first angular position, at this and each subsequent arrival of the second fixed point of the shaft 106 at the 180 degree position, the signal of the line 3PH is binary at each such time. This causes a binary one signal on line C040, which, when added to the signals of lines 3f’4-3P10 and together with the signal of line 4PH, transmits signals to lines JK12-3P19 during such rounds, representing the number of times the first fixed point has passed the first angular position; this is done to correct the output of the counter CK4 if it is incorrect at such times.

It can be seen from the above that if the counter CN3 or CN4 does not correctly display signals showing the position of the first fixed point 30 64998 of the shaft 101 and the number of times the first fixed point of the shaft 101 has passed through its first angular position, the output signals CN3 and CN4 of these counters are replaced every once the logic level of the signal generators PG3 and PG4 is changed from the first level to the second level or from the second level to the first level. The plane changes causing the correction of the counter CN3 with each revolution of the shaft 101 are selected to occur when the first fixed point of the shaft 101 is at the first angular point and again when the first fixed point is 180 degrees away from its first position. The plane changes causing the correction of the counter CN4 with each revolution of the shaft 101 are selected so that they occur when the second fixed point of the shaft 106 is at its second angular position and again when this second fixed point is 180 degrees away from its second angular position.

The operation of the rotation of the shafts 101 and 106 of this embodiment, in which the counters subtract the numbers stored therein according to the signals coming from the line 4XUD, occurs when there is no signal coming from the line HIO. This signal does not occur when the signals on line X3 are ahead of the signals on line Y3. This activity will be apparent to those of ordinary skill in the art from the foregoing and, for brevity, will not be set forth herein. It should be noted, however, that due to the change in the direction of rotation of the shafts, the signals of the lines IM3B2 and IM4B2 are in the wrong state to form the desired functions of the exclusive OR gate X0R8 and the NOT OR gate N0G4 as described above. To correct this, the input signals are applied to the exclusive OR gates X0R5 and X0R7, and these signals handle the signals of the lines IM3B2 and IM4B2 in the reverse direction of rotation.

It will be apparent that various modifications of the foregoing will be apparent to those skilled in the art and that the apparatus disclosed herein is for illustrative purposes and should not be construed as limiting.

li

Claims (4)

A measurement value converter for rotational position of a rotating shaft having a first coded disk (103) disposed on a first rotatable shaft (101), with a second coded disk (105) disposed on a second rotatable shaft (106), with for identifying code markings of the discs serving electrical identification devices and having a signal processing circuitry which processes the identification signals supplied by the electrical identification devices and brings them to the instruction, the first rotatable shaft (101) and the second rotatable shaft (106) coupled to each other over a switching gear (102, 104), characterized in that a) the first coded disc (103) is coupled to rotate relative to the second coded disc (105) such that the first coded disc rotates a first binary number 2n + 1 revolution while the second coded disk (105) rotates a second binary number 2n revolutions, where n is an integer greater than zero, b) the signal processing circuitry For example, the identification signals supplied by the electrical identification devices operate in such a way that the instruction is a function of difference in the angular position of the encoded disks (103, 105). Measured value converter according to claim 1, characterized in that each coded disk (103, 105) has a complete absolute position code and that the signal processing device contains means (SUBT) for subtracting absolute position signals (B0-B10) of the one encoded disk (105) from absolute position signals (CA0-CA9) of the second coded disk (103). Measured value converter according to claim 1, characterized in that the signal processing switching device contains the following: a higher order section (CNZ: CN4) and a lower order (CN1, CN3) section, each of which contains several parallel data inputs (P1-P4) and a parallel order input (PE), this counter generating output signals, of which the section (P80-PP11; 4P4-4P11) of the lower order indicates the rotational position of one of the disks and of which the section PP12-PP19; 3P12-3P19) of higher