NL8900588A - DEVICE AND METHOD OF A VLSI SHIFT TECHNOLOGY IMPLEMENTED RULES BASED EXPERT SYSTEM. - Google Patents

Description

N.0. 35716

Design and working method of a VLSI circuit-technically implemented, regulation-based expert system.

Field and Background of the Invention This invention relates to a rule-based expert system, and more particularly to a circuit engineering implemented rule-based expert system, capable of performing high-speed deductions in artificial intelligence. applications.

Expert systems are a class of computer programs that include artificial intelligence technology to address problems that would normally require human experts or specialists. In a rules-based expert system, an expert's knowledge in a specific field of application is represented in the form of a series of "production rules" rules. When working with a typical expert system, the user feeds, via a suitable user interface, the expert system with certain known information about a specific problem, and the expert system applies the production instructions to this known information, for the purpose of deducing facts and solving problems which are relevant to the scope. For further background information regarding expert systems, reference is made to the following articles: 20 Robert H. Michael sen, et al., "The Technology of Expert Systems", Byte Magazine, April 1985, pp. 308-312; Beverly A. Thompson, et al., "Inside an Expert System", Byte Magazine, April 1985, pp. 315-330, Michael F. Deering, "Architectures for AI", Byte Magazine, April 1985, pp. 193-206.

25 Successful expert systems have been developed for a number of application areas: for making medical diagnoses, for identifying organic mixtures, for selecting drilling oil suspensions, etc. In addition, a number of application-independent expert systems have been developed in software form, to support 30 building regulatory-based expert systems for specific application areas. A number of commercially available expert system tools are described in the above articles. These expert systems and expert system tools are typically designed in the form of computer programs to run on a general purpose computer or a microcomputer. The computer program provides an interactive session between the user and the expert system in which the expert system asks questions to the user, and for 8900588.

· '· »2 use the problem-solving expert database to provide advice to the user.

There is considerable interest in extending the application of expert systems to other practical applications and in particular in developing expert systems suitable for use in real-time applications. These systems could for example be useful as a control system for various applications, such as manufacturing processes, process control, guidance systems, robotics, etc. A serious limitation in the development of 10 complex, real-time artificial intelligence systems ("artificial intelligence (AI) systems") ") is the calculation speed. To make effective practical use of artificial intelligence technology, efficiency and calculation speed must be increased.

Significant efforts have been made to improve the speed of AI-15 processing by improving and streamlining the programming tools used in AI processing, such as the AI languages. It has also been recognized that quality improvements can be achieved through custom circuitry, especially designed for artificial intelligence processing. As indicated in the above Deering article, an approach to circuit engineering architecture improvements included refinements in the processor instruction set to allow faster processor operation. Attention has also been paid to the development of parallel processing architectures, with which it may be possible to perform the AI calculations in parallel. The article also notes that custom VLSI circuits could be used to accelerate specific operations such as comparison, instruction retrieval, parallel 1-el processor communication and signal-to-symbol processing.

Summary of the invention

An important object of the present invention is to improve the speed and efficiency of prescription-based expert systems by providing a circuit-implemented deduction machine. More particularly, the present invention provides a dedicated integrated circuit specially designed for high speed deductions for a regulatory expert system.

The apparatus and method for a circuit-engineered, prescription-based expert system of the present invention is described below with the acronym REX ("Rule-8900588.

3 • τ based EXpert "), and includes a working memory in which known information or facts are stored at the start of a deduction operation for the application area. The device further comprises a prescription memory for storing a prescription set for the application area. consists of a series of instructions each defining a condition or an action Means are provided for loading consecutive instructions from the prescription set from the working memory and logical means are provided for sequentially executing the instructions in the working memory with regard to the facts stored in working memory, thus deducing new facts.

During the deduction process, when new facts are deduced, they are stored in working memory, which can be used during the execution of successive instructions from the prescription set to derive further facts. After the deduction process has been completed, the facts stored in the working memory are transferred to an output device.

Each of the instructions from the prescription set includes an operator, a condition / action flag, and a pair of operands. The logical means includes an instruction decoder for testing the condition / action flag of each instruction to determine whether the instruction is a condition or an action. When the instruction is a condition, the operands are compared in accordance with the operator-specified logic operation to generate a logic result (for example, true or false). When the instruction is an action, the operator-specified action is performed on the operands.

The working memory and logic means can conveniently be provided as an integrated circuit. The prescription memory can be connected to the main memory externally from the integrated circuit via a suitable external memory bus, or the prescription memory can also be included in the integrated circuit with suitable data bus connections to the main memory.

Because the application rule set is stored in a memory device, the REX deduction machine is area independent allowing it to be used for different applications, simply by including another application rule set in the rule memory. The structure of the prescription memory and the data structure of the application prescription set are designed to greatly increase the efficiency of the deduction process.

40 To illustrate versatility and broad general purpose 6900588.

4 suitability of the present invention, the following detailed description shows how the REX deduction machine as. coprocessor in conjunction with an existing computer or microcomputer can be used to provide an expert system suitable for performing deductions at speeds significantly greater than would be possible by a conventional software-infused deduction machine . However, the REX deduction machine can also be used for many other applications, such as a self-contained system, if equipped with a suitable internal control system, a user interface and input / output devices.

The REX deduction machine is suitable for real-time knowledge processing based on current VLSI technology. The rate at which problems are solved is measured in logical deductions per second (LIPS) instead of floating point operations per second (FLOPS). An LIPS equals about 100 to 1000 FLOPS on a typical computer.

Brief Description of the Drawings Some of the features and advantages of the invention have already been mentioned, others will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, in which:

Fig. 1 is a perspective view illustrating how the REX deduction machine of the present invention can be used as a co-processor in a conventional personal computer;

Fig. 2 is a more detailed view of a co-processor card using the REX deduction machine; FIG. 3 is a block diagram showing the data flow for the REX machine;

Fig. 4 is a block diagram illustrating the structure of the rule database for the REX machine;

Fig. 5 is a diagram showing the data structure of the instructions stored in the prescription memory;

Fig. 6 is a diagram illustrating the operation code format used in the REX chip;

Fig. 7 is a total block diagram of the main functional components of the REX chip;

Fig. 40 8 is a diagram showing the data bus bit allocation for I / O

8900588.

5

* sT

illustrates read / write operations;

Ffg. 9 is a flow chart showing the deduction current of the REX chip; and

Fig. 10 to 12 are time diagrams for the REX chip showing the timing of the read mode, write mode and external memory, respectively.

Detailed description

The present invention is described in more detail below with reference to the accompanying drawings, in which an illustrative embodiment of the invention is shown. However, the invention can be practiced in many different forms and should not be construed as being limited to the embodiment described below, as the applicant has provided this embodiment for the description to be thorough and complete and to fully illustrate the scope of the invention to those skilled in the art .

Referring now particularly to the drawings, Fig. 1 illustrates an expert system of the present invention designed to interface with a microcomputer 10, such as an IBM AT Personal Computer, with a prescription-based expert system (REX) added thereto. co-processor card 11. The REX card 11 is composed of a REX chip 12, an external prescription memory 13 and an I / O interface 14. The REX card is shown in more detail in Fig. 2.

An application prescription set for a specific application area, indicated by 15 in Fig. 2, is stored in the external prescription memory 13. The REX chip 12 is therefore area independent and can be used for a wide variety of application areas.

Referring to Fig. 2, each component of the REX co-processor card 11 is explained as follows: 30 I / O interface: The I / O interface 14 is responsible for the communication between the personal computer 10 and the REX co-processor card 11. External data is transferred from the personal computer 10 via the I / O interface 14 to the REX card 11. In the embodiment illustrated herein, a DMA channel provides a communication link between the REX card 11 and the personal computer 10. A computer program running on the personal computer is used to provide an easily understandable user interface.

REX chip: The REX chip 12 is a circuit-based deduction machine and forms the heart of the REX co-processor card 11. Two main components of the REX chip are the working memory and the control unit. Front 8900588.

* 6 that the deduction process starts, the working memory is initialized with external data from the I / O interface. External data relevant to facts known from the application area are stored in special memory locations of the working memory. During the deduction process, the working memory forms a temporary storage for intermediate data. When the deduction process is completed, the working memory contains the results of the deduction process, which are then transferred to the personal computer via the I / O interface.

Prescription memory; The knowledge engineer extracts a production prescription set, called an application prescription set 15, from the application area and this prescription set is stored in the prescription memory 13. During the deduction process, the REX chip 12 refers to the prescription memory 13 for prescription information. The prescription memory structure is suitably designed to meet the requirements of the REX chip and to reduce memory space. The data structure of the application prescription set stored in the prescription memory is designed to greatly increase the efficiency of the deduction process. Further details about the structure of the prescription memory and the application prescription set stored therein are provided below.

The prescription memory can be a ROM, RAM, EPROM or other suitable memory device. When a RAM for the prescription memory is used, an initialization program is used to pre-load the application prescription set 15 into the external memory 13.

While the specific embodiment illustrated herein demonstrates how to use the REX chip 12 as a co-processor for a personal computer, those skilled in the art will recognize that the circuit-implemented, regulatory-based expert system of the present invention (REX) for many other specific applications can be used. For example, it can be used as a standalone operating system. In such a case, a control system is provided for handling the user interface and the I / O interface and additional I / O devices such as a keyboard, a graphic display, etc. are provided to communicate between the REX card and enable the user.

Deducti emechani sme

There are several types of deduction methods that can be used to solve a problem in a prescription-based expert system 40. Some of the major deduction methods 0900588.

> 7 are forward chain formation, backward chain formation and combination chain formation. The deduction machine particularly illustrated and described herein utilizes the forward chain formation deduction method with production instructions.

5 The rules of the rules-based system are represented by production rules. The production rules consist of an if (“if”) part and an if (“then”) part.

The jf part is a list of one or more conditions or antecedents. The then part is a list of actions or consequences. A production rule can therefore be represented as follows: if condition_1, condition_2, • 15 condition_n then action_1, action_2,

V

* action_n 20

When the conditions (condition_1, condition_2, .. condition_n) are fulfilled by the facts of a given problem, we can say that the rule has been triggered. The expert system can then perform the given actions. When the actions are finished It is said that the rules have been fired. These special actions may change other conditions, which in turn may fire other rules. The flow of fired rules will continue until the problems are resolved, or until none other prescriptions may be fulfilled This method of firing prescriptions moves forward through the prescriptions, so it is called forward chaining Forward chaining is also called a deductive system or fact-driven because the facts direct the flow of the fired regulations.

The drawing of the rules does not mean that the rules have been fired, because the conditions of several other rules may be met simultaneously, and all are drawn.

When this occurs it is necessary to apply a conflict resolution strategy to decide which rule is actually fired. A conflict resolution strategy is a process of selection 89 005 88 ·.

8 Run the most favorable rule when more than one rule is met. Examples of conflict resolution strategies include the following: 1. The rule containing the most recent data is selected. This strategy is in the English language "Data Recency

Ordering "called.

2. The rule that holds the most complicated of the most difficult conditions is selected. In the English language this is also called "Context Limiting Strategy".

10 3. The rule that is first in the list is selected. This is called "Rule Ordering" in the English language.

Example I

Example of forward chain formation This example provides a general illustration of the operation of a regulatory based expert system. For the purpose of this illustration, reference is made to the animal identification rule set in Appendix A. This prescription set tries to identify an animal by giving its physical properties. Assume that the following properties have been observed: the animal has hair, the animal eats meat, the animal has a yellow-brown color, the animal has black stripes.

These observations are translated into the following facts: covering = hair, food = meat, color = tan, stripes = black.

Given these facts, REGULATION 1 is drawn. According to this rule, we deduce that class = mammal.

That the animal is a mammal is now taken as a new fact by the system. Consequently, REGULATION 2 to REGULATION 4 & 9005S8 may apply.

9 cannot be drawn. The condition of REGULATION 5 is valid so that the system will deduce that the animal is a carnivore.

meat eater = yes.

5

The system has so far infused two useful new facts. The first three conditions of REGULATION 9 are true, but the last condition is not, so REGULATION 9 fails. REGULATION 10 is pulled and can be fired. The system therefore deduces that the animal is a tiger.

animal = tiger.

The deduction does not stop here, because there are several regulations.

15 In this case, none of the other requirements can be met. The system identifies the animal as a tiger.

The example shows a deduction method in the forward direction, from the current situation of facts or observations to a conclusion.

20 REX deducti emachi ne architecture

The main components of the REX deduction machine are shown in more detail in Fig. 3. The REX chip itself has three primary functional components: the working memory 16, an arithmetic and logic unit (ALU) 17 and control logic 18. In the embodiment shown herein, the code memory 13 is a separate memory device which is connected to the working memory 16 via a data bus 21. On the other hand, it will be apparent to one skilled in the art that the prescription memory could be integrated into the REX chip itself if desired. The I / O interface 14 is communicatively connected to the working memory via a system interface bus 30, which is designated 22 in its entirety. The control logic is shown schematically in Fig. 3 and is indicated by the reference numeral 18. In general, the control logic 18 has the task of controlling the operation of the other elements, such as the ALU 17 and the working memory 16.

35 Data flow in the REX deduction machine

The data flow of the REX machine will best be apparent from Fig. 3 and the following description. The circled figures in fig. 3 correspond to the following topics: 1. Input data 40 The user enters the facts via a user interface program 8900588.

10 ma on the personal computer 10 to the system. The user presents the facts in a predetermined syntax. For example, using the fact data of Example I and the Appendix A prescription set, the user would enter: 5 coverage = hair color = tan • · .. etc.

10

The user interface program converts any actual observation into values represented by a few binary numbers. The first part of the pair is an address and the second part of the pair is a value.

15 address 1 value

In the example above we have: 20 (address 032) coverage = (value% 10) hair, (sidres 058) color - (value% 55) yellow brown, • · .. etc.

25 wherein "0" and indicate that the referenced digit is an address or a value, respectively. In the above case, cover is shown at address 32 (no other word is displayed at address 32). Each word is therefore assigned a unique address number. The value hair is stored at address 32. These numbers are used in step 2-30.

2. Storing facts in working memory

In step 2 the facts are stored in the working memory.

3. Placing prescriptions in the working memory

The external memory is used to store regulations relevant to the application area. Each prescription is represented as follows: 8900588.

»11

IF

condition 1 and condition 2 and 5

THEN

action 1 action 2 • * · 10

A condition element is: (class = mammal) 15 Similar is an action element: (type = hoofed)

Each element, both a condition and an action part of the rule, is internally represented as an instruction in the format shown below:

Operandl | 0perand2 | Operator [Dir / Imme [Act / Cond 25 Each instruction has a predetermined length, for example 32 bits. Operandl represents an address of the working memory. Depending on the value of the Dir / Imme field, 0perand2 is either an address or a value in working memory. The Dir / Imme field specifies whether the addressing mode of 0perand2 is Direct or Immediate. The Act / Cond field specifies whether the element refers to the condition or action portion of a rule. The Operator field specifies the type of operator used in the condition part of the rule. Examples of operators are: equals (=), greater than (>), less than (<) ·, etc.

35 4-5. Deduction cycle

The following steps are performed during the deduction cycle.

4.1. Reaching the external memory element

A prescription is retrieved from the prescription memory 13, specifying the Cond / Act field of the first instruction 8900588.

* 12 searched to determine if it is a condition or an action. When the statement is a condition element, the section 4.1.1. described procedure. When it is an action, the information in section 4.1.2. described procedure.

5 4.1.1. Adapting the prescription condition element to the working memory

The address in Operandl is loaded into the ALU (step 4). The Dir / Imme field is then examined to determine whether OperandZ is Direct or Immediate. When this is Immediate, the value of 0 0perand2 is applied directly to the ALU, otherwise the content of the address designated by 0perand2 is applied to the ALU. The input of the ALU is compared by the ALU using the operator (Operator field) to determine if the condition is true or false. When the condition is true, the next successive instruction of the prescription is examined by repeating the series of steps indicated in section 4.1. When the condition element is false, this rule is discarded and the following rule is examined by repeating the series of steps in section 4.1.

20 4.1.2. Action part

The Dir / Imme flag of the action element is checked first. When it is Direct, the value stored in location 0perand2 of the working memory is copied to the working memory address represented by Operandl. When the Dir / Imme flag 25 is Immediate, 0perand2 is copied to the working memory address represented by Operandl. After performing the action specified by the instruction, the next successive action instruction of the rule is read and the one described in section 4.1.2. described procedure. When the action instruction is the last instruction of the rule, repeat the sequence of steps in section 4.1. examined the following prescription.

6. Facts to data

When all prescriptions have been processed, the control is transferred to the I / O interface 14. The numerical representation of the facts 35 is converted into a form which can be easily understood by the user.

7. Data output

The I / O interface will then output the data to the personal computer 10.

8900588, 8 13

Example II

Example of the REX data stream

This example illustrates how the REX chip solves the problem described in Example I above. The numbered items 5 again correspond to the circled numbers in Fig. 3. See Appendix A for the complete animal identification rule set.

1. Input of external data

The data or observations made are: 10 the animal has hair, the animal eats meat, the animal has a yellow-brown color, the animal has black stripes.

15 The above data enters the I / O interface and is translated into facts. The data is translated into the following facts: {address 032) coverage = (value * 10) hair, (address 041) food = (value% 3) meat, 20 (address 058) color = (value% 55) tan, ( address 035) stripes s (value $ 8) black.

2. Facts stored in working memory

The address represents the location in the working memory. For example, address! O-25 katie 32 houses the value 10.

3. Loading an instruction

An instruction is loaded from the prescriptions memory. The first instruction of REGULATION 1 is a condition, and it takes the form of: 30 (address 032) covering EQUAL (“EQUAL”) (value * 10) hair 4. Loading operands a. Condition 35 The value of address ! cation 32 is loaded into the ALU, in this case 10. The ALU comparison process is: (value% 10) hair EQUAL (value% 10) hair 40 This result is true.

9900588.

14

If the instruction is: (address 032) cover EQUAL (value% 11) springs,

5, the output of the ALU would be false. The control returns to STEP

3.

b. Action

If the instruction is an action, such as: 10 (address 077) class MOV (value% 20) mammal, the ALU would get the value 20 and store it at address 77 location.

5. Storing facts in working memory

The value 20 has been deduced from the REGULATION 1 and must be stored at 15 address location 77. The control returns to STEP

3.

6. Facts to data

In this example, the value on the (address 088) class is transferred to the I / O interface. From the facts it follows that the value at 20 address location 88 (value% 100) is tiger.

7. Export of data

The interface translates the value 100 into tiger.

Structure of the regulation database

The application rule set 15, which is stored in the working memory 16, is divided into two parts - STRUCT and REGULATIONS. In each rule, a set of conditions is grouped at adjacent addresses. Also, in each rule, a set of actions at adjacent addresses is grouped. These groups can be stored in the REGULATIONS section of working memory in the following way: 8900588.

15

Regulation% 1 address xxxl condition_l_l address xxx2 condi ti e__l_2 5.

• address xxxm condition_l_m address yyyl action_l_l address yyy2 action_l_2 10.

• ·

Regulation% 2 address zzzl condition_2_l • · 15

Since the conditions and actions are successively stored at different memory addresses, the representation of the rules can be structured using the start address of each rule. The production requirement can therefore be expressed as: if xxxl then yyyl 25 if zzzl then ....

This format shows that when a group of conditions at a given address is TRUE, the group of actions must be performed at the address specified in the then part. Then, when the first rule is false, the steering mechanism jumps to the start address of the next rule. There is no need for end indicators for each prescription, so that the REX does not waste time looking for end indicators.

The structure of the REX regulatory database is shown in Figure 4. In this version, an external memory of 64K X 32 ROM is used to store the application rule set 15. To maximize the use of limited memory, STRUCT 40 and REGULATIONS are at both ends of the front 8900588, respectively. ' 16 exercise book memory 13 stored. STRUCT starts from address 0000H and above. REGULATIONS start from the address FFFFH and below.

Fig. 5 shows the detailed structure of the prescriptions memory. STRUCT houses the address index pointing to the starting address 5 of each rule in REGULATIONS. The size of the prescription memory is 64K, so that only the 16-bit bottom half word is used.

Each condition or action is represented as a 32-bit word instruction processed by the REX. The condition is basically a logical comparison of two given operands. The actions are organized in a similar way. The operators of the actions are basically logical operators and an assignment operator. There are two operands for each process: operandl and operand2. 0perand2 can take two forms: direct or immediate. As shown in Fig. 4, the di-15 operand is a pointer ("pointer") to an address in working memory represented by the symbol "0" and the immediate operand is an integer represented by

Instruction set for the REX deduction machine

As shown in Fig. 5 (b), instructions from the REX are always 32 bit long. The Operation code (6 bits), 0P1 (13 bits) and 0P2 (13 bits) have been combined into a 32-bit instruction. Each prescription in a given application prescription set has condition and action parts. The REX therefore has two types of instruction set: - Condition Instructions: This type of instruction is used to check whether the condition is True or False. This allows users to define different logical relationships between two operands, such as "Equal to" ("Equal"), "Greater than" ("Greater than"), etc. The operation result of a Condition statement can only be True or False, which affects the following processing sequence.

- Action Instructions: This type of instruction is only executed when all conditions of the current prescription are True. The result of executing the action is always stored in the first operand.

35 The instructions and associated operation codes are in Table A.

summarized.

8900588.

TABLE A - REX OPERATION CODES

17

Operation codes Operation Description_ 5 OXOOOO EQ Equal to ("EQual to"); ___Is operandl = operand2? _ 0X0001 NE Not Equal to ("Not Equal to"); ___Is operandl <> operand2? _ 0X0010 GT Greater than ("Greater Than"); 10___Is operandl> operand2? _ 0X0011 LT Less than ("Less Than"); ___Is operandl <operandZ? _ 0X0100 GE Greater than or Equal to ("Greater than or Equal to"); 15___Is operandl> = operand2? _ 0X0101 LE Less than or Equal to ("Less than or Equal to"); ___Is operandl <= operand2? _ 1X0000 NOT logical denial operandl ("logic 20 NOT operandl");

Each bit of operandl is complemented and the result is stored in operandl _____ in working memory. 1X0001 AND logical AND ("AND") operandl and operand2; The logical AND operation is performed on the corresponding bits of operand1 and ope-rand2. The result is stored in working memory on ___operandl.

1X0010 OR logical OR ("OR") operandl and operand2; The logic OR operation is performed on the corresponding bits of operand1 and ope-edge2. The result is stored in working memory on ___operandl.

1X0011 MOV Move ("MOVe") operand2 to operand1;

The contents of operand2 are stored on operandl __ in the working memory. 8900588.

18 i TABLE A (continued)

Operation codes Operation Description_ 5 1X0100 SHR Slide ("SHift") operandl one bit to the right ("Right");

The least significant bit is removed and a zero is shifted in place of the most significant bit; 10 the result is stored on operandl in the working memory. 1X0101 SHL Slide ("SHift") operandl 1 bit to the Left ("Left");

The most significant bit is removed and a zero is shifted in place of the least significant bit; the result is stored on operandl in the working memory. XX0110 JMP Spring ("JuMP") to a new address of the external memory;

For the JMP instruction, the least significant 16 bits of the instruction are loaded into the C1 register pointing to the new prescription in the external memory. _ XX0111 EOR End of external memory ("End of __ External Memory") ._ | operandl is a direct addressed data (WM [0P1]) from working memory.

operand2 can be a direct addressed data (WM [0P2]) or an immediate data (0P2).

The format of the opcode is shown in Fig. 6. The MSB (Most 35 Significant Bit), which is Fl, of the opcode is used to specify the type of instruction. When Fl is 0, it is a Condition statement, otherwise it is an Action statement.

A Condition statement always has two operands. An Action Instruction, on the other hand, can have only one or two operands, depending on the operation required.

8900588.

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The REX allows two types of addressing: immediate and direct addressing. The first operand always uses direct addressing. The second operand can be an immediate data or a direct-addressed data. The addressing mode is determined by examining the second MSB, which is F2, of the operation code. When F2 is 0, the second operand is immediate. Otherwise, the second operand is directly addressed.

Functional description of the REX chip Fig. 7 provides a detailed block diagram of the REX chip 10 12. To avoid repeated description, elements described above in conjunction with previous figures are indicated by the same reference numerals.

Table B lists the name, I / O type and function of each input and output illustrated in Figure 7.

8900588.

TABLE B - PEN DESCRIPTION OF THE REX

20

Symbol Type Name and function_ 5 CLK I Clock Input ("Clock Input"): CLK controls the internal processing of the REX chip. The maximum clock frequency is 8 MHz. CS I Chip Selection ("Chip Select"): CS is an active low input used to select the REX chip as an I / O device when the CPU wants to read / write the internal registers (WM, ________WMC, C / S) of the REX chip.

EMCS 0 External Memory Chip Selection ("External

Memory Chip Select "): EMCS is active low. When REX is in deduction mode, EMCS is selected to select the external memory for ___ prescription information. -_ IOR II / O-Read (" I / O Read "): IOR is active low.

20 When both CS and IOR are active, the CPU has read access to the internal registers ___ (WM, WMC, C / S) of the REX chip._ IOW II / O Write ("I / O Write"): ÏÜW is low active,

When both CS and ÜÜW are active, the 25 CPU has write access to the internal registers ___ (WM, WMC, C / S) of the REX._

READY 0 Ready ("Ready"): READY is active low. READY

is a synchronization signal for external data transfer. READY goes low when REX is ready for new data. RESET I Reset ("Reset"): RESET is active high.

RESET is used to initialize the state of the REX chip. All registers are reset ___ after RESET is activated.

35 INT 0 Interrupt Request ("INTerrupt Request"): INT

is highly active. The REX chip uses INT to interrupt the CPU when the REX chip _ has finished the deduction process ._ 8900588.

* TABLE B (continued) 21

Symbol__Type__Name and Function 5 A0-A1 I Address ("Address"): The CPU transfers the two least significant address lines for sending data transfer to the internal registers (WM, WMC, C / S) of the REX chip used.

DO-D15 I / O Data Bus ("Data Bus"): The data bus lines are bidirectional tri-state signals connected to the system data bus. The Data Bus contains output signals when IOR is active. The Data Bus contains _____ input signals when IOW is active. 15 MA0-MA15 0 External Memory Address Bus ("External Memory

Address Bus "): When the REX chip is in deduction mode, the external memory address bus is used to address a prescription in the _____external memory .__ 20 MD0-MD31 I External Memory data bus (" External Memory

Data Bus "): When the REX chip is in deduct! E mode, the external memory data bus sends the information related to each prescription to the REX chip. 25 WM: Working Memory WMC: Working Memory Counter register (Working Memory Counter register) C / S: Send / Status flag registers (Control / Status flag 30 registers)

The identification of each register and the operation of each is as follows: WM (Working memory): The working memory 16 is used during the deduction process for storing the intermediate data. Before REX starts the deduction process, the working memory is loaded with facts entered by the user. The size of the working memory always limits the amount of input from the user to the REX. In the horny! The exemplary embodiment, the working memory is a 4K X 8 static 40 RAM.

8900588.

22 · WMC (Working memory counter) register: WMC is a 13-bit adder with the possibility of parallel loading. During I / O mode, WMC is used as the RAM address counter for data transfer. When data transfer is in progress, WMC will be automatically increased. The contents of WMC can be set by the CPU prior to the start of data transfer.

- Cl register: Cl is a 16-bit adder with the possibility of parallel loading. During the deduction process, Cl points to one of the addresses of the rules in the STRUCT portion of the rules memory 13. Cl increases by one before REX moves to the next rule. For a JMP statement, Cl is loaded with a new value instead of incrementing it.

- C2 register: C2 is a 16-bit countdown with the possibility of parallel loading. C2 points to the REGULATIONS section of the prescription memory. When no false condition occurs in a prescription, C2 is decreased by one before REX moves to the next condition or action. When a false condition is detected with respect to a rule, C2 is loaded with the start address of the next rule, rather than decreasing it by one.

20 - OP register: The OP register has three parts: Operation code, 0P1 and 0P2, which include a REX instruction. Oper action code is a 6-bit register that stores the operator of an instruction. Both 0P1 and 0P2 are 13-bit data registers which store the address in the operand1 and operand2 RAM respectively.

25 - OP 'register: The OP' register is a pre-fetch register ("prefetch register") used to store the pre-fetch instruction ("prefetch instruction") for the OP register. REX will execute the pre-fetch instruction unless a JMP instruction or a false condition occurs.

30 - SI (Start / Inactive) ("Start / Idle") Control Flag: SI is used to identify the REX operation status: Deduction mode and I / O mode. SI is set by the CPU after the system sends all the facts to RAM. SI has the value 1 during the deduction mode. SI is reset by the REX every time the deduction process stops, after which the REX switches to I / O mode.

- IE (Interrupt Enable) ("Interrupt Enable") control flag: IE is set by the CPU at the same time as the Sl flag. REX grants interrupt release when the REX enters deduction mode. IE is used with the IRQ flag to output an interrupt signal. The IE flag becomes 89 0 05 88 at the end of the interrupt service routine.

23 reset by the CPU.

- IRQ (Interrupt Request) ("Interrupt ReQuest") status flag: When the deduction process stops, IRQ is set by REX to indicate that the REX is requesting an interrupt from the CPU. For outputting an interrupt signal INT, IRQ is en-linked with the IE flag. IRQ is reset by the CPU after the interrupt is recognized.

When the REX is in I / O mode, the CPU registers can read or write REX. The signals and the affected registers are shown in Table C.

10

TABLE C - DEFINITION OF REGISTER CODES

Register operation__CS IW IOR Al AO

Read status registers 01 0 00 15 ("Read Status Registers") _______

Write control registers 00100 ("Write Control Registers") ______

Read working memory counter 0 10 0 1 ("Read Working Memory Counter") ______ 20 Write working memory counter 00 1 01 ("Write Working Memory Counter") _____

Read working memory 0 1010 (“Read Working Memory”) ___________

Write working memory 0 01 1 0 25 ("Write Working Memory") ______

REX chip is not selected IX X XX

| ("REX Chip is Not Selected") ______

Editing modes 30 REX has two editing modes: - I / O mode - deduction mode.

The steering flag SI is used as a fashion flag. REX switches to the other mode when the SI flag is changed.

35 Before REX enters the deduct! Emode, the REX must load all user-entered facts from the main system into the REX's working memory. When the SI flag is set, the REX switches from I / O mode to deduct! Emode. After the deduction process has ended, the results are transferred from the working memory to the main system.

8900588.

24

During the I / O operation, the main system can read or write specific registers, if the REX chip is selected. The control of read / write operations and the selection of registers are controlled by a set of control lines, which are indicated in table C. During reading and writing WMC and C / S registers, only a few bits of the system data bus are used. This is illustrated in Fig. 8.

As soon as the working memory is loaded with facts entered by the user, the REX will start the deduction process from the first prescription in the external memory. The deduction current of the REX is shown in Fig. 9.

There are three different machine cycles for the REX in deduction mode.

- Tl cycle: Tl is a prescription fetch cycle. The Tl cycle 15 is performed only during the first start of the deduction process or when a JMP instruction occurs. In the Tl cycle $ of a prescription in the external memory, the start address is placed in the Cl register. Cl is in fact a prescription counter pointing to the start address of the currently deducted prescription.

20 - T2 cycle: T2 is an instruction fetch cycle. In the T2 cycle, the first condition instruction of each prescription is placed in the REX registers. The T2 cycle is performed when one of the conditions of a rule is false, processing starts from the first instruction of the next rule. C2 can be interpreted as an instruction counter that refers to a condition instruction or an action instruction that is currently being executed in the ALU.

- T3 cycle: The T3 cycle is an instructor cycle. There are several cases for the T3 cycle: 30 Condition Instruction / Immediate Data

Condition instruction / Direete addressing

Action Instruction / Immediate Data

Action Instruction / Direct Addressing

JMP

35 STOP (end of the prescription)

The pre-fetch cycle is overlapping with the T3 cycle. When a JMP instruction occurs, the edit sequence will go to the Tl cycle. When the result of a Condition statement is false 40, the edit sequence will advance to the T2 cycle. When no JMP-in 3900588.

If no false condition occurs, the REX will use the pre-fetch data to go to the T3 cycle.

REX will always go through the same process until all prescriptions in the external memory are deducted. When the deduction process stops, the $ I flag is reset to "O". The REX then switches from the deduction mode to the I / O mode.

Time chart

The time diagrams for the REX in the I / O read mode, the 1/0 write mode and for the external prescription memory are also shown in FIGS. 10-12, respectively. The AC (AC) properties of the REX in I / O mode are shown in Table D.

6900588.

TABLE D - AC SPECIFICATION

26

Symbol Parameter Min Type Max Unit 5______ Unit TAS I / O Address Setup Time 20 - - ns __ ("I / O Address Setup Time") __; __; ___ TAH I / O Address Hold Time 10 - - ns __ ("I / O Address Hold Time ") _____ 10 TIW I / O Read / Write Signal Width 60 - - ns __ (" I / O Read / Write Signal Width ") ____ TOD Data Output Delay Time - - 40 ns __ (" Data Output Delay Time ") _____ TOH Data Output Hold Time 10 - - ns 15 __ ("Data Output Hold Time") _____ TDS Data Setup Time 20 - - ns __ ("Data Setup Time") _____ TDH Data Hold Time 10 - - ns __ ("Data Hold Time") _____ 20 TRS Ready signal setting time 0 - - ns __ ("READY Signal Setup Time") _____ TRD Ready signal delay time 0 - CLK * 1 ns __ ("READY Signal Delay Time") _____ TRW Ready signal width CLK-10 CLK * 1 CLK + 10 ns 25 __ ("READY Signal Width") ______ TMAW External Memory Address Signal Width ("External Memory CLK * 2-20 CLK * 2 CLK * 2 + 20 ns __Address Signal Width") _______ TMAC External Memory Address 30 run time ("External Memory - - 170 ns __Address Access Time ") _____ TMOH External Memory Data Output Hold Time (" External 0 - - ns __Memory Data Output Hold Time ") _____ 35 TCSS External Memory Chip Selection Setup Time (" External Memory 0 - - ns __Chip Select Setup Time ") ______ TCSH External Memory Chip Selection Hold Time ("External Memory 0 - - ns 40__Chip Select Hold Time") _____ TMOZ External Memory Output Exchange ("External Memory Output - 20 - ns __Floating") _____ 8900586.

GLOSSARY

27

Antecedent The 1f (if) part of a production rule.

5 Application area The subject or field relevant to the expert system.

Application regulation set A set of regulations, which have been selected by a knowledge engineer and which are relevant for a specific area of application.

ASIC Application-specific integrated circuit ("Application Specific Integrated Circuit") is a tailor-made integrated circuit for a specific application.

Consequence The then (then) part of a production instruction.

CPU Central processing unit ("Central

Processing Unit "): An operating unit 20 which processes instructions and data.

Co-processor A specialized processor that works with a main computer to increase the quality of the entire system.

25 Control logic A custom circuit that controls all operations required for the REX chip.

DMA Direct memory access ("Direct Memory

Access "): A method common in communication technology between a main computer and computer peripherals. DMA provides the most efficient way of transferring a block of data.

35 External Data A block of binary data that resides in main computer memory.

External memory A physical memory in which the application rule set is stored.

4900588.

GLOSSARY (continued) 28

Fact A truth known by actual experience or observation. A group of facts is gathered for gripping assumptions.

Deduction Interpreting a prescription from an application prescription set.

Deduction machine A problem solving steering mechanism 10 for an expert system.

I / O interface A type of device controller responsible for the communication between the main computer system and computer peripherals.

15 Knowledge engineer A person who extracts knowledge and facts from a relevant application area and converts it into an application prescription set.

PC Personal computer.

20 PC / DOS The Disk Management System ("Disk Operating

System ") of a personal computer * that manages the read / write operations of a disk controller.

Production rule A rule that is specified in an if-then format.

RAM Random-access memory: An electronic memory containing binary information accessible for reading or writing.

ROM Dead Memory ("Read-Only Memory"): An electronic memory that stores the binary information. A ROM is only accessible for reading; it has no writing capability.

Prescribing Information- An organizational chart that efficiently stores the prescriptive structure prescriptions to save memory space and processing time.

900586.

29 GLOSSARY (continued)

Working memory A RAM housed in the REX chip to store the initial, intermediate and final data of a deduction process.

User interface A computer program that is responsible for the communication between the end users and the main computer system.

8900588.

30

APPENDIX A

Example of an animal identification prescription set

REGULATION 1 5 IF

(cover = hair)

THEN

(class = mammal).

10 REGULATION 2 IF

(production = milk)

THEN

(class = mammal).

15

REGULATION 3 IF

(cover = feathers)

THEN

20 (class = bird).

REGULATION 4 IF

(movement = flying) and 25 (production = eggs)

THEN

(class = bird).

REGULATION 5 30 IF

(food = meat)

THEN

(meat eater = yes).

69 00 588. " APPENDIX A (continued) 31

REGULATION 6 IF

5 (teeth = pointed) and (lid = claws) and (eyes = forward)

THEN

(carnivore = yes).

10

REGULATION 7 IF

(class = mammal) and (members = hooves)

15 THEN

(type = need).

REGULATION 8 IF

20 (class = mammal) and (food = ruminant mass)

THEN

(type = hoofed) and (toes = even).

25

REGULATION 9 IF

(class = mammal) and (type = carnivore) and 30 (color ** tan) and (spots = dark)

THEN

(animal = cheetah).

8900588.

APPENDIX A (cont.) 32

REGULATION 10 IF

5 (class = mammal) and (type = carnivore) and (color = tan) and (stripes = black)

THEN

10 (animal = tiger).

REGULATION 11 IF

(type = hoofed) and 15 (neck = long) and (legs = long) and (spots = dark)

THEN

(animal = giraffe).

20

REGULATION 12 IF

(type = hoofed) and (stripes = black)

25 THEN

(animal = zebra).

REGULATION 13 IF

30 (class = bird) and (movement <> flying) and (neck = long) and (legs = Tang) and (color = black and white)

35 THEN

(animal = ostrich).

8900588.

APPENDIX A (cont.) 33

REGULATION 14 IF

5 (class = bird) and (movement = <> flying) and (swimming = yes) and (color = black_and__white)

THEN

10 (animal = penguin).

REGULATION 15 IF

(class = bird) and 15 (movement = good__ flying)

THEN

(animal = albatross).

8900588.

Claims (32)

1. Circuitry-implemented, rule-based expert system device, capable of performing high-speed deductions in artificial intelligence applications, based on an application area prescription set, characterized by: (a) working memory means; (b) input means for recording external data relevant for the application area and for storing this external data as facts in the working memory means; (c) prescription memory means; (d) means for storing in the prescription memory means a prescription set for the application area, consisting of a series of instructions each defining a condition or an action; (e) means for loading successive instructions from the prescription set from the preset memory means into the working memory means, and (f) logical means for sequentially processing the instructions in the working memory means with respect to the facts stored in the working memory means for thus deducing new facts. 2. Device as claimed in claim 1, characterized in that the logical means are composed of: means for storing the deduced new facts in the working memory means, and output means for transferring the deduced new stored in the working memory means to an output device. facts. Device as claimed in claim 2, characterized in that the output means comprise an input-output interface and an interface bus, which communicates the input-output interface and the working memory means mutually communicatively. Device according to claim 1, characterized in that the working memory means comprise a random access semiconductor memory device, and the prescription memory means comprise a separate random access semiconductor memory device, as well as a data bus and an address bus connecting the working memory means and the prescription memory means, to enable data transfer between them. 8900588. 5. Link Engineering-implemented regulatory-based expert system device, capable of high-speed deductions in artificial intelligence applications, based on an application area prescription set, characterized by: (a) working memory means; (b) input-output interface means for communicatively connecting the working memory means to an external system, which input-output means comprise further means operative during the initialization of the deduction process, for recording and in the storing working means of values representing known facts relevant to the application area; (c) prescription memory means; fd) means for storing in the prescription memory means a prescription set for the application area, consisting of a series of instructions each defining a condition or an action; (e) means operative during the deduction process for sequentially retrieving from the prescription memory means and storing instructions from the prescription set in the working memory means; (f) logic means operative during the deduction process to sequentially record the respective instructions stored in the working memory means and to process these instructions with respect to the facts stored in the working memory means, thus deducing new facts which logic means also include means for storing deduced new facts in the working memory means for use during processing or subsequent instructions, and (g) the input-output means comprising means operative after completing the deduction process to transfer the facts stored in the working memory means to an output device. 6. Device according to claim 5, characterized in that the means for sequentially retrieving instructions from the prescription set comprises prescription memory boiler means with an address register for storing the address of the current instruction in the prescription memory means, and means for updating the address register with the address of the next instruction each time an instruction is fetched from the prescription memory means. The device according to claim 5, characterized in that each of the 89 00588 instructions of the prescription set comprises an operator, a condition / action flag and a pair of operands, the logic means being an instruct! for testing the condition / action flag to determine whether the instruction is a condition or an action, the decoder comprises means 5 for generating a logical result which operate when the instruction is a condition for comparing the operands in according to the operator-specified logic operation, and means operative when the instruction is an action for performing the operator-specified action on the operands. The device according to claim 7, characterized in that the logic means comprise means operative when the logic result of the comparing step is TRUE to effect the retrieval of the next instruction of the same rule. The device according to claim 8, characterized in that the logic means comprise means operative when the logic result of the comparison step is FALSE to effect the retrieval of the first instruction of the following rule. 10. Device according to claim 7, characterized in that each of the instructions also comprises a direct / immediate flag for specifying the addresses ngsmode of one of the operands. 11. Circuitry-implemented, regulatory-based expert system device, capable of performing deductions in artificial intelligence applications at high speed, based on an application area prescription set, characterized by: an integrated circuit incorporating: ( a) working memory means; (b) system interface bus means for communicatively connecting the working memory means to an external system for recording and storing in the working memory means values representing known facts relevant to the application area; (c) prescription memory bus means for communicating with an external prescription memory in which a prescription set for the application area is stored, consisting of a series of instructions each defining a condition or an action; (d) prescription memory counter means comprising an address register for storing the address of the current instruction in the external memory means; 40 (e) means for retrieving the current instruction from the prescription memory via the prescription memory bus means, and (f) logic means for recording the current instruction and for processing the instruction relating to the working memory means stored facts for thus deducing 5 new facts. Device according to claim 11, characterized in that the logical means also comprise means for storing deduced new facts in the working memory means. 13. Circuitry-implemented, rule-based expert system device, characterized by: {a) working memory means; (b) means for recording external data representing known facts and storing values representing these facts at predetermined memory addresses of the working memory means; (c) a memory device for storing a prescription set; (d) a prescription set consisting of a series of prescriptions stored in the memory device, each prescription of the prescription set comprising a series of instructions stored at successive memory addresses of the memory device; (e) wherein at least one of the instructions of each rule represents a condition to be fulfilled by the facts of a given problem, and comprising: (i) an operation code defining a logic operation to be performed; (ii) a first operand defining a first value to be compared by the logical operation, and (iii) a second operand defining the address in the working memory 30 containing a second value to be compared by the logical operation. Device according to claim 13, characterized in that (f) at least one of the instructions of each rule represents an action to be performed when all the conditions of the rule are met, and comprising: (i) a operation code defining the action to be performed; (ii) a first operand defining a value for a fact, and (iii) a second operand defining an address in the working memory means to which the values defined in the first operand are 0900588. " the should be saved. 15. An application rule set for a circuit-implemented rule-based expert system comprising a memory having a large number of memory addresses, characterized by: 5 a set of rules stored in memory; each prescription of the prescription set comprising a series of instructions stored at successive addresses of the memory; wherein at least one of the instructions of each prescription represents a condition to be fulfilled by the facts of a given problem, and at least one of the instructions of each prescription represents an action to be performed when the condition is met. A prescription set according to claim 15, characterized in that the instructions are all the same number of bits long. A prescription set according to claim 15, characterized in that certain bits of each instruction define an operand and other bits of the instruction define an operation code. A prescription set according to claim 15, characterized in that at least one bit of the instruction includes a flag indicating whether the instruction is a condition or an action. A prescription set according to claim 16, characterized in that the instructions are 32 bits long and include bits that define an operation code, bits that define a first operand, bits that define a second operand, and at least one bit that is a flag defines which indicates whether the statement is a condition or an action. A prescription set according to claim 16, characterized in that the instructions each comprise at least one bit indicating the addressing mode of one of the operands. 21. A prescription set according to claim 15, characterized in that the prescriptions of the prescription set are stored as a starting, end-of-memory sequence of instructions at consecutive memory addresses, with a prescription index starting at consecutive memory addresses. the opposite end of the memory is stored, the rule index comprising a series of memory addresses defining the initial memory address of each rule of the rule set. 22. An application rule set for a circuit engineering 40 implemented rule-based expert system comprising a memory with a large number of memory addresses, characterized by: a set of rules each consisting of a set of instructions a predetermined number of bits long and are stored in successive memory addresses in memory, 5 where certain instructions of each rule represent a condition to be fulfilled by the facts of a given problem, further instructions of each rule represent an action to be performed when that rule is fired, and a rule index also stored in memory which comprises a series of memory addresses of the memory corresponding to the initial memory address of each prescription of the prescription set. An apparatus according to claim 22, characterized in that the prescriptions of the prescription set are stored on successive memory addresses starting at one end of the memory and wherein the prescription index is stored on successive memory addresses starting at the opposite end of the memory. The device according to claim 22, characterized in that each of the instructions of the prescription set comprises an operator, a condition / action flag and a pair of operands. 25. An application rule set for a circuit-implemented rule-based expert system comprising a memory having a large number of memory addresses, characterized by: a set of rules each consisting of a set of instructions a predetermined number of bits long, wherein the instructions of each prescription are stored in memory at successive memory addresses, the prescriptions of the prescription set being stored sequentially beginning at one end of the memory; which instructions include bits that define an operation code, bits that define a first operand, bits that define a second operand, at least one bit that defines a flag indicating whether the instruction is a condition or an action, and at least one bit that indicates the addressing mode of one of the operands, and a rule index, also stored in memory, consisting of a series of memory addresses of the memory, corresponding to the initial memory address of each rule of the rule set, that rule index at consecutive memory address 8900585. sen, starting at the opposite end of the memory from which the prescription set begins. 26. Circuitry-implemented, rule-based expert system method, for performing high-speed deductions in artificial intelligence applications, based on a prescription set for an application area, characterized by: (a) storing in a working memory known facts which are used for the application area are relevant; (b) storing in a prescription memory a prescription set for the application area, consisting of a series of instructions each defining a condition or an action; (c) loading an instruction from the prescription set from the working memory into working memory, and (d) processing the instruction in working memory with regard to the facts stored in working memory. The method of claim 26, characterized by repeating steps (c) and (d) for successive instructions from the prescription set to deduce a new fact, and storing the deduced new fact in working memory. A method according to claim 27, characterized in that the step of storing a prescription set in a prescription memory comprises storing the instructions of the prescription set in successive memory addresses of the prescription memory, and in that a step of updating a memory address register with the address of the next instruction is executed each time an instruction is loaded from the prescription memory. 29. A method according to claim 26, characterized in that the step of storing a prescription set in a prescription memory comprises storing instructions on successive memory addresses of the prescription memory, which includes an operator, a condition / action flag and a pair of operands, and wherein the step of processing the instruction includes examining the condition / action flag to determine whether the instruction is a condition or an action. A method according to claim 29, characterized by the step of comparing the operands according to the operator-specified logic operation for outputting a logic result when the instruction is a condition. A method according to claim 29, characterized by the step of performing the action specified by the operator on the operands when the instruction is an action. 6900588. 32. Circuitry-implemented, rule-based, expert system method for performing high-speed deductions in artificial intelligence applications, based on an application area prescription set, characterized by: 5 (a) defining a set of properties relevant to the application area; (b) assigning each property of the set to a specific memory address in a working memory; (c) for a particular problem to be solved by the expert system, selecting from the set those properties which have values that are known; Cd) storing the values of the known properties in the working memory at the appropriate memory addresses designated for those properties; (E) storing in a prescription memory a prescription set for the application area, the prescription set comprising a set of instructions; Cc) loading successive instructions from the prescription set from the working memory into working memory and processing the instructions relating to the values of the properties stored in working memory, thus deducing a value for an unknown property; and (d) storing the deduced value in the working memory at the memory address corresponding to that property. +++++++ 8900588