GB2217068A - VLSI hardware-implemented rule-based expert system - Google Patents

Description

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22 17 U 6 8 VLSI HARDWARE IMPLEMENTED RULE-BASED EXPERT SYSTEM APPARATUS AND METHOD This invention relates to a rdle-based expert system, and more particularly to a hardware implemented rule-based expert system suitable for perfonAng high speed inferencing in 5 artificial intelligence (Al) applications.

Expert systems are a class of computer programs that incorporate artificial intelligence (AI) technology to address problems normally thought to require human experts or specialists. In a rule-based expert system, expert knowledge in a particular application domain is represented in the form of a series of rules,."production rules". In the operation of a typical expert system the user, through a convenient user interface, supplies the expert system with certain known information about a particular problem, and the exert system applies the production rules to this known information to deduce facts and solve problems pertaining to the application domain. For further background information pertaining to expert systems, reference is made to the following articles: Robert H. Michaelsen, et al., "The Technology of Expert Systems", Byte

Magazine, April 1985, pp. 308-312; Beverly A. Thompson, et al., "Inside an Expert System", Byte Magazine, April 1985, pp. 315330; Michael F. Deering, "Architectures for AI", Byte Magazine, April 1985, pp. 193-206.

Successful expert systems have'been developed for a number of application domains: for making medical diagnoses, for identifying organic compounds, for selecting oil drilling muds, and so forth. Additionally, a number of domain-independent expert system shells in software form have been developed to facilitate building rule-based expert systems for specific 1 1:2 P-3lication domains. Several commercially available expertsystem tools are described in the above-noted articles. Typically, these expert systems and expert system tools are in the form of software programs designed to run on a general purpose computer or microcomputer. The software program provides an interactive session between the user and the expert system in which the expert system asks questions of the user and employs its expert knowledge base to solve problems and provide advice to the user.

There has been considerable interest in expanding the use of expert systems into other practical applications, and especially in developing expert systems capable of use in realtime applications. Such systems would be useful, for example as a control system for various applications, such as manufacturing processes, process control, guidance systems, robotics, etc.

However, a major limitation in the development of complex, real time AI systems is the speed of computation. In order to make effective practical use of artificial intelligence technology, the efficiency and speed of computation must be increased.

Significant efforts have been made to improve the speed of Al processing by improving aAd streamlining the software tools used in AI processing, such as the AI languages. It has also been recognized that performance improvements can be achieved by custom designed hardware specifically engineered for artificial intelligence processing. As indicated in the Deering article noted above, one approach with respect to hardware architectural improvements has involved refinements in the processor's instruction.set to allow the processor to operate more quickly. Attention has also been given to developing parallel processing architectures which would allow the AI computations to be carried il 3 or' in parallelism. The article also notes that custom VLSI hardware could be employed to accelerate p articular operations such as matching and fetching, parallel-processor communication and signal-to-symbol processing.

An important object of the present invention is to improve the speed and efficiency of rule-based expert systems by providing an inference engine which is implemented in hardware. More particularly, the present invention provides an application specific integrated circuit designed especially to perform high speed inferencing for a rule-based expert system.

The hardware-implemented rule-based expert system apparatus and method of the present invention is referred to herein by the acronym REX (Rulebased EXpert), and includes a working memory in which, at the beginning of an inferencing operation, is stored known information or facts pertaining to the application domain. Additionally, the apparatus includes a rule memory for storing a rule set for the application domain. The rule set is comprised of a series of instructions, each defining a condition or an action. Means is provided for loading from the rule memory into working memory'successive instructions of the rule set, and a logic means is provided for successively executing the instructions in working memory with reference to the stored facts in working memory to thereby deduce new facts. During the inferencing operation, as new facts are deduced, they are stored in working memory and may be used during the execution of subsequent instructions of the rule set to derive additional facts. Upon the completion of the inferencing operation, the facts stored in working memory are transferred to an output device.

4 Each of the instructions of the rule set n-ay include ar operator, a condition/action flag, and a pair of operands. The logic means my include an instruction decoder for testing the condition/action flag of each instructio n to determine whether A the instruction is a condition or an action. If the instruction is a condition, the operands are compared in accordance with the logical operation specified by the operator to-generate a logic result (e.g. true or false). If the instruction is an action, the action specified by the operator is performed on the operands.

The working memory and the logic means may be suitably provided in an integrated circuit. The rule memory may either be external to the 'integrated circuit and connected to the working memory via a suitable external memory bus, or the rule memory may also be provided on the integrated circuit with appropriate data bus interconnections with the working memory. Since the application rule set is stored in a memory device, the REX inference engine is domain independent and can be used in any number of different applications simply by installing a different application rule set in the rule memory. The structure of the rule memory and the data structare of the application rule set are designed to greatly enhance the efficiency of the inferencing process.

To illustrate the versatility and general wide applicability of the present invention, the detailed description which follows shows how the REX inference engine can be used as co-processor in conjunction with an existing computer or microcomputer to provide an expert system capable of performing inferencing at rates significantly greater than that which could be performed by conventional software implemented inference i (..". -1 i- ei_-nes. The REX inference engine can also be utilized however, in many other applications, such as a stand-alone system when provided with an appropriate internal control system, user interface, and input/output devices.

The REX inference engine is capable of performing realtime knowledge processing based upon current VLSI technology. The speed of problem solving is measured by logical inferences per second (LIPS) instead of floating point operations per second (FLOPS). One LIPS is equivalent to approximately 100 to 1000 10 FLOPS on a conventional computer.

The in--,ention will be further described bv wa-.- of non-limitative example with re-f-e-rence to the accompanyina drawings, in which:- Figure 1 is a perspective view illustrating how the REX 15 inference engine of the present invention may be utilized as a co-processor in a conventional personal computer; Figure 2 is,a more detailed view of a co-processor board employing the REX inference engine; Figure 3 is a block s6hematic diagram showing the data 20 flow for the REX engine; Figure 4 is a block diagram illustrating the rule base structure for the REX engine; Figure 5 is a diagram showing the data structure of the instructions which are stored in rule memory; Figure 6 is a diagram illustrating the operation codes format used in the REX chip; Figure 7 is an overall block diagram of the major functional components of the REX chip; (9 Figure 8 is a diagram illustrating the data bus b:t assignment for 1/0 read/write operations; ' Figure 9 is a flowchart showing the inferencing flow of the REX chip; and A Figures 10 to 12 are timing charts for the REX chip showing the timing of the read mode, write mode, and external memory respectively.

is Referring now more particularly to the drawings, Figure 1 illustrates an expert system in accordance with the present invention which is designed to operate on a microcomputer 10, such as an IBM AT Personal Computer with an added Rule-based EXpert system (REX) co-processoi7 board 11. The REX board 11 consists of a REX chip 12, external rule memory 13 and an 1/0 interface 14. The REX board is illustrated in Figure 2 in greater detail. An application rule set for a particular application domain, indicated at 15 in Figure 2, is stored in external rule memory 13. Thus, the REX chip 12 is domain independent and can be utilized in a variety of different applications.

Referring to Figure 2, each component of the REX co30 processor board 11 is explained as follows:

i 1 1/0 Interface: The 1/0 interface 14 is responsible for the communication between the personal computer 10 and the REX co-processor board 11. External data is transferred from the personal computer 10 to the REX board 11' via the 1/0 interface 14. In the preferred embodiment illustrated herein, a DMA channel provides a communication link between the REX board 11 and the personal computer 10. A software program run by the personal computer is employed to provide an easily understandable user interface.

REX Chin: The REX chip 12 is a hardware inference engine and forms the heart of the REX co-processor board 11. Two major components of the REX chip are working memory and control logic. Before the inferencing process is begun, the working memory is initialized with external data from the 1/0 interface.

External data pertaining to facts which are known about the application domain are stored in particular memory locations of the working memory. During the inferencing process, the working memory is a temporary storage for intermediate data. When the inferencing process is completed, the working memory contains the results of the inferencing process, which is then transferred to the personal computer via the IO interface.

Rule Memory: The knowledge engineer extracts a set of production rules, called an application rule set 15, from the application domain and this rule set is stored in the rule memory 13. During the inferencing process, the REX chip 12 refers to rule memory 13 for rule information. The structure of the rule memory is well designed to match REX chip requirements and to reduce memory space. The data structure of the application rule set stored in rule memory is designed to greatly enhance the efficiency of the inferencing process. Further details about the 1 st. Acture of the rule memory and the application rule set stored therein are provided hereinafter.

The rule memory can be a ROM, RAM, EPROM, or other suitable memory device. If a RAM is use'd for rule memory, an A initialization program is utilized to Initially install the application rule set 15 in the external memory 13.

While the specific embodiment illustrated herein demonstrates how the REX chip 12 can be utilized as a coprocessor for a personal computer, persons skilled in the art will recognize that the hardware-implemented rule-based expert system of the present invention (REX) can be utilized in many other specific applications. For example, it can be utilized as a stand-alone sytteM. In such event, a control system is provided to handle user interface and 1/0 interface, and additional 1/0 devices such as a keyboard, graphics display, etc. are provided to permit communication between the REX board and the user.

Inferencing Mechanism There are several types of inferencing methods that can be used to solve a problem in a rule-based expert system. Some of the major inference methods ire forward chaining, backward chaining, and combination chaining. The inference engine specifically illustrated and described herein uses the forward chaining inferencing method with production rules.

The rules of the rule-based system are represented by production rules. The production rule consists of an if part and a then part. The if part is a list of one or more conditions or antecedents. The then part is a list of actions'or consequents.

Thus, a production rule can be represented as follows: - r k - if 61 then condition - 1 ' condition_2.,, condition n action_l, action_2, action_n 4 If the conditions (condition_l, condition_2,..

condition_n) are satisfied by the facts of a given problem, we can say that the rule is triggered. The expert system can then execute the given actions. once the actions are executed then the rules are said to be fired. These particular actions may change other conditions, which may in turn fire other rules. The flow of rules firing will continue until the problems are solved, or no other rules can be satisfied. This method of rule firing is moving forward through the rules, hence we call this forward chaining. Forward chaining is also referred to as a deduction system or facts driven because the facts guide the flow of the rules being fired.

The triggering of the rules does not mean that the rules are fired, because the conditions of several other rules may be satisfied simultaneously, and all being triggered. Should this happen, it is n6cessary to apply a conflict resolution strategy to decide which rule is actually fired. A conflict resolution strategy is a process of selecting the most favorable rule where more than one rule is satisfied. Examples of conflict resolution strategies are the following:

I. The rule containing the most recent data is selected. This strategy is called Data Recency Ordering.

2. The rule which has the most complex of the toughest requirements is selected. This is also called Context Limiting Strategy.

/0 3. The rule declared first in the list is selected. This is called Rule Ordering.

EXAMPLE 1 Forwarding Chainincr _Examble A This example provides a general illustration of the operation of a rule- based expert system. For this illustration, refer to the Animal Identification Rule Set in-Appendix A. This rule set tries to identify an animal by giving its physical characteristics. Assume that the following characteristics have 101 been observed: the animal has hair, the animal eats meat, the animal has a tawny color, the animal has black stripes. These observations are translated into the following f acts: - covering = hair, food meat, color tawny, stripes =,.black. Given these facts, RULE 1 is triggered. According to the rule, we deduce that class = mammal Now the system takes this as a new fact, that the-animal is a mammal. Hence RULE 2 through RULE 4 cannot be triggered. The condition of RULE 5 is valid, thus the system will deduce that the animal is a carnivore. carnivore = yes So far, the system has deduced two new facts that can be used.

The first three conditions of RULE 9 are true, but the last 1 c. idition is not, thus RULE 9 failed. RULE 10 is triggered-and can be fired. The system thus deduces that the animal is a tiger.

animal = tiger The Inferencing does not stop here,. because there are more rules. In this case none of the other rules can be satisfied. The system identifies that the animal is a tiger.

The example shows the inferencing method by working forward from the current situation of facts or observations toward a conclusion.

REX Inference Engine Architecture The major components of the REX inference engine are shown in greater'detail in Figure 3. The REX chip itself has three primary functional components: the working memory 16, an arithmetic logic unit (ALU) 17 and control logic 18. In the embodiment illustrated herein, the rule memory 13 is a separate memory device connected to the working memory 16 by a data bus 21. However, those skilled in the art will recognize that the rule memory could, if desired, be integrated into the REX chip itself. The 1/0 interface 14 is communicatively connected to the working memory by a system interface bus, generally indicated at 22. The control logic is schematically represented in Figure 3 and indicated by the reference character 18. In general, the function of the control logic 18 is to control the operations of the other elements, such as the ALU 17 and working memory 16. Data Flow in the REX Inference Enqine The flow of data for the REX engine will be best understood from Figure 3 and the description which follows. The circled numbers in Figure 3 correspond to the following numbered topic headings:

0- 1. Input-Data The user inputs the facts to the system through a user interface program on the personal computer 10. The user presents the facts in a predefined syntax. For instanceF using the factual data of the Example 1 and the Rule Set of Appendix A, - the user would enter the following: covering = hair color = tawny etc.

The user interface program converts each factual observation into a values represented by a pair of binary numbers. The first part of the pair is an address and the second part of the pair is a value.

1 Address 1 Value 1 In the above example we have 20 (address $32)covering = (value#10)hair, (address $58)color = (value W55)tawny.

. etc.

where, I'$" and 11#11 indicate that the number referred to is an address and a value, respectively. In the above case covering is mapped to address 32 (no other word maps address 32). Thus each word is assigned to a unique address number. The value hair is stored in address 32. These numbers are used in Step 2.

2. Store Facts into Workinq Memory In Step 2 the facts are stored in Working Memory.

1.:

1 -.

P\-.w 1 /3 3. Fetch Rules into Workiner Memory External Memory is used to store rules pertinent to the application domain. Each rule is represented as follows:- IF condition 1 dnd condition 2 and THEN action 1 action 2 A condition element is:

(class = mammal) Similarly, an action element is:

(type = ungulate) Each element, whether condition or action part of the rule, is represented intenally as an instruction in the format shown below:

1 Operandl 1 Operand2 1 operator 1 Dir/lmme 1 Act/Cond 1 Each-instruction is of a predetermined length, for example 32 bits. Operandl represents an address of Working Memory. Depending on the value of Dir/Imme field, Operand2 is either an address or a value in the WorkiAg Memory. Dir/Imme field specifies whether the addressing mode of Operand2 is Direct or

Immediate. The Act/Cond field specifies whether the element refers to condition or action part of a rule. The Operator field specifies the type of operator used in the condition part of the rule. Example operators are: equal to (=),.greater than (>), less than (<), etc.

cycle.

4-5 Inferencing Cycle The following steps are executed during the inferencing c1 /H 4.1 Fetch External Memory.Element A rule is fetched from Rule Memory 13 and the Cond/Act field of the first instruction of the rule is examined to check if it is a condition or an action. Ifthe instruction is a

A condition element, then the procedure.described in Section 4-1- is used. If it is an action, then the procedure described in Section 4.1.2 is used.

4.1.1 Matching Rule Condition Element to Working Memory The address in Operandl is loaded into ALU (Step 4). Next the Dir/Imme field is checked to see if Operand2 is Direct or Immediate. If it is immediate, then the value of Operand2 is directly input to ALU, otherwise the contents of the address pointed by Operand2 is input to ALU. The inputs to ALU are compared by the ALU using the operator (Operator field) to determine whether the condition is true or false. If the condition is true, the next successive instruction of the rule is examined by repeating the sequence of steps indicated in section 4.1. If the condition element is false, then this rule is discarded and the next rule is tested by repeating the sequence of steps in Section 4.1.

4.1.2. Action Part The Dir/Imme flag of the action element is first checked. If it is Direct, then the value stored at Working Memory location Operand2 is copied to the Working Memory address represented by Operandl. If Dir/Imme flag is Immediate, then Opera.nd2 is copied to the Working Memory address represented by Operandl. After performing the action defined by the instruction, the next successive action instruction of the rule is read and the procedure described in Section 4.1.2 is repeated.

i i 1 i t..:.1 1.

/5- 7 the action instruction is the last instruction of the rule, then, next rule is tested by repeating the sequence of steps in Section 4.1.

6. Facts to Data A After all the rules have been processed, the control is transferred to the 1/0 interface 14. The numerical representation of the facts is translated to a form which will be readily understood on the user.

7. -Data Output The 1/0 interface will then output the data to the personal computer 10.

EXAMPLE 2 REX Data Flow Exarple This example illustrates how the REX chip solves the problem described above in Example 1. Again, the numbered topic headings correspond to the circled numbers in Figure 3. Refer to Appendix A for the complete Animal Identification Rule Set.

1. Input External Data The data or observation made is:

the animal has hair, the animal 6ats meat, the animal has a tawny color, the animal has black stripes.

enters 1/0 interface and is translated translated into the following facts:

$32) covering = (value #10) hair, $41) food (value #3) meat, $58) color (value 55) tawny, $35) stripes = (value W8) black-.

The above data 25 into facts. The data is (address (address (address (address 16 2. _Store Facts in Working Memory The address represents the location in Working Memory. For example, address location 32 stores the value of 10.

3. Load Instruction An instruction-is loaded from Rule Memory. The first instruction of RULE 1 is a condition, and takes the form of:

(address $32) covering EQUAL (value #10) hair 4. Load Operands a. Condition The value of address location 32 is loaded into ALU, in this case 10. The comparison operation of ALU is:

(value.#10) hair EQUAL (value #10) hair This result is true If the instruction is:

(address $32) covering EQUAL (value #11) feathers, the output of ALU will be false. The control returns to STEP 3.

b. Action If the instruction is an action such as:

(address $77) clAss MOV (value #20) mammal ALU will get the value 20 and will store it at the address location 77.

5. Store Facts in Working Memory The value of 20 is deduced from RULE 1 and is instructed to be stored at address location 77. The control returns to STEP 3.

I- I- 6. Facts to Data In this example the value at the (address $88) class is transferred to I/0 interface. From the facts, the value at address location 88 is (value_#100) t er. ' - 7. Data Output The value 100 is translated by the interface to tiger. Rule Base- Structure The application rule set 15 which is stored in working memory 16 is divided into two parts - STRUCT and RULES. A set of conditions in each rule is grouped together in adjacent addresses. Also, a set of actions in each rule is grouped together in adjacent addresses. These groups can be stored in the RULES part of working memory in the following fashion:

- Rule #1 address xxxl condition 1 1 address xxx2 condition_1_2 address xxxm condition 1 Tn address yyyl action - 1 - 1 address yyy2 action_l_2 Rule #2 address zzzl condition_2_1 Since conditions and actions are sequentially stored in different memory addresses, the representation of rules can be structured by using the starting address of each rule. Thus, the production rule can be expressed as:

if XXX1 then yyY1 if zZZ1 then 1g This format shows that if a group of conditions ata certain address is TRUE, then execute the group of actions at the address specified in then- part. Now, if the first rule fails then the control mechanism jumps to the'starting address of the next rule. There is no need of the end-indicators for each rule, hence REX does not waste time on searching end-indicators.

Rule Base Structure of-REX is illustrated in Figure 4. For this version, External Memory of 64K X 32 ROM is used to store the Application Rule Set 15. To maximize the utilization of limited memory, STRUCT and RULES are stored at both ends of Rule Memory 13, respectively. STRUCT starts from address OOOOH and increases. RULES starts from address FFFFH and decreases.

The detailed structure of Rule Memory is shown in Figure 5. STRUCT stores the address index which points to the starting address of each rule in RULES. The size of Rule Memory is 64K, so only 16-bit lower-half word is used.

Each condition or action is represented as a 32-bit word instruction executed by REX. The condition is basically a logical comparison of two given operands. The actions are organized in a similar fashion. The operators of the actions are basically logic operators and aii assignment operator. There are two operands for each operation: operandl and operand2. Operand2 can be of two forms: direct or immediate. As shown in Figure 4, the direct operand is a pointer to an address in the working memory represented by the symbol 1$1 and the immediate operand is an integer represented by 111.

Instruction Set for REX Inference Enqine As shown in Figure 5(b), instructions of REX are always 32-bit long. The operation Code (6 bits), OP1 (13 bits), and OP2 (13 bits) are assembled into one 32-bit instruction. Each rule a 1.- - 1 -P a given Application Rule Set has condition and action par:ts. Therefore, REX has two types of instruction set:

Condition Instructions: This type of instruction is used to check if the condition is True or False. This allows users to specify different logic relations between two operands, such as "Equal", "Greater Than", etc. The execution result of an -Condition Instruction can only be True or False, which will affect the-next execution sequence.

Action Instructions: This type of instruction is 10 executed only when all the conditions of the current rule are True. The result of the execution of the action is always stored in the first operand.

The instructions and the corresponding operation codes are summarized in Table 1. - TABLE 1 - REX OPERATION CODES Not Equal to; Is operandl <> operand2 ? Greater Than; Is operandl > operand2 Less Than; Is operandl < operand2 ? Greater than or Equal to; Is operandl ≥ operand 2 ? Operation Codes operation OX0000 EQ OX0001 NE OX0010 GT OX0011 LT OX0100 GE OX0101 LE 1X0000 NOT 1 Description

Equal To; Is operandl = operand2 ? Less than or Equal to; Is operandl ≤ operand2? logic NOT operandl; Each bit of the operandl is complemented and the result is stored in operandi in Working Memory C J0 Table 1 Continued so Operation Codes operation Description

IX0001 AND logic AND operandl and opera.nd2; Logic AND operation it;-performed on t the correspondent bits of the.operandl and operand2.

The result is stored in operandl in Working Memory.

IX0010 OR logic OR operandl and operand2; Logic OR operation is performed on the correspondent bits of operandl and operand2. The result is stored in operandl in Working Memory.

1X0011 MOV MOVe oPerand2 to operandl; The content of the operand2 is stored in operandl in Working Memory.

1X0100 SHR SHift operandl Right 1 bit; The least significant bit is discard and a zero is shifted into the most significant bit; the result is stored in operandl in Working Memory.

1X0101 SHL SHift operandl Left 1 bits; The most significant bit is discardand a zero is shifted into the least significant bit; the result is stored in operandi in Working Memory.

XX0110 imp JuMP to new address of External Memory; For JMP instruction, the least significant 16 bits of the instruction is loaded to Cl register which points to the new rule in External Memory.

XX0111 EOR End of External Memory.

operandi is direct-addressed data (WM[OP1]) from Working Memory.

operand2 can be direct-addressed data (W14[OP2]) or an immediate data (OP2).

is k - C2 / The format of the opcode is displayed in Figure 6,. MSB (Most Significant Bit), i.e. F1, of the opcode is used to specify the type of the instruction. If F1 is 0, it is a Condition instruction; otherwise it is an Action instruction.

A A Condition instruction always has two operands. Whereas, an Action instruction may have only one or two operands depending on the operation needs.

REX allows two types of addressing mode: immediate and direct addressing. First operand always uses direct addressing mode. The second operand can be an immediate data or direct- addressed data. The addressing mode is distinguished by checking second MSB, i.e. F2, of the operation code. When F2 is 0, second operand is an immediate data. otherwise, the second operand is a direct-addressed data.

Functional Descrivtion of the REX ChiD Figure 7 provides a detailed block diagram of the REX chip 12. To avoid repetitive description, elements which have been previously described in connection with earlier drawing figures will be identified with the sane reference characters.

Table 2 below lists the name, 1/0 type, and function of each input and output illustrat6d in Figure 7.

ji TABLE 2 - PIN DESCRIPTION OF REX so Symbol Type CLK 1 u-s 1 EMCS 0 IOR I IOW I Name and Function Clock Input:"CLY% controls the internal operations of REX chip. The maximum clock rate is 8 MHz.

Chip Select: Chip Select is an active low input used to select REX chip as an 1/0 device when CPU wants to read/write REX chip's internal registers (WM, WMC, C/S).

External Memory Chip Select: EMCS is low active. When REX is in inferencing mode, EMCS is used to select External Memory for information of the rule.

1/0 Read: IOR is low active. When both ES' and IOR are active, CPU has read access to REX chip's internal regist6rs (WM, WMC, C/S).

1/0 Write: IOW is low active. When both E-S and IOW are active, CPU has write access to REXIs internal registers (WM, WMC, C/S).

i i i i cl 23 Table 2 Continued is so Symbol Type Name and Function READY 0 Ready: READYI s low active. READY is A a synchronization signal for external data transfer. READY goes low when REX is ready for new data.

RESET I Reset: RESET is high active.- RESET is used to initialize REX chip state.

All the registers are reset after RESET is activated.

INT 0 INTerrupt Request: INT is high active.

REX chip uses INT to interrupt CPU when REX chip finished the inferencing process.

AO - Al I Address: The two least significant -address lines are used by CPU to control the data transfer to REX chip's internal registers (WM, WMC, CIS).

DO-D15 1/0 Data Bus: Data Bus lines are bidirectional three-state signals connected to system data bus. The Data Bus are output signals when IOR is active. The Data Bus are input I I signals when IOW is active.

k. -- 1 1 C2 h Table 2 Continued Symbol Type Name and Function MAO-RA15 0 External Memory Address Bus: When REX chip is in inferencing mod&, External Memory Address Bus is used to address a rule in External Memory, MDO-MD31 1 External Memory Data Bus: When REX chip is in inferencing mode, External Memory Data Bus sent the information regarding each rule to the REX chip.

WM: -Working Memory WMC: Working Memory Counter register C/S: Control/Status flag registers The identification of each register, and the function of each is as follows:

- WM (Working Memory): Working Memory 16 is used to store the intermediate data during the inferencing process.

Before REX starts the inferencing process, Working Memory is loaded with facts from user's iput. The size of Working Memory limits the amount of user inputs to REX at any one time. In the illustrated embodiment, Working Memory is a 4K X 8 Static RAM.

- WMC (Working Memory Counter) Register: WMC is an 13bit increment counter with the capability of parallel load. During the 1/0 -mode, WMC is used as Working memory address counter for data transfer. When data transfer is proceeding, WMC will increment automatically. The content of WMC can be set by CPU before data transfer starts.

J5 - Cl Register: Cl is an 16-bit increment counter-with the capability of parallel load. During the inferencing process, Cl points to one of the rules addresses in the STRUCT part 'Of the Rule Memory 13. Cl increments by one 11 be. for4 REX goes to the next rule. For JMP instruction, Cl will be loaded with a new value instead of incrementing by one.

- C2 Register: C2 is an 16-bit decrement counter with the capability of parallel load. C2 points to the RULES part of Rule Memory. If no false condition occurs in a rule, C2 decrements by one before REX goes to the next condition or action. When a false condition of a rule is detected, C2 will be loaded with the starting address of the next rule instead of decrementing by one.

- - OP Register: OP Register contains three parts:

Operation Code, OP1, and OP2, which comprise an REX instruction. Operation Code is a 6-bit register that stores the operator of an instruction. Both OP1 and OP2 are 13-bit data registers that store theaddress of operandl and operand2 in Working Memory respectively.

- OPI Register: OPI Register is a prefetch Register used to store the prefetch instiuction for OP Register. REX Will execute the prefetch instruction-except that when an JMP Instruction or a false condition occur.

- SI (Start/Idle) Control Flag: SI is used to identify REX operation status: Inferencing Mode and 1/0 Mode. SI is set by CPU after the system sent all the facts to Working Memory. SI has the value 1 during the Inferencing Mode. SI is reset by REX each time the inferencing process stops, then REX switches to 1/0 Mode.

j & - IE (Interrupt Enable) Conrol Flag: IE is set by CPU at the same time with SI flag. REX is granted the interrupt enable before REX goes to inferencing mode. IE is used with IRQ flag to generate interrupt signal. IE flag'is reset by CPU at 5 the end of the interrupt service routine.

- IRQ (Interrupt ReQuest) Status Flag:. When inferencing process stops, IRQ is-set by REX to indicate that REX is requesting an interrupt to CPU. IRQ is and-gated with IE flags to generate interrupt signal INT. IRQ is reset by CPU 10 after the interrupt is acknowledged.

When REX is in 1/0 Mode, CPU can read or write REX registers. The signals and affected registers are listed in Table 3.

TABLE 3 - DEFINITION OF REGISTER CODES Register operation CS low IOR A1 1 AO Read Status Registers 0 1 0 0 0 Write Control Registers 0 0 1 0 0 Read Working Memory Counter. 0 1 0 0 Write Working Memory Counter 0 0 1 0 1 Read Working Memory 0 1 0 1 0 Write Working Memory.0 0 1 1 0 REX Chip is Not Selected 1 X X X X J 1 Operational Modes REX has two operation modes: - 1/0 Mode - Inferencing Mode A Control flag SI is used as a mode flag. REX switches to the other mode when SI flag is changed.

Before REX get into Inferencing Mode, REX has to load all the user-input facts from the host system into Working Memory of REX. REX is switched from 1/0 Mode to Inferencing Mode when SI flag is set by host. After the inferencing process is terminated, the results will be transferred from Working Memory to the host system.

During'the 1/0 operation, the host system can read or write specific registers when REX chip is selected. The control of read/write operations and the selection of registers are controlled by a set of control lines which are listed in Table 3. During reading and writing of WMC and CIS registers, only some bits of the system data bus are used. This is illustrated in Figure 8.

Once Working Memory is loaded with user-input facts, REX will start the inferencing rocess from the first rule in External Memory. The inferencing flow of REX is shown in Figure 9.

There are 3 different machine cycles for REX in inferencing Mode.

- T1 Cycle: T1 is Rule Fetch Cycle. T1-cycle is executed only at the very beginning of the inferencing process or when JMP instruction occurs. T1 cycle fetchs the starting address of a rule in External Memory to C1 register. Cl is J7 ar+ually a Rule counter, which points the starting address of currently inferenced rule.

- T2 Cycle: T2 is Instruction Fetch Cycle. T2 cycle fetchs the first Condition Instructioh of-each rule to P.EX 4 registers. T2 cycle is executed when one of the conditions of a rule is false and the execution starts from the first instruction of the next rule. C2 can be regarded as an Instruction counter points to a Condition Instruction or an Action Instruction which is currently executed in ALU.

is Cycle. There T3 Cyc1e: -T3 cycle is Instruction Execution are several cases of the T3 cycle:

Condition Instruction/Immediate Data Condition Instruction/Direct Addressing Action Instruction/Immediate Data Action Instruction/Direct Addressing imp STOP (End of Rule) The instruction prefetch cycle is overlapped with T3 cycle. -If a JMP instruction occurs, execution sequence will go to T1 cycle. If the result of a Condition Instruction is false, the execution sequence will go to T2 cycle. If no JMP instruction and no false condition occurs, REX will use the prefetch data then go to T3 cycle.

REX will go through the same process over and over again, until all the rules in External Memory are inferenced.

When inferencing process stopped, SI flag is reset to 11011. Then REX switches from Inferencing Mode to 1/0 Mode.

Timing Chart The timing charts for REX in the 1/0 Read Mode, the 1/0 Write Mode, and for external rule memory are shown in Figures 1012 respectively. The A.C. (Alternating Current) characteristics of REX in 1/0 Mode is listed in Table 4.

f L 0 1.

1-1 c TAME 4 - A. C. SPECIFICATION

Symbol Parameter Min Typ Max Unit TAS 1/0 Address Setup TiTrve. 20 ns TAH 1/0 Address Hold Tijre 10 ns TIW 1/0 Read/Write Signal Width 60 - -:rLs TOD Data Output Delay Tine 40 ris Toll Data Output Hold Tim 10 -- ns TDS Data Setup ThTe 20 --- ns; TD11 Data Hold Tire 10 ns TM READY Signal Setup Tijm 0 ns TRD READY Signal Delay Time 0 CLK1 ns TRq READY Signal Width CIYI-10 CLK1 CLK+10 ns TMAW External Memory Address Signal Width Cll2-20 =2 CLY\2+20 ns MIMC External Memory Address Access Tim 170 ns TMH External Memory Data output Hold Tine 0 ns TCSS External Memory Chip Select Setup Tire 0 ris TCSH Extexnal Me1wry Chip Select Hold Time 0 -- -ns TMOZ External Memory Output Floating 20 ns 1..

I- Antecedent Application Domain Application Rule Set ASIC Consequent CPU Co-processor Control Logic 2 0 DHA 3 0 Fact External Data External Memory Inferencing Inference Engine 1/0 Interface GLOSSARY The 11 part of a production rule.

The subject or field to which the expert system pertains.

A set of rulbs, which are extracted by knowledge engineer, pertaining to a specific application domain. ' Application Specific Integrated Circuit is a custom-designed integrated circuit for a specific application.- The then part of a production rule.

Central Processing Unit: An operational unit which processes instructions and data.

A specialized processor which cooperates with a host computer to enhance the performance of the entire system.

A custom circuit that controls all the operations necessary for the REX chip.

Direct Memory Access: A commonly used communication method between a host computer and computer peripheral devices. DMA provides the most efficient way to transfer a block of data.

A block of binary data resides in a host computer memory.

A physical memory which stores Application Rule Set.

A truth known by actual experience or observation. A group of facts are collected to combat conjectures.

Interpreting a rule of Application Rule Set.

A problem-solving control mechanism for an expert system.

A kind of device driver responsible for the communication between the computer host system and computer peripheral devices.

1 Y-owledge Engineer PC RAM PC/DOS Production Rule ROM Working Memory User Interface Rule Base Structure 1 A person who extracts knowledge and facts of a particular application domain and converts them into Application Rule Set.

Personal Compuer.

The Disk ope3rating System of Personal Computer, which managers the read/write operations of a disk driver.

A rule specified in an if-then format.

Random-Access Memory: An electronic memory stores binary information which can be read-or-write-accessed.

Read-Only Memory: An electronic memory storage which stores the binary information. A ROM is read-accessed only; it does not have a write capability.

An organization which stores the production rules in an efficient way to save the memory space and processing time.

A RAM that resides in the REX chip to store the initial, intermediate, and final data of an inferencing process.

A software program responsible for the communication between the endusers and the computer host system.

i1. ^.

1 3C2 APPENDIX A Example of Animal Identification Rule Set is RULE 5 - IF RU LE 1 1 p (covering = hair) THEN (class = mammal).

RULE 2 IF (produce - milk) THEN (class = mammal).

RULE 3 IF (covering = feathers) THEN (class- bird).

RULE 4 IF (movement fly) and (produce eggs) THEN (class = bird).

(food = méat) THEN (carnivore = yes).

-1 W 33 RULE 6 IF THEN RULE 7 IF THEN RULE 8 IF THEN RU LE 9 I F THEN RULE 10 IF THEN (teeth = pointed) and (limb) = claws) and (eyes = forward) (carnivore = yes).

(class = mammal) and (limbs = hoofs) (type = ungulate) (class mammal) and (food cud) (type -- ungulate) and (toed = even).

(class = mammal) and (type = carnivore) and (color = tawny) and (spots = dark) (animal = cheetah).

(class = mammal) and (type = carnivore) and (color = tawny) and (stripes = black) (animal = tiger).

4 RULE 11 IF THEN RULE 12 IF THEN RULE 13 IF THEN RULE 14 IF THEN RULE 15 IF THEN j 314+ (type - ungulate) and (neck = long) and (legs = long) and (spots - dark) (animal = giraffe).

(type = ungulate) and (stripes = black) (animal = zebra).

(class = bird) and (movement <> fly) and (neck long) and (legs long) and (color black_and_white) (animal = ostrich).

(class = bird) and (movement <> fly) and (swims = yes) and (color = black and_white) (animal ="penguin).

(class = bird) and (movement = flies-well) (animal = albatross).

i i 1 35-

Claims (33)

1. A hardware-implemented rule-based expert system apparatus suitable for performing high speed inferencing in AI applications based upon a rule set for an application domain, comprising (a) working memory means; (b) input means for receiving external data pertaining to the application domain and for storing the external data in said working memory means as facts; (c) rule memory means; (d) means for storing in said rule memory means a rul set for the application domain comprised of a series of instructions, each defining a condition or an action; (e) means for loading from said rule memory means into said working memory means successive instructions of said rule set; and (f) logic means for successively executing the instructions in said working memory means with reference to the stored facts in said working memory means to thereby deduce new facts.

2. An apparatus according to Claim 1 wherein said logic means includes means for storing the deduced new facts in said working memory means, and additionally including output means for transferring the deduced new facts stored in said working memory means to an output device.

e 1... - L

3. An apparatus according to Claim 2 wherein said output means comprises an input-output interface and an interface bus communicatively interconnecting said input-output interface to said working memory means.

I.

4. An apparatus according to Claim 1 or 2 wherein said working memory means comprises a semiconductor random access nemory device, and said rule memory means comprisds a separate semiconductor random access memory device, and including a data bus and an address bus interconnecting said working memory means and said rule memory means for permitting the transfer of data therebetween.

5. A hardware-implemented rule-based expert system apparatus suitable for performing high speed inferencing in AI applications based upon a rule set for an application domain, comprising (a) working memory means; (b) input-output interface means for communicatively connecting said working memory means with an external system; said input-outbut means including means operable at the initialization of the inferencing operation for receiving and storing in the working memory means values representing known facts pertaining to the application domain; (c) rule memory means (d) means for storing in said rule memory means a rule 'set for the application domain comprised of a series of instructions, each defining a condition or an action; (e) means operable during the inferencing operation for successively fetching from said rule memory means 1 . d ' S' -1 storing in said working memory means instructions of said rule set; (f) logic means operable during the inferencing operation for successively receiving the respective instructions stored in said working memory means and for executing the instructions with reference to the stored facts in said working, memory means to thereby deduce new facts, said logic means also including means for storing deduced new facts in said working memory means for use during the execution of subsequent instructions; and (g) wherein said i:nput-output means includes means operable upon completion of the inferencing operation for transferring the.facts stored in said working memory means to an output device.

6. An apparatus according to Claim 5 wherein said means for successively fetching instructions of said rule set includes rule memory counter means including an address register for storing the address of the current instruction in said rule 5 memory means; and n(ans for updating said address register with the address of the next instruction each time an instruction is fetched from said rule memory means.

7. An apparatus according to Claim 5 or 6 vierein each of the instructions of said rule set includes an operator, a condition/action flag, and a pair of operands; and wherein said logic means includes an instruction decoder for testing said condition/action flag to determine whether the instruction is a condition or an action; means operable if the instruction is a condition for comparing the operands in accordance with the ; 1, .. 1 -1 37 gical operation specified by the operator to generate a logic result; and means operable if the instruction is an action for performing the action specified by the operator on the operands.

A

8. An apparatus according to Claim 7 wherein said logic means includes means operable if the logic result of said comparing step is TRUE for effecting fetching of the next instruction of the same rule.

9. An apparatus according to Claim 7 or 8 wherein said logic means includes means operable if the logic result of said comparing step is FALSE for effecting fetching the first instruction of the next rule.

10. said instructions also includes a direct/immediate flag for specifying the addressing mode of one of the operands.

11. A hardware-implemented rule-based expert system apparatus suitable. gor performing high speed inferencing in AI applications based upon a rule et for an application domain, comprising an integrated circuit on which there is provided:

(a) working memory means; (b) system interface bus means for communicatively connecting said working memory means with an external system for receiving and storing in the working memory means values representing known facts pertaining to the application domain; I 3 (c) rule memory bus means for communicating.with an external rule memory in which is stored a rule set for the application domain comprised of a series of instructions, each defining a condition or an action; (d) rule memory counter means including an address register for storing the address of the current instruction in said external memory means, (e) means for fetching the current instruction from the rule memory via said rule memory bus means; and (f) logic means for receiving the current instruction and for executing the instruction with reference to the stored facts in said working memory means to thereby deduce new facts.

12. An apparatus according to claim 11 wherein said logic means also includes means for storing deduced new facts in said working memory means.

13. A hardware-implemented rule-based expert system apparatus comprisin.g (a) working mem6ry means; (b) means for receiving external data representing known facts and for storing values representing said facts in predetermined memory addresses of said working memory means; (c) a memory device for storing a rule set; (d) a rule set comprised of a series of rules stored in said memory device, each rule of said rule set comprising a series of instructions stored in successive memory addresses of said memory device; AO (e) at least one of said instructions of each rule representing a condition to be satisfied by the facts of a given problem and including (i) an operation codedefining a logical operation to be performed; (ii) a first operand defining a first value to bg compared by said logical operation; and - (iii) a second operand defining the address in said working memory containing a second value to be compared by said logical operation.

14. An apparatus according to Claim 13 wherein Gf) at least one of said instructions of each rule represents an action to be performed if all of the conditions of the rule are satisfied, and including (i) an operation code defining the action to be performed; and (ii) a first operand defining a value for a fact, and._(iii) a second operand defining an address 10 in said working me mory means whire the value defined in the first operand is to be stored.

15. An application rule set for a hardware-implemented rule-based expert system which includes a memory having a plurality" of memory addresses, said rule set comprising a series of rules stored in said memory; each rule of said rule set comprising a series of instructions stored in successive memory addresses of said memory; 1 I-:

/4 1 at least one of said instructions of each rule representing a condition to be satisfied by the facts of a given problem; and at least one of said instructions of each rule representing an action to be executed if said condition is satisfied.

16. A rule set according to Claim 15 wherein said instructions are all of the same number of bits in length.

17. A rule set according to Claim 15 or 16 wherein certain of the bits of each instruction define an operand and other bits of the instruction define an operation code.

18. A rule set according to Claim. 15-, 16 or 17 wherein at least one bit of the instruction comprises a flag indicating whether the instruction is a condition or an action.

1

19. A rule set according to Claim 16 wherein said instructions are 32, bits in length and include bits defining an operation code, bits defining afirst operand, bits defining a second operand, and at least one bit defining a flag indicating 5 whether the instruction is a condition or an action.

20. A rule set according to Claim 16, 17, 18 or 19 wherein said instructions each include at least one bit indicating the addre.ssing mode of one of said operands.

1 A P.

21. A rule set according to any one of Claims 15 to 20 wherein the rules of said rule set are stored as a series of instructions in successive memory addresses beginning at one end of said memory, and including a rule index stored in successive memory addresses beginning at the opposite end of said memory, the rule index comprising a series of memory addresses defining the beginning memory address of each rule of said rule set.

22. An application rule set for a hardware-implemented rule-based expert system which includes a memory having a plurality of memory addresses; said rule set comprising a series of rules, each comprised of a series of instructionsof a predetermined number of bits in length stored in successive memory addresses of said memory, certain of the instructions of each rule representing a condition to be satisfied by the facts of a given problem, other instructions of each rule representing an action to be executed when that rule is fired, and rule index also stored in said memory and comprising a series of memory addresses in the memory corresponding to the beginning memory address of each rule of said rule set.

23. An apparatus according to Claim 22 wherein the rules of said rule set are stored in successive memory addresses beginning at one end of said memory, and said rule index is stored in successive memory addresses beginning at the opposite end of said memory.

l i 1 t A 5

24. An apparatus according to Claim 22 or 23 wherein each of the instructions of said rule set includes an operator, a condition/action flag, and a pair of operands.

25. An application rule set for a hardware-implemented rule-based expert system which includes a memory having a plurality of memory addresses; said rule set comprising a series of rules, each comprised of a series of instructions of a predetermined number of bits in length, the instructions of each rule being stored in successive memory addresses of said memory, the rules of the rule set being stored consecutively beginning at one end of said memory; said instructions including bits defining an operation code, bits defining a first operand, bits defining a second operand, at least one bit defining a flag indicating whether the instruction is a condition or an action, and at least one bit indicating the addressing mode of one of said operands, and a rule index also stored in said memory and comprising a series..of memory addresses in the memory corresponding to the beginning memory address of each rule of said rule set, said rule index being stored in successive memory addresses beginning at the opposite end of said memory from where the rule set begins.

26. A hardware-implemented rule-based expert system method for performing high speed inferencing in AI applications based upon a rule set for an application domain, comprising (a) storing in a working memory known facts pertaining to the application domain; 9. 1 k,.1 Af ti (b) storing in a rule memory a rule set for the.. application domain comprised of a series of instructions, each defining a condition or an action; (c) loading from said rule memory into said working 4 memory an instruction of said rule set; and (d) executing the instruction in said working memory with reference to the stored facts in said working memory.

27. A method according to Claim 26 comprising repeating steps (c) and (d) for successive instructions of said rule set to deduce a new fact, and storing the deduced new fact in working memory.

28. A method according to Claim 27 wherein said step of storing a rule set in a rule memory comprises storing the instructions of said rule set in successive memory addresses of said rule memory, and including the step of updating a mempry address register with the address of the next instruction each time an instruction is loaded from said rule memory.

29. A method accordiAg to Claim 26 wherein said step of storing a rule set in a rule memory comprises storing in successive memory addresses of said rule memory instructions containing an operator, a condition/action flag, and a pair of operands, and wherein said step of executing the instruction includes examining the condition/action flag to determine of the instruction is a condition or an action.

1 1 J A-

30. A method according to Claim 29 including the step, executed if the instruction is a condition, of comparing the operands in accordance with the logical operation specified by the operator to generate a logic result.

A

31. A method according to Claim 29 or 30 including the step executed if the instruction is an action, of performing the action specified by the operator on the operands.

32. A hardware-implemented rule-based expert system method for performing high speed inferencing in AI applications based upon a rule set for an application domain, comprising (a) dTefining a set of characteristics pertaining to 5 the application domain; (b) assigning each characteristic of the set to specific memory addresses in a working memory; (c) selecting from said set for a particular problem which is to be solved by the expert system, those characteristics having values which are known; (d) storing the values for the known characteristics in working memory at the appropriate memory addresses assigned for those characteristics; (e) storing in a rule memory a rule set for the application domain, said rule set comprising a series of instructions; (c) loading from said rule memory into said working memory successive instructions of said rule set and executing the instructions with reference to the stored characteristic values in said working memory to thereby deduce a value for an unknown characteristic; and 1 A& (d) storing the deduced value in working inemory.at the corresponding memory address for that characteristic.

33. A hardware-implemented rule-based expert system apparatus constructed and arra nged to operate substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

Published 1989 atThe Patent Office.State House, 66171 High Holbom, London WCIR 4TP. Further copies maybe obtained from The PatentOffice. Sales Branch, St Mary Cray, Orpington, Kent BR5 ULD. Printed by Multiplex techniques 1W, St Mary Cray, Kent, Con- 1187 o