NL194520C - Expert system based on regulations. - Google Patents

Description

1 194520

Expert system based on regulations

This invention relates to a rule-based expert system, and more particularly to a circuit-based, rule-based expert system suitable for performing deductions in artificial intelligence applications at high speed.

From the article "VOSS-VHSIC Hosted Expert System" by M. Plutowski, published in "Proceedings of the IEEE 1986 National Aerospace and Electronics Conference NAECON 1986, part 4, May 19, 1986 Dayton, OH USA, is such, by prescriptions based expert system known The expert system described comprises an integrated hardware software design that allows calculation-intensive and memory-intensive applications of an expert system to be implemented in this system.

Expert systems include a class of computer programs with artificial intelligence technology to address problems that would normally require human experts or specialists. In a rules-based expert system, the knowledge of an expert in a specific field of application is represented in the form of a set of rules "production rules". When working with a typical expert system, the user, through a suitable user interface, feeds the expert system with certain known information about a specific problem, and the expert system applies the production rules to this known information, for deducing facts and solving problems which are relevant to the scope.

European patent application EP 0166 251 discloses such an expert system which comprises a deduction system and associated method in which knowledge technologies such as "production rules" or "production frameworks" are applied.

In the "Rule-Based Systems" article by Hayes-Roth, published in "Communications of the Association for Computing Machinery," Part 28, Number 9, September 1985, New York, USA, pages 921-932, a general overview of regulatory based expert systems and their applications.

Furthermore, this article extensively examines the characteristic features of such expert-based expert systems.

For further background information regarding expert systems, reference is made to the following articles: Robert H. Michaelsen, et al., "The Technology of Expert Systems", Byte Magazine, April 1985, pages 30 308-312; Bevely A. Thompson, et. al., "Inside an Expert System," Byte Magazine, April 1985, pp. 315-330; Michael F. Deering, "Architectures for ΑΓ, Byte Magazine, April 1985, pp. 193-206.

Successful expert systems have been developed for a number of application areas: for making medical diagnoses, for identifying organic mixtures, for selecting drilling oil suspensions, etc. In addition, a number of application independent expert systems have been developed in software form, for supporting the building of regulatory based expert systems for specific application areas. In the aforementioned articles by Michaelsen, et al. Thompson, et al., And Deering, a number of commercially available expert system tools are described. These expert systems and expert system tools are typically designed in the form of computer programs to run on a general purpose computer or a microcomputer. The computer program provides an interactive session between the user and the expert system in which the expert system asks questions to the user, and uses expert knowledge database to solve problems and provide advice to the user.

There is considerable interest in extending the application of expert systems to other practical applications and in particular in developing expert systems which are suitable for use in real-time applications. These systems could, for example, be useful as a control system for various applications, such as manufacturing processes, process control, guidance systems, robotics, etc. However, a serious limitation in the development of complicated, real-time artificial intelligence systems ("artificial intelligence (Al) systems") the calculation speed.To make effective practical use of artificial intelligence technology, the efficiency 50 and calculation speed must be increased.

Significant efforts have been made to improve the speed of Al processing by improving and streamlining software tools used in Al processing, such as the Al languages. It has also been recognized that quality improvements can be achieved through bespoke circuits, especially designed for artificial intelligence processing. As indicated in the above-mentioned Deering article, an approach to circuit engineering architectural enhancements included refinements in the processor instruction set to enable faster operation of the processor. Attention was also paid to the development of parallel processing architectures, 194520 2, with which it could be possible to perform the Al calculations in parallel. The article also notes that customized VLSI circuits could be used to speed up specific operations such as comparisons, retrieval of instructions, parallel processor communication and signal-to-symbol processing.

An important object of the present invention is to improve the speed and efficiency of prescription-based expert systems by providing a circuit-technically implemented deduction machine. More specifically, the present invention provides a dedicated integrated circuit that has been specially designed for performing high-speed deductions for a regulation-based expert system.

The present invention relates to a hardware-implemented rule-based expert system device for performing high-speed deductions based on a prescription set for an application area, comprising: allocated working memory means for storing therein relating to the application area; 15 dedicated prescription memory means for storing therein the prescription set for the scope, comprising a series of instructions each defining a condition or an action; logical means; a first communication bus communicatively connecting the working memory means to the logic means; 20 a second communication bus which is communicatively connected to the prescription memory means; which logical means comprises allocated means for successively executing the instructions in the prescription memory means obtained via the second communication bus, with reference to the stored facts in the working memory means as obtained via the first communication bus, thereby thereby deducing new facts, and wherein at least one of said instructions represents for each rule a condition to be met by the facts of a given problem and comprising: (i) an operation code defining a logical operation to be performed; (ii) a first operand defining a first value to be compared by the logical operation; and (iü) a second operand that defines the address in the working memory that contains a second value to be compared by the logical operation.

Furthermore, the present invention relates to a hardware-implemented or prescription-based expert system device that is capable of performing high speed deductions based on a prescription set for an application area, comprising: allocated working memory means for storing therein facts relating to the application area ; allocated prescription memory means for storing therein the prescription set for the scope, comprising a set of instructions that each define a condition or an action; logical means; a first communication bus communicatively connecting the working memory means to the logical means; a second communication bus that is communicatively connected to the prescription memory means; which logical means comprises allocated means for successively executing the instructions in the prescription memory means obtained via the second communication bus, with reference to the stored facts in the working memory means as obtained via the first communication bus, thereby thereby deducing new facts, and wherein at least one of the instructions of each rule represents an action to be performed if all conditions of the rule are met and comprising: (i) an operation code defining the action to be performed; and (ii) a first operand defining a value for a fact; and 50 (iii) a second operand defining an address in the working memory means, in which the value defined in the first operand is to be stored.

The arrangement and method for a circuit-implemented, rule-based expert system according to the present invention is hereinafter referred to as the acronym REX ("Ruleba-sed EXpert"), and comprises a working memory in which, at the start of a deduction operation for 55 information or facts are stored in the field of application .The device further comprises a prescription memory for storing a prescription set for the field of application. The prescription set consists of a series of instructions which each determine a condition or an action. loading the prescription memory into the working memory of successive instructions from the prescription set and logical means are provided for successively executing the instructions in the working memory with respect to the facts stored in the working memory, thus deducing new facts.

During the deduction process, when new facts are deducted, they are stored in the working memory, which can be used during the execution of successive instructions from the prescription set to derive further facts. After completion of the deduction process, the facts stored in the working memory are transferred to an output device.

Each of the prescription set instructions includes an operator, a condition / action flag, and a pair of operands. The logic means includes an instruction decoder for testing the condition / action flag of each instruction to determine whether the instruction is a condition or an action. When the instruction is a condition, the operands are compared in accordance with the logical operation specified by the operator to generate a logical result (e.g. true or false). When the instruction is an action, the action specified by the operator is performed on the operands.

The working memory and the logical means may suitably be provided as an integrated circuit. The prescription memory can either be connected externally of the integrated circuit to the working memory via a suitable external memory bus, or the prescription memory can also be included in the integrated circuit with suitable data bus connections to the working memory. Because the application prescription set is stored in a memory device, the REX deduction machine is region-independent, so that it can be used for different applications by simply including another application prescription set in the prescription memory. The structure of the prescription memory and the data structure of the application prescription set are designed to greatly increase the efficiency of the deduction process. To illustrate the versatility and broad general applicability of the present invention, the following detailed description shows how the REX deduction machine can be used as a coprocessor in conjunction with an existing computer or microcomputer to provide an expert system that is suitable is for performing deductions at speeds that are significantly greater than could be performed by conventional software-implemented deduction machines. However, the REX deduction machine can also be used for many other applications, such as an independently operating system, if provided with a suitable internal control system, a user interface and input / output devices.

The REX deduction machine is suitable for carrying out real-time knowledge processing, based on current VLSI technology. The speed at which problems are solved is measured in logical deductions per second ("logical inferences per second") (LIPS) instead of floating point operations per second ("floating point operations per second") (FLOPS). A LIPS equals about 100 to 1000 FLOPS on a conventional computer.

Brief Description of the Drawings 40 Some of the features and advantages of the invention have already been mentioned, others will become apparent from the following detailed description, in conjunction with the drawings, in which: Figure 1 is a perspective view illustrating how the REX deduction machine as a co-processor can be used in a conventional personal computer; Figure 2 is a more detailed view of a co-processor card that uses the REX-45 deduction machine; Figure 3 is a block diagram showing the data flow for the REX machine; Figure 4 is a block diagram illustrating the structure of the regulations database for the REX machine; Fig. 5 is a diagram showing the data structure of the instructions stored in the rule memory; Fig. 6 is a diagram illustrating the operation code format used in the REX chip; Figure 7 is a total block diagram of the main functional components of the REX chip; Fig. 8 is a diagram illustrating the data bus bit allocation for I / O read / write operations; Fig. 9 is a flow chart showing the deduction current of the REX chip; and Figs. 10 to 12 are time diagrams for the REX chip showing the read mode, write mode and external memory timing respectively.

194520 4

Detailed description

Figure 1 illustrates an expert system designed for collaboration with a microcomputer 10, such as an IBM AT Personal Computer with an attached expert system (REX) co-processor card 11. The REX card 11 is made up of a REX chip 12, an external prescription memory 13 and an I / O interface 14. The REX card is shown in more detail in Figure 2. An application prescription set for a specific application area, designated 15 in Figure 2, is stored in the external prescription memory 13. The REX chip 12 is therefore region-independent and can be used for a large number of different application areas.

Referring to Figure 2, each component of the REX processor card 11 is explained as follows: 10 I / O interface: The I / O interface 14 is responsible for the communication between the personal computer 10 and the REX processor. processor card 11. External data is transferred from the personal computer 10 via the I / O interface 14 to the REX card 11. In the embodiment illustrated herein, a DMA channel provides a communication link between the REX card 11 and the personal computer 10. A computer program running on the personal computer is used to provide an easily understandable user interface.

REX chip: The REX chip 12 is a circuit-based deduction machine and forms the heart of the REX processor card 11. Two main components of the REX chip are the main memory and the control logic. Before the deduction process begins, the main memory is initialized with external data from the I / O interface. External data which are relevant for facts known from the application area are stored in special memory locations of the working memory. During the deduction process, the working memory forms a temporary storage for intermediate data. When the deduction process is completed, the working memory contains the results of the deduction process, which are then transferred to the personal computer via the I / O interface.

Prescription memory: The knowledge engineer extracts a production prescription set, called an application prescription set 15, from the application area and this prescription set is stored in the prescription memory 13. During the deduction process, the REX chip 12 refers to the prescription memory 13 for prescription information. The structure of the prescription memory is suitably designed to meet the requirements of the REX chip and to reduce memory space.

The data structure of the application prescription set stored in the prescription memory is designed to greatly increase the efficiency of the deduction process. Further details about the structure of the prescription memory and the application prescription set stored therein are provided below.

The prescription memory can be a ROM, RAM, EPROM or other suitable memory device. When a prescription memory RAM is applied, an initialization program is used to pre-accommodate the application prescription set 15 in the external memory 13.

Although the specific embodiment illustrated herein demonstrates how the REX chip 12 can be used as a co-processor for a personal computer, those skilled in the art will recognize that the circuit-implemented, rule-based expert system (REX) can be used for many other specific applications. . For example, it can be used as an independently operating system. In such a case, a control system is provided for handling the user interface and the I / O interface and additional I / O devices such as a keyboard, a graphical display, etc. are provided to communicate between the REX card and to enable the user.

Deduction mechanism 45 There are different types of deduction methods that can be used to solve a problem in a prescription-based expert system. Some of the most important deduction methods are forward chain formation, backward chain formation and combination chain formation. The deduction machine particularly illustrated and described herein utilizes the forward chain-forming deduction method with production rules.

50 The rules of the rule-based system are represented by production rules. The production rules consist of an if ("if") part and an if ("then") part.

The iFdeel is a list of one or more conditions or antecedents. The then part is a list of actions or consequences. A production rule can therefore be represented as follows: if condition_1, 55 condition_2, condition_n 5 194520 then action_1, action_2, action_n 5 When the conditions (condition_1, condition_2, .. conditions) are fulfilled by the facts of a given problem, we can say that the prescription has been drawn ("triggered"). The expert system can then perform the given actions. Once the actions have been performed, the prescriptions are fired ("fired"). These special actions may change other conditions, which in turn may change The flow of fired rules will continue until the problems are solved, or until no other rules can be fulfilled.This method of firing rules moves forward through the rules, so this is called forward Forward chain formation is also called a deduction system or fact driven, omda t the facts guide the flow of the fired regulations.

Drawing the rules does not mean that the rules are fired, because the conditions of several other rules can be met simultaneously, and all are drawn. When this occurs it is necessary to apply a conflict resolution strategy to decide which rule has actually been fired. A conflict resolution strategy is a process of selecting the most favorable rule when more than one rule is met. Examples of conflict resolution strategies are the following: 1. The rule that contains the most recent data is selected. This strategy is called "Data Recency Ordering" in the English language.

2. The rule that has the most complicated of the most difficult conditions is selected. In the English language this is also called "Context Limiting Strategy".

3. The rule that is first in the list is selected. This is called 25 "Rule Ordering" in the English language.

EXAMPLE 1

Example of forward chaining

This example provides a general illustration of the operation of a rules-based expert system. For the purpose of this illustration, reference is made to the animal identification rule set in Appendix A. This prescription set tries, by giving its physical properties, to identify an animal. Suppose that the following properties have been observed: the animal has hair, the animal eats meat, the animal has a tan, the animal has black stripes.

These observations are translated into the following facts: coverage = hair, food = meat, 40 color = tan, stripes = black.

Given these facts, REGULATION 1 is drawn. According to this regulation we deduce that class mammal.

That the animal is a mammal is now accepted by the system as a new fact. Consequently, 45 REGULATION 2 to REGULATION 4 cannot be drawn. The condition of REGULATION 5 is valid so that the system will deduce that the animal is a meat eater. meat eater = yes.

The system has so far deduced two useful new facts. The first three conditions of REGULATION 9 are true, but the last condition is not, so that REGULATION 9 fails. REGULATION 50 10 is drawn and can be fired. The system therefore deduces that the animal is a tiger. animal = tiger.

The deduction does not stop here, because there are several prescriptions. In this case, none of the other requirements can be met. The system identifies the animal as a tiger.

The example shows a deduction method in the forward direction, from the current situation of facts or 55 observations to a conclusion.

194520 6 REX deduction machine architecture

The main components of the REX deduction machine are shown in more detail in Figure 3. The REX chip itself has three primary functional components: the main memory 16, an arithmetic and logic unit (ALU) 17 and control logic 18. In the embodiment shown herein, the control memory 13 is a separate memory device which is connected via a data bus 21 to the working memory 16 is connected. On the other hand, it will be clear to a person skilled in the art that the prescription memory could, if desired, be integrated into the REX chip itself. The I / O interface 14 is communicatively connected to the working memory via a system interface bus, which is designated in its entirety by 22. The control logic is schematically shown in Figure 3 and designated with the reference numeral 18

10. In general, the control logic 18 has the task of operating the other elements, such as the ALU

17 and the working memory 16.

Data stream in the REX deduction machine

The data stream of the REX machine will best become clear from Figure 3 and the following description. The circled figures in Figure 3 correspond to the following subjects: 1. Input data

The user applies the facts to the system via a user interface program on the personal computer 10. The user presents the facts in a predetermined syntax. When applying the fact data of example I and the prescription set of Appendix A, the user would, for example, enter the following: coverage = hair color = tan .. etc.

The user interface program converts any actual observation into values represented by a pair of binary numbers.

The first part of the pair is an address and the second part of the pair is a value.

address value 30

In the example above we have: (address o32) coverage = (value% 10) ohaar, (address e58) color = (value% 55) tan, 35 .. etc.

wherein α and "%" indicate that the digit being referred to is respectively an address or a value. In the above case, coverage is displayed at address 32 (no other word is displayed at address 32). A unique address number is therefore assigned to each word. The hair value is stored at address 32. These numbers are used in step 2.

40 2. Storing facts in the main memory

In step 2 the facts are stored in the working memory.

3. Placing rules in the working memory

The external memory is used for storing regulations relevant to the application area. Each prescription is represented as follows: 45 IF condition 1 and condition 2 and THEN action 1 action 2 50

A condition element is: (class = mammal)

Similarly, an action element is: (type = required) 55 Each element, both a condition part and an action part of the prescription, is intemally represented as an instruction in the format shown below: 7 194520

Operand I Operand 2 I Operator I Dir / lmme I Act / Cond

Each instruction has a predetermined length, for example 32 bits. Operandl represents an address 5 of the main memory. Depending on the value of the Dir / lmme field, Operand2 is either an address or a value in the working memory. The Dir / lmme field specifies whether the addressing mode is Operand2 Direct or Immediate. The Act / Cond field specifies whether the element refers to the condition or action part of a prescription. The Operator field specifies the type of operator used in the condition part of the prescription. Examples of operators are: equals (=), greater than (>), less than (<), etc.

4-5. Deduction cycle

The following steps are performed during the deduction cycle.

4.1. Reaching the external memory element

A prescription is retrieved from the prescription memory 13, wherein the Cond / Act field of the first 75 instruction is examined to determine if it is a condition or an action. If the statement is a condition element, the statement in section 4.1.1. procedure described. If it is an action, the information in section 4.1.2. procedure described.

4.1.1. Adapting the prescription condition element to the working memory

The address in Operandl is loaded in the ALU (step 4). Next, the Dir / lmme field under-20 is searched to see if Operand2 is Direct or Immediate. When this Immediate is, the value of Operand2 is directly supplied to the ALU, otherwise the content of the address designated by Operand2 is supplied to the ALU. The ALU compares the ALU input using the operator (Operator field) to determine if the condition is true or false. If the condition is true, the next successive instruction of the prescription is examined by repeating the 2s in section 4.1. specified sequence of steps. If the condition element is false, this rule is discarded and the next rule is examined by repeating the sequence of steps in section 4.1.

4.1.2. Action part

The Dir / lmme flag of the action element is checked first. When this is Direct, the value stored in the Operand2 location of the main memory is copied to the address of the main memory represented by Operand1. When the Dir / lmme flag is Immediate, Operand2 is copied to the address of the main memory represented by Operandl. After performing the action specified by the instruction, the following successive action instruction is read from the rule and the one described in section 4.1.2. procedure described. When the action instruction 35 is the last instruction of the prescription, repeating the sequence of steps in section 4.1. examined the following requirement.

6. Facts to data

When all regulations have been processed, the control is transferred to the I / O interface 14. The numerical representation of the facts is converted into a form that can be easily understood by the user.

7. Data output

The I / O interface will then output the data to the personal computer 10.

EXAMPLE II

45 Example of the REX data stream

This example illustrates the manner in which the REX chip solves the problem described above in Example I. The numbered subjects again correspond to the circled figures in Figure 3. See Appendix A for the complete animal identification rule set.

1. Input of external data 50 The data or observations made are: the animal has hair, the animal eats meat, the animal has a tan color, the animal has black stripes.

55 The above information enters the L / O interface and is translated into facts. The data is translated into the following facts: (address o32) coverage = (value% 10) hair, 194520 8 (address 041) food = (value% 3) meat, (address 058) color = (value% 55) tan, (address 035) stripes = (value% 8) black.

5 2. Facts stored in the working memory

The address represents the location in the main memory. For example, address location 32 houses the value 10.

3. Loading an instruction

An instruction is loaded from the prescription memory. The first instruction of REGULATION 1 is 10 a condition, and takes the form of: (address 032) coverage IS EQUAL ("EQUAL") (value% 10) hair 4. Loading operands a. Condition

The value of address location 32 is loaded into the ALU, in this case 10. The comparison process of the 15 ALU is: (value% 10) her EQUAL (value% 10) her This result is true.

If the instruction is: (address 032) cover EQUAL (value% 11) springs, the output of the ALU would be false. The control goes back to STEP 3.

b. Action

If the instruction is an action such as: (address 077) class MOV (value% 20) mammal, the ALU would get the value 20 and store it at address location 77.

25 5. Storing facts in the working memory

The value 20 is deduced from REGULATION 1 and must be stored at address location 77. The control goes back to STEP 3.

6. Facts to data

In this example, the value on the (address 88) class is transferred to the I / O interface. It follows from the 30 facts that the value at address location 88 (value% 100) is tiger.

7. Export of data

The value 100 is translated into tiger through the interface.

Structure of the regulation data base 35 The application regulation set 15, which is stored in the working memory 16, is divided into two parts -STRUCT and REQUIREMENTS. In each regulation, a set of conditions is grouped at adjacent addresses. A set of actions is also grouped at adjacent addresses in each prescription. These groups can be stored in the REGULATIONS section of the main memory in the following manner: 40 Prescription% 1 address xxx1 condition_1_1 address xxx2 condition_1_2 45 address xxxm condition_1_m address yyy1 action_1_1 address yyy2 action_1_2 50 Prescription% 2 address zzz1 condition_2_1

Because the conditions and actions are successively stored at different memory addresses, the representation of the rules can be structured using the start address of each rule. The production regulation can therefore be expressed as: 9 194520, if xxx 1 then yyy1 if zzz1 5 then

This format shows that when a group of conditions at a given address is TRUE, the group of actions must be executed at the address specified in the then part. If the first rule is then false, the steering mechanism jumps to the start address of the next rule. There is no need for end indicators for each requirement, so that the REX does not waste time searching for end indicators.

The structure of the REX regulatory data bank is shown in Figure 4. In this version, for storing the application prescription set, an external memory of 64K X 32 ROM is used.

In order to maximize the use of the limited memory, STRUCT and REGULATIONS are stored at both ends of the prescription memory 13, respectively. STRUCT starts from the address OOOOH and higher. REGULATIONS start from the FFFFH address and below.

Figure 5 shows the detailed structure of the prescription memory. STRUCT houses the address index that points to the start address of each rule in RULES. The size of the prescription memory is 64K, so that only the 16-bit lower half word is used.

Each condition or action is represented as an instruction of a 32-bit word processed by the REX. The condition is basically a logical comparison of two given operands. The actions are organized in a similar way. The operators of the actions are basically logical operators and an allocation operator. There are two operands for each process: operandl and operand2. Operand2 can take two • forms: direct or immediate. As shown in Figure 4, the direct operand is a pointer ("pointer") to an address in the main memory represented by the "o" symbol and the immediate operand is an integer represented by "%".

Instruction set for the REX deduction machine 30 As shown in Figure 5 (b), instructions from the REX are always 32 bits long. The Operation Code (6 bits), OP1 (13 bits) and OP2 (13 bits) are merged into a 32-bit instruction. Every prescription in a given application prescription set has condition and action parts. The REX therefore has two types of instruction set: - Condition instructions: This instruction type is used to determine whether the condition is True or False. This makes it possible for users to define different logical relationships between two operands, such as "Equal", "Greater than" ("Greater than"), etc. The editing result of a Condition instruction can only be True or False, which affects the next processing sequence.

- Action instructions: This type of instruction is only executed when all conditions of the current rule are True. The result of performing the action is always stored in the first operand.

40 The instructions and the associated operation codes are summarized in Table A.

TABLE A

REX OPERATION CODES

40 Operation codes Operation Description OXOOOO EQ Same as ("EQual to");

Is operandl = operand2? OXOOOI NE Not Equal to ("Not Equal to"); S0 Is operandl <> operand2? OXOOIO GT Greater than ("Greater Than");

Is operandl> operand2? OXOOII LT Less than ("Less Than");

Is operandl <operand2? 00 OXOIOO GE Greater than or Equal to ("Greater than or Equal to");

Is operandl> = operand2? 194520 10

TABLE A

REX OPERATION CODES (continued)

Operation codes Operation Description 5 _____ ____ - OXOIOI LE Less than or Equal to "Less than or Equal to";

Is operandl <= operand2? IXOOOO NOT logical denial operandl ("logic NOT operandl");

Each bit of operandl is complemented and the result is stored on operandl in the working memory.

IXOOOI AND logical AND ("AND") operandl and operand2;

The logical AND operation is performed on the corresponding bits of operand1 and operand2. The result is stored in the main memory on perandl.

IXOOIO OR OR ("OR") operandl and operand2;

The logical OR operation is performed on the corresponding bits of operand1 and operand2. The result is stored in the working memory on operandl.

IXOOII MOV Move ("MOVe") operand2 to operandl;

The contents of operand2 are stored in the working memory on operandl.

25 IXOIOO SHR Slide ("SHift") operandl over 1 bit to the Right ("Right ·");

The least significant bit is removed and a zero is shifted at the location of the most significant bit; the result is stored in the working memory on operandl.

IXOIOI SHL Move ("SHift") operandl over 1 bit to the Left ("" Left ");

The most significant bit is removed and a zero is shifted at the location of the least significant bit; the result is stored in the working memory on operandl.

XXOIIO JMP Jump ("JuMP") to a new address of the external memory;

For the JMP statement, the least significant 40 bits of the statement are loaded into the C1 register pointing to the new rule in the external memory.

XXOIII EOR End of the external memory ("End of External

Memory ").

45 _ - operandl is a directly addressed data (WM [OP1j) from the main memory.

- operand2 can be a direct-addressed data (WM [OP2j) or an immediate data (OP2).

50

The format of the opcode is shown in Figure 6. The MSB (Most Significant Bit), that is F1, of the opcode is used to specify the instruction type. When F1 is 0, it is a Condition statement, otherwise it is an Action statement. A Condition instruction always has two operands. An Action statement, on the other hand, can only have one or two operands, depending on the required operation.

The REX allows two types of addressing: immediate and direct addressing. The first operand always uses direct addressing. The second operand can be an immediate given or an immediately addressed given. The addressing method is determined by examining the second MSB, that is F2, of the operation code. When F2 is O, the second operand is an immediate given. Otherwise, the second operand is a direct address.

Functional description of the REX chip

Figure 7 provides a detailed block diagram of the REX chip 12. To avoid repeated description, elements described in the foregoing in conjunction with previous figures are designated with the same reference numerals.

Table B gives the name, I / O type and function of each input and output illustrated in Figure 7.

TABLE B

PEN DESCRIPTION OF THE REX ... Symbol Type Name and function 70 CLK I Clock Input: CLK controls the internal processing of the REX chip.

The maximum clock frequency is 6 MHz.

CS I Chip Selection ("Chip Select"): CS is an active-low input which is used 2Q to select the REX chip as an I / O device when the CPU handles the internal registers (WM, WMC, C / S) wants to read / write from the REX chip.

EMCS O External Memory Chip Selection ("External Memory Chip Select"): EMCS is low active. When REX is in the deduction mode, EMCS is selected for selecting the external memory for information about the prescription.

TOR I / O Read ("I / O Read"): TÖR is low active. When both CS and 1ÜR are active, the CPU has read access to the internal registers (WM, WMC, C / S) of the REX chip.

1CW I / O Write ("I / O Write"): 1ÖW is low active. When both CS and IÖW

"Q are active, the CPU has write access to the internal registers (WM, WMC, C / S) of the REX.

HLauV O Ready: HEADY is low active. HEADY is a synchronization signal for external data transfer. HEADY goes low when REX is ready for new data.

RESET I Reset ("Reset"): RESET is highly active. RESET is used to initialize the state of the REX chip. All registers are reset after RESET is activated.

INT O Interruption Request ("INTerrupt Request"): INT is highly active. The REX chip uses INT to interrupt the CPU when the REX chlp has finished the 4q deduction process.

AO-A1 I Address ("Address"): The CPU uses the two least significant address lines for controlling data transfer to the internal registers (WM, WMC, C / S) of the REX chip.

DO-D15 I / O Data Bus ("Data Bus"): The data bus lines are bidirectional 45 three-state signals that are connected to the system data bus.

The Data bus contains output signals when TÜR is active. The Data bus contains input signals when 1CW is active.

MAO-O External Memory Address Bus ("External Memory Address Bus"): When the MAI5 REX chip is in deduction mode, the external memory address bus is used to address a regulation in the external memory.

MDO-I External Memory Data Bus (External Memory Data Bus): When the MD31 REX chip is in deduction mode, the external memory data bus sends the information related to each rule to the REX chip.

55 - WM: Working memory ("Working Memory") - WMC: Working memory counter register ("Working Memory Counter register") - C / S: Send / Status flag registers ("Control / Status flag registers") 194520 12

The identification of each register and the operation of each is as follows: - WM (Working memory): The working memory 16 is used during the deduction process for storing the intermediate data. Before REX starts the deduction process, the main memory is loaded with facts entered by the user. The size of the working memory always limits the amount of input 5 from the user to the REX. In the illustrated embodiment, the working memory is a 4K X 8 static RAM.

- WMC (Working memory counter) register: WMC is a 13-bit adder with the possibility for parallel loading. WMC is used as the main memory address counter for data transfer during the I / O mode. When data transfer is in progress, WMC will be automatically increased. The contents of WMC can be set by the CPU prior to the start of data transfer.

- C1 register: C1 is a 16-bit adder with the possibility of parallel loading. During the deduction process, C1 points to one of the prescriptions addresses in the STRUCT section of the prescription memory 13. C1 increases by one before REX moves to the next prescription. For a JMP statement, C1 is loaded with a new value instead of incrementing it by one.

15 - C2 register: C2 is a 16-bit counter with the possibility of parallel loading. C2 points to the REGULATIONS section of the prescription memory. If no false condition occurs in a prescription, C2 is lowered by one before REX moves to the next condition or action. When an untrue condition is detected with respect to a prescription, C2 is loaded with the start address of the next prescription, rather than lowering it by one.

20 - OP register: The OP register comprises three parts: Operation code, OP1 and OP2, which include a REX instruction. Operational code is a 6-bit register that stores the operator of an instruction. Both OP1 and OP2 are 13-bit data registers which respectively store the address in the working memory of operand1 and operand2.

- OP 'register: The OP' register is a pre-fetch register ("prefetch register") that is used for storing the pre-fetch instruction ("prefetch instruction") for the OP register. REX will execute the pre-collection instruction unless a JMP instruction or a false condition occurs.

- SI (Start / lactive) ("Start / ldle") control flag: SI is used to identify the REX operation status: Deduction mode and l / O mode. SI is set by the CPU after the system has sent all the facts to the main memory. During the deduction mode, SI has the value 1. SI is reset by the REX each time the deduction process stops, after which the REX switches to the I / O mode.

- IE (Interrupt Release) ("Interrupt Enable") control flag: IE is set by the CPU at the same time as the Sl flag. REX assigns the interrupt release when the REX switches to the deduction mode. IE is applied with the IRQ flag for issuing an interrupt signal. The IE flag is reset by the CPU at the end of the interrupt service routine.

35 - IRQ (Interrupt Request) ("Interrupt ReQuest") status flag: When the deduction process stops, REX sets IRQ to indicate that the REX is requesting an interrupt from the CPU. To output an interrupt signal INT, IRQ is en-linked with the IE flag. IRQ is reset by the CPU after the interruption has been recognized.

When the REX is in the I / O mode, the CPU can read or write registers from the REX. The signals 40 and the affected registers are indicated in Table C.

TABLE C

DEFINITION OF REGISTER CODES

45 CS IOW IOR A1 AO Register Operation

Read status registers 0 10 0 0 ("Read Status Registers") 50 Write control registers 0 0 10 0 ("Write Control Registers")

Read working memory counter 0 1 0 0 1 ("Read Working Memory Counter") 55 ----—

Write working memory counter 0 0 10 1 13 194520

TABLE C

DEFINITION OF REGISTER CODES (continued)

Register operation CS IOW IOR A1 AO

5 _ ("Write Working Memory Counter")

Read working memory 0 10 10 ("Read Working Memory") 10 _

Write working memory 0 0 110 ("Write Working Memory")

REX chip is not selected 1 X X X X

15 ("REX Chip is Not Selected")

Editing modes REX has two editing modes: 20 - l / O mode - deduction mode.

The control flag SI is used as a fashion flag. REX switches to the other mode when the Sl-viag is changed.

Before REX enters the deduction mode, the REX must load all the facts entered by the user from the main system into the working memory of the REX. When the Sl flag is set, the REX switches from the I / O mode to the deduction mode. After the deduction process is finished, the results are transferred from the main memory to the main system.

During the I / O operation, the main system can read or write specific registers if the REX chip is selected. The control of read / write operations and the selection of registers are controlled by a set of control lines, which are indicated in table C. During the reading and writing of WMC and C / S registers, only a few bits of the system data bus are used. This is illustrated in Figure 8.

Once the main memory has been loaded with facts entered by the user, the REX will start the deduction process from the first prescription in the external memory. The deduction current of the REX is shown in Figure 9.

There are three different machine cycles for the REX in deduction mode.

- T1 cycle: T1 is a prescription retrieval cycle. The T1 cycle is only performed during the first start of the deduction process or when a JMP instruction occurs. In the T1 cycle, the start address of a regulation in the external memory is placed in the C1 register. C1 is in fact a 40 prescription counter, pointing to the starting address of the currently deduced prescription.

- T2 cycle: T2 is an instruction retrieval cycle. In the T2 cycle, the first condition instruction of each prescription is placed in the REX registers. The T2 cycle is performed when one of the conditions of a rule is false, the processing starting from the first instruction of the next rule. C2 can be understood as an instruction counter referring to a condition instruction or an action instruction 45 which is currently being implemented in the ALU.

- T3 cycle: The T3 cycle is an instruction processing cycle. There are several cases for the T3 cycle:

Condition instruction / Immediate data Condition instruction / Direct addressing 00 Action instruction / Immediate data Action instruction / Direct addressing JMP

STOP (end of the prescription)

The instruction prefetch cycle overlaps the T3 cycle. When a JMP instruction occurs 02, the operation sequence goes to the T1 cycle. If the result of a Condition statement is false, the operation sequence will go to the T2 cycle. If no JMP instruction and no false condition occurs, the REX will use the prefetch data to go to the T3 cycle.

194520 14 REX will always go through the same process until all regulations in the external memory have been reduced. When the deduction process stops, the Sl flag is reset to "O". The REX then switches from the deduction mode to the I / O mode.

5

Timetable

The time diagrams for the REX in the I / O read mode, the I / O write mode and for the external rule memory are shown in Figures 10-12, respectively. The AC (alternating current) properties of the REX in the I / O mode are shown in Table D.

10

TABLE D

AC SPECIFICATION

Symbol Parameter Min Min Type Max Unit 15 -: - TAS l / O address set time 20 - ns ("I / O Address Setup Time") TAH l / O address hold time 10 - - ns 20 ("I / O Address Hold Time" ) TIW l / O read / write signal width 60 - - ns ("I / O Read / Write Signal Width") 25 TOD Data output delay time - - 40 ns ("Data Output Delay Time") TOH Data output hold time 10 - - ns (" Data Output Hold Time ”) 30 - TDS Data setup time 20 - - ns (" Data Setup Time ") TDH Data retention time 10 - - ns 35 (" Data Hold Time ") TRS Ready signal setup time 0 - - ns (" READY Signal Setup Time ”) 40 TRD Ready signal delay time 0 - CLK * 1 ns (“ READY Signal Delay Time ”) TRW Ready signal width CLK-10 CLK * 1 CLK + 10 ns (“ READY Signal Width ”) 45 - TMAW External memory address signal width - CLK * 2 CLK * 2 + 20 ns ("External Memory CLK * 2-20 Address Signal Width") 50 TMAC External memory address access time ("External - - 170 ns

Memory -

Address Access Time ”) TMOH External memory data output retention time - - ns 55 (" External 0

Memory Data Output Hold Time ") 15 194520

TABLE D

AC SPECIFICATION (continued)

Symbol Parameter Min Min Type Max Unit 5 _______ - ___ _ _ -___— TCSS External memory chip selection set time - - - ns ("External Memory 0 Chip Select Setup Time") 10 TCSH External memory chip selection hold time ns ("External Memory 0 Chip Select Hold Time ”) TMOZ External memory output change (" External - 20 - ns

Memory Output Floating ”)

GLOSSARY

20

Antecedent The jf (if any) part of a production regulation.

Application area The subject or field that is relevant to the expert system.

Application- A set of rules, which have been selected by a knowledge engineer, and a specific application area is relevant for the set of prescriptions.

25 ASIC Application-specific integrated circuit ("Application Specific Integrated

Circuit ”) is a tailor-made integrated circuit for a specific application.

Consequence The then (then) part of a production regulation.

CPU Central processing unit ("Central Processing Unit"): An operating unit 30 which processes instructions and data.

Co-processor A specialized processor that works together with a main computer to increase the quality of the entire system.

Control logic A customized circuit that controls all operations required for the REX chip.

35 DMA Direct memory access: A method common to communication technology between a main computer and computer peripherals. DMA provides the most efficient way of transferring a block of data. External A block of binary data that resides in a main computer memory. , data 40 External memory A physical memory in which the application prescription set is stored.

Fact A truth that is known through factual experience or observation. A group of facts is collected for the assumption.

Deduction Interpreting a prescription from an application prescription set.

Deduction machine A problem-solving steering mechanism for an expert system.

45 l / O interface A type of device controller that is responsible for communication between the main computer system and computer peripherals.

Knowledge engineer A person who extracts knowledge and facts from a relevant application area and converts them into an application prescription set.

PC Personal computer.

50 PC / DOS The disk management system ("Disk Operating System") of a personal computer, which controls the read / write operations of a disk controller.

Production- A prescription specified in an if-then format, prescription RAM Random Access Memory: An electronic 55 memory that contains binary information that is accessible for reading or writing.

194520 16 ROM Dead memory ("Read-Only Memory"): An electronic memory that stores the binary information. A ROM is only accessible for reading; it does not have 5 writing options.

Regulations - An organization chart with which the production regulations are efficiently stored in information - to save memory space and processing time, bank structure

Working memory A RAM that is housed in the REX chip for storing the initial *, intermediate and final data of a deduction process.

Users - A computer program that is responsible for communication between the end-user interface and the main computer system.

Example of an animal identification prescription set REGULATION 1 15 IF

(cover = hair)

THEN

(class = mammal).

REGULATION 2 20 IF

(production = milk)

THEN

(class = mammal).

REGULATION 3 25 IF

(cover = springs)

THEN

(class = bird).

REGULATION 4 30 IF

(movement = flies) and (production = eggs)

THEN

(class = bird).

35 REQUIREMENT 5 IF

(food = meat)

THEN

(meat eater = yes).

40 REQUIREMENT 6 IF

(teeth = pointed) and (lid = claws) and (eyes = forward)

45 THEN

(carnivore = yes).

REGULATION 7 IF

(class = mammal) and 50 (members = hooves)

THEN

(type = required).

REGULATION 8 IF

55 (class = mammal) and (food = ruminant mass)

THEN

17 194520 (type = required) and (toes = even).

REGULATION 9 IF

5 (class = mammal) and (type = meat eater) and (color = tan) and (spots = dark)

THEN

10 (animal = cheetah).

REGULATION 10 IF

(class = mammal) and (type = meat eater) and 15 (color = tan) and (stripes = black)

THEN

(animal = tiger).

REGULATION 11 20 IF

(type = hoved) and (neck = long) and (legs = long) and (spots = dark)

25 THEN

(animal = giraffe).

REGULATION 12 IF

(type = hoved) and 30 (stripes = black)

THEN

(animal = zebra).

REGULATION 13 IF

35 (class = bird) and (movement <> fly) and (neck = long) and (legs = long) and 40 (color = black and white)

THEN

(animal = ostrich).

REGULATION 14 IF

45 (class = bird) and (movement = <> fly) and (swimming = yes) and (color = black and white)

THEN

50 (animal = penguin).

REGULATION 15 IF

(class = bird) and (movement = good-flying) (animal = albatross).

55 THEN

Claims (10)

194520 18 1, Hardware-implemented rule-based expert system device for performing high-speed deductions based on a prescription set for an application area, comprising: allocated working memory means for storing therein relating to the application area; allocated prescription memory means for storing therein the prescription set for the scope, comprising a series of instructions that each define a condition or an action; Logical means; a first communication bus communicatively connecting the working memory means to the logic means; a second communication bus that is communicatively connected to the prescription memory means; which logical means comprise allocated means for successively executing the instructions in the prescription memory means obtained via the second communication bus, with reference to the stored facts in the working memory means as obtained via the first communication bus, in order thereby to deduce new facts and wherein at least one of said instructions of each rule represents a condition to be satisfied by the facts of a given problem and comprising: (i) an operation code defining a logical operation to be performed; (ii) a first operand defining a first value to be compared by the logical operation and (iii) a second operand defining the address in the working memory that contains a second value to be compared by the logical operation. 2. Hardware-implemented rule-based expert system device capable of performing high-speed deductions based on a set of prescriptions for an application area, comprising: allocated working memory means for storing therein facts relating to the application area; allocated prescription memory means for storing therein the prescription set for the scope, comprising a set of instructions that each define a condition or an action; logical means; a first communication bus communicatively connecting the working memory means to the logic means; a second communication bus that is communicatively connected to the prescription memory means; Which logical means comprise allocated means for successively executing the instructions in the prescription memory means obtained via the second communication bus, with reference to the stored facts in the working memory means as obtained via the first communication bus, in order thereby to deduce new facts and at least one of the instructions of each prescription represents an action to be performed if all 40 conditions of the prescription are met and comprising: (i) an operation code defining the action to be performed and (ii) a first operand representing a defines a value for a fact and (iii) a second operand defining an address in the working memory means, in which the value defined in the first operand is to be stored. A hardware-implemented rule-based expert system device according to claim 1 or 2, characterized in that the prescription set is stored as a set of instructions in successive memory addresses starting at one end of the prescription memory means and further comprising means for storing a prescription index in successive memory addresses starting at the opposite end of the prescription memory means, which prescription index comprises a series of 50 memory addresses defining the initial memory address of each prescription of the prescription set. Device according to one of claims 1 to 3, characterized in that the means for successively executing instructions in the prescription memory means comprises prescription memory counting means comprising an address register for storing the address of the current instruction in the prescription 55 memory means and means for updating the address register with the address of the next instruction at any time that an instruction is retrieved from the prescription memory means. Device according to one of claims 1 to 4, characterized in that the logic means sequentially execute the instructions in the prescription memory means to perform deductions with forward chaining on the stored prescription set and thereby the new facts to deduce. Device according to one of the preceding claims, characterized in that it comprises means that function if the logical result of the logical operation is TRUE for effecting the retrieval of the next instruction of the same rule. Device according to one of the preceding claims, characterized in that it comprises means which function if the logical result of the logical operation is ERROR for retrieving the | first instruction of the following requirement. 8. Device as claimed in any of the foregoing claims, characterized in that each of the instructions also comprises a direct / immediate flag for specifying the address mode of one of the operands. Hardware-implemented prescription-based expert system device according to one of the preceding claims, characterized in that the first communication bus is a bi-directional communication bus, the second communication bus is a unidirectional communication bus; The device also comprising an input-output interface and a bi-directional input-output interface bus that communicatively connects the operating memory means and the input-output interface for storing in the working memory from an external system of the facts relating on the field of application and for transferring the deduced new facts stored in the working memory to an external system and that each of the instructions of the prescription set comprises a condition / action flag and that the logic means comprise an instruction decoding unit for testing the condition / action flag to determine whether the instruction is a condition or an action, means operative if the instruction is a condition for comparing the operands in accordance with the logical operation specified by the operation code to generate a logical result and agents active ind and the instruction is an action 25 for performing the action specified by the operation code on the operands. A prescription-based expert system, characterized in that it comprises a hardware-implemented rule-based expert system device according to claim 9, as well as "host" computer means as said external system, which is communicatively connected to the working memory means for supplying of the facts relating to the field of application to the working memory means and for accepting the deduced new facts from the working memory means.