NL7808607A - AUTOMATIC TELECOMMUNICATIONS SWITCH SYSTEM. - Google Patents

Description

• / 'ν' · * '- # BELL TELEPHONE MANUFACTURING COMPANY S.A., Antwerp, Belgium AUTOMATIC TELECOMMUNICATIONS SWITCH SYSTEM.

The invention relates to an automatic telecommunication switching system comprising a switching network with a number of chains and control means which are able to invest chains and use them for establishing connections via the network, the control means scanning and detecting means for sensing the circuits and detecting at least one type of state changes and other events therein, wherein each of the chains may be in a busy or free state, first recorders associated with a group of at least one of the 10 chains and capable of collecting the detected state changes, second recording means associated with each of the chains for recording the detected other events, and reading means for regularly reading the content associated with that chain for each chain of one of the recording means and for reading the contents of d e other recording means when a recording means has collected a predetermined value.

Such an automatic telecommunication switching system is already known from the article "Faulty-trunk detection algorithms using EADAS / ICUR traffic data" by J.S.Kaufman published in the Bell 20 System Technical Journal, July-August 1977, biz 918-976. In this known system, the scanning and detecting means are capable of detecting each of the circuits, for example, trunks, changes of state thereof, for example from busy to free, and each of the first recording means is able to count these changes of state. The scanning and detecting means are further able to detect any circuit which is in the busy or free state, and the second recording means is able to count the number of times this busy state has been detected. Finally, the reading means regularly read the recorded value in the second recording means associated with a chain and when it is found that this value exceeds a predetermined value, the reading means compares the registered 7808607 2 value in the first recording device associated with this chain with a threshold value. . When this recorded value is less than the threshold value, the chain is considered normal, while it is considered an abnormal (killer) chain when the registered value is greater than the threshold value.

This known system is based on the insight that the holding time of such a "killer" chain is considerably less than that of a normal chain, so that it will have considerably more state transitions than a normal chain for a certain number of counted busy states. . In order to properly detect the state transitions and the busy states, it is understood that the sensing and detecting means should scan the circuits at sample intervals substantially equal to the normal hold time of these circuits.

This means that in the known system the knowledge of this holding time 15 is essential to determine whether or not an abnormal chain is present.

An object of the invention is to provide an automatic telecommunication switching system of the above-mentioned type which does not need to know the normal holding time to arrive at such a decision.

Another drawback of the known automatic telecommunication switching system is that the second recording means must be able to store a relatively large number, corresponding to the total number of times a chain has been occupied.

Another object of the invention is therefore to provide an automatic telecommunication switching system of the above-mentioned type in which the second recording means need only be able to register a very limited number of states, for example one of two possible binary states.

According to the invention, the above objects are achieved by the fact that the scanning and detecting means are able to detect for each of the chains that it is involved in a successful operation or not and that the reading means read the contents of a second recording means which in a chain, when the first 35 recording means belonging to this chain have collected the predetermined value, which value is equal to the minimum number of condition changes 7808607 * 3 to be registered in the first recording means belonging to a particular group of chains, in order to achieve that, with a predetermined high probability, each of these chains are involved in at least one successful operation 5 following such a change in state.

Therefore, by reading the contents of the second recording means, the reading means are able to check whether a circuit whose state has changed a predetermined number of times, for example from 0 to 1, by a transition corresponding to the loading of the chain is involved in a successful or unsuccessful operation after at least one of these investments.

Since the registration of a successful or unsuccessful operation of a chain in second recording means requires only one bit, these second recording means are of simple construction. A chain 15 is considered to be a normal or abnormal chain independent of the knowledge of the normal holding time of this chain, because the distinction between both types of chains is based only on whether they have been involved in a successful operation or not.

It should be noted that British Patent 1,505,517 20 already describes an automatic telecommunications switching system in which a first and a second recording means belong to each chain, the first recording means being a first counter to count the total number of successful and unsuccessful operations and second recording means is a second counter to count the number of unsuccessful operations in which the chain was involved. The contents of the second counter are read when the first counter belonging to the same chain has counted a predetermined value, this value depending on the traffic. Conclusions as to the correct or incorrect condition of the chain are then drawn from the number read. This patent does not disclose how the traffic dependent predetermined value is calculated and the second counter is more complicated than the second recording means used in the present invention.

Another feature of the control system according to the invention is that each of the first recording means belongs to a 7808607 4 group of chains and is able to collect the state changes of all chains of this group.

By registering the changes in the state of all chains of a group in a single first recording means, the current system becomes even simpler and less time is required for the readers to check the operation of these chains because only one first recording means has to be regularly read for each group of chains.

According to a preferred embodiment of the invention, the automatic telecommunication switching system comprises a multi-circuit switching network and a computer capable of investing chains and using them to establish connections over the switching network. The computer contains a processor and a memory with a number of first recording means each allocated to a group of 15 chains and used to record the total number of times each chain of the group has been invested without distinguishing between the chains, a number of second recording means each individually assigned to a chain and used to register the first investment as well as a successful operation of this chain and a number of third party recording means each assigned to a group of chains and used to store a predetermined reference value, the processor being adapted to scan the chains and detect the state changes and successful operations of these chains and record these events in the corresponding recording means. In addition, the processor is able to regularly compare the contents of corresponding first and third recording means in order to detect those groups of chains for which a number of investments greater than the predetermined reference value have been registered and the second recording means allocated to the chains of each of these 30 groups in order to find the abnormal chains that have been invested but have failed.

The invention will be explained in more detail with reference to the drawing. In the drawing: Fig. 1 shows a diagram of an automatic telecommunication switching system according to the invention; Fig. 2 shows the computer COMP of Fig. 1 in more detail.

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In Fig. 1, the automatic telecommunication system is a computer-controlled telephone switching system comprising a telephone switching network SN and a computer COMP which has access to this switching network SN via a peripheral equipment PE.

Only a portion of the telephone switching network SN is sufficient to explain the invention, that is to say, i.e. line chains LIC1 and LIC2 connected to the subscriber stations ST1 and ST2 via telephone lines L1 and L2, a start-jumper chain OJC, and a end-jumper chain TJC, respectively. digit receiver DR and switch-10 stages ST1-ST9. The switching stages of each of the sets ST1-ST4, ST5-ST7 and ST8-ST9 are interconnected by links (not shown). Each of the subscriber stations ST1 and ST2 includes a telephone set (not shown).

The peripheral equipment PE contains a number of test, marking and 15 drive chains, but only one marking chain MC, one drive chain DC

and four different types of test chains, i.e. LTR, NTR, MTR, PTR, are shown. These test, marking and drive chains are connected on the one hand to the computer COMP via a bus B1, an edge register PER and a bus B2 and on the other hand to the constituent parts of the switching network SN via diagrams B3-B16.

The test, mark and drive chains can perform various functions described below after these circuits have received instructions from the computer COMP via the bus B2, the peripheral register PER and the bus B1.

LTR is a line tester and more particularly a cyclic scanner and can check the (open or closed) states of the line loops between the line chains and the subscriber stations, for example between LICl and ST1. The line tester can also check the condition (energized or not) of the so-called isolating relays that are part of these line-30 circuits. Each of the isolation relays is energized when a switching route has been successfully established between the corresponding line chain and another chain, for example, between LICl and OJC via ST1-ST4.

Such a line tester is described in U.S. Patent 3,546,388.

NTR is a network tester which can collect the information state (occupied 7808607 6 or free) of all switching stage link shells such as the above-mentioned circuits which interconnect the switching stages of sets ST1-ST4, ST5-ST7 and ST8-ST9. This network tester can also test the condition (occupied or free) of the junction chains, such as OJC and TJC 5. Such a network tester is described in U.S. Pat. No. 3,573,383.

MTR is a so-called mixed chain tester and can ask the test points in the start and end jumper chains such as OJC and TJC to obtain the (open or closed) loop states of the calling and called 10 lines, for example L1 and L2. This tester is of the same type as the network tester NTR.

PTR is a so-called pole tester and can query the test points in the signaling units as in the digit receiver DR. This tester can also check the condition (busy or free) of this digit receiver DR 15 and collect the signals received by this unit. This tester is equivalent to the mixed chain tester MTR.

The marking circuit MC can establish the routes chosen by the computer between certain points in the network. Such a marking action has already been described in U.S. Pat. No. 3,536,847.

Finally, the drive circuit can raise or drop DC relays in the junction circuits such as OJC and TJC and in the signaling units such as DR.

In Fig. 2, the computer COMP is of the conventional type 25 and contains a memory MEM with four memory blocks M1-M4 and a processor CPU which is constituted by a computing unit AU, an input-output unit I / O and a control unit CU for controlling of the operations of the computing unit AU and the input-output unit I / O. These units are interconnected as shown and the unit I / O is connected to the peripheral register PER (Fig. 1) via the bus B2 and the memory MEM via a bus BI7. In a known manner, the processor CPU can access the memory MEM, for example to write information therein, to read information therefrom, and to perform logical operations, such as comparisons, on the read data. Memory block M1 stores the conditions of different constituent chains of the switching network SN, such as LICl, LIC2, 7808607

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7 OJC, TJC, DR, these states are obtained by the above testers. More specifically: the line input buffer LIB1 stores the loop state of the telephone line L1 and of the isolation relays contained in the LICl (not shown).

These states are also obtained by the line testers LTR; the line input buffer LIB2 stores the states of the telephone line L2 and of the separation relays contained in the LIC2 (not shown).

These states are also obtained by the line tester LTR;

- the junctor status buffer JSB (OJC) stores the network tester NTR

10 obtained status information (occupied or free) from the OJC on? - the junctor status buffer JSB (TJC) stores the status information (busy or free) of the TJC obtained by the network tester NTR? - the junctor input buffer JIB (OJQ) stores the loop state (open or closed) of a line connected to OJC such as L1. This state is obtained by the MTR? - the junction input buffer JIB (TJC) stores the loop state (open or closed) of a line connected to TJC such as L2. This condition is achieved by MTR; - the status buffer SB (DR) stores the status information (occupied or free) of the DR obtained by the pole tester PTR? - the memory location DIG is used to store the digits received by the DR. These figures are collected from the DR by the pool tester PTR.

The memory block M2 contains the storage cells M21-M2n assigned to different groups of 25 equal chains of the switching network SN and each such cell contains a number of places individually assigned to different chains of the group. Each such location is used to store two bits: a so-called investment bit SZR to indicate that the individually allocated circuit 30 has been invested (or occupied) for the first time and a so-called success bit SUC to indicate that this chain is involved in a successful operation. For example, the storage cell M21 is assigned to a group of digit receivers to which DR belongs and contains a number of 35 places individually assigned to different receivers of this group, the first place M211 of M21 being assigned to the drawn DR, for example. Likewise, for example, M2x is assigned to a group of junctors to which OJC belongs and the first memory location M2x1 of M2x is assigned to the drawn OJC. Similarly, M2yl is assigned to the drawn TJC.

The memory block M3 stores a number of counters M31-M3n 5 which are assigned to several of the above groups of switching network circuits SN. Each of these counters serves to count the number of times the chains of the associated group have been invested. For example, the counter M31 is assigned to a group of digit receivers to which DR belongs and counts the number of times these receivers have been invested.

Finally, the memory block M4 contains a number of locations M41-M4n which are assigned to several of the above groups of circuits and therefore also to several of the above counters M31-M3n. Each of these locations serves to store a predetermined reference value equal to the number of times that the chains of the associated group must be invested before an appropriate action is to be taken by the computer.

For example, the memory location M41 is allocated to the above group of digit receivers to which DR belongs and also to the counter 20 M31 and stores a reference or threshold value equal to the number of times these digit receivers must be invested before the computer has to take an appropriate action .

The reference or threshold value stored in each of the memory locations M41-M4n of the memory block M4 is calculated such that when the chains of the group to which this value is assigned are invested several times equal to that reference value, each of these chains is at least one successful operation must be involved. For example, for the signed digit receiver DR, successful operation means that the computer has detected by means of the tester PTR that this receiver has just received the telephone number of a called subscriber station ST2 from a calling subscriber station ST1. For example, for the incoming and outgoing junctors OJC and TJC, such successful operation means that the computer has detected by means of the MTR in the TJC that a loop closure of the line L2 has occurred in the called subscriber station ST2 after ST1 and ST2 have been connected through LI, LIC1, ST1-ST4, OJC, ST5-ST7, TJC, ST1-ST4, LIC2 and L2. The reference or threshold values mentioned above 7808607 I.V »9 take into account that any investment in a chain does not necessarily lead to a successful operation thereof and that an unsuccessful operation does not necessarily result from a failure of the chain . For example, it may happen that although the circuit DR is properly invested, it cannot perform proper operation since no digits have been received, for example, because the subscriber has imposed in the calling station ST1 before dialing.

The reference or threshold value described in the introduction to the application will now be calculated by first deriving the minimum number of effective investments r in terms of n. Then the total number of k (effective and ineffective) investments from a group of n chains, i.e. k, can be found by relating this to r.

15 The minimum number of effective investments corresponds to the probability P that with r investments, each of the n chains must be invested at least once. This probability is given by P - e'm (1) 20 in which m is a parameter equal to both the mean and the variation of the probability distribution and is determined by x_ m = ne n (2)

This is derived, for example, in the publication "An introduction to probability theory and its applications", Vol. 1, W. Feller, 3rd ed. Wiley 25 international edition 1974, biz 101-105, which deals with the corresponding problem of a random distribution of r balls in n cells assuming that each arrangement has a probability of n r. Subsequently, it was found that the probability of finding a given number of empty cells is a Poisson distribution when n is sufficiently large. In the particular case where no cell is empty, corresponding to the state that each of the n chains is invested at least once, the probability P is simply given by equation (1). By eliminating the parameter m (with P close to the unit, m is given by 1 — P) 35 gives equation (2) r as 7808607 ίο r = il ° 5t rr? (3)

In a practical example where there are η = 155 incoming junction chains and p = 0.999, r = 2209.

As already noted, the above does not distinguish between effective and non-effective investments and therefore the threshold value k must be higher than the above calculated value of r since the counters M31-M3n also count the ineffective investments.

This correction depends on the probability p that an investment is effective and on the distribution of the effective investments over the total number of effective and ineffective investments.

In order to value the latter and in fact show that it has little significance compared to the influence of p.15, a normal probability distribution for the effective investments can be assumed. In contrast to the Poisson distribution used above for which there is only one parameter m equal to both the mean and the variation, a normal or gush distribution has two different parameters for the mean and for the variation. 20 The former is kp where p = 1-q is the equal probability that some of the k investments are effective while the second is kpq as they are the mean and the variation for a binomial distribution giving the probability that an event whose probability of success is p, accurate r grinding in k attempts will be made. This is approximated by a normal distribution in standard form, ie 2 z ”~ 2 e ---------- (4) V 2 7f with the variable z, normally distributed with mean 0 and variation 1 given is by 30 z2 = lr W2 (5) kpq

This good approximation holds for sufficiently large values of k, and with neither p nor q = 1-p too close to 0, for example with kp, the average is 7803607 11. · 'Number of effective investments, or kq each greater than 5.

The normal or burst function defined by the expression (4) is a symmetrical bell-shaped curve extending to infinity on both sides and smoothing off at the r axis. The probability of exceeding the pre-calculated and given value of r by equation (3) is equal to the total area under the curve to the left of the ordinate + r and which is the cumulative distribution function whose value is the unit when r is on the right side reaches infinity, which corresponds to the total area under the 10 curve.

From tables of this function, one can therefore choose an ordinate ζ ^ for the standard variable z, which corresponds to the probability that the pre-calculated value of r for the number of investments is always exceeded, that is to say that the equation ( 3) given value of r is a minimum. It should be noted that the ordinate z ^ can also be selected from tables of the error function, also known as the probability integral, which is equal to the area under the same curve between the ordinates + z ^ and -z ^.

Namely, there is a simple linear relationship between the two functions: the difference between twice the cumulative distribution function and the error function is the unit. When such a special value z ^ for z is inserted into equation (5), the latter provides a square for the ratio between kp and r, that is: (^) - 2 (1 + s) ^ E. + 1 = 0 (6) r r 25 in which the positive parameter s is determined by S {<* 1 Vf> 2 (7>

The product of the two (positive) roots of equation (6) is the unit, one root being larger and the other (inversely) smaller than the unit. Therefore, when kp is greater than the pre-calculated minimum 30 male value of r, equation (6) gives ^ = 1 + s V2s + s2 = 1 + V ~ 2s (8) r 7808607 12 for the larger root, where the second expression for the ratio is an approximation, because s is small relative to the unit.

With a probability of 0.999 that the pre-calculated value of r for the number of investments will always be exceeded, the tables mentioned give z ^ = 3.72 and if q = 1-p is chosen at 0.7, i.e. say, that the probability that an investment is ineffective, and as the highest estimate obtained from practical measurements, the previously obtained value of r = 2209 gives a value of s = 0.0022 from equation (7). For such values 10, equation (8) gives kp equal to 2360 and therefore the threshold of k equals 7860 since 0.3 has been obtained experimentally for p. Therefore, the correction from r to kp compared to that from kp to k is small and the value obtained from equation (3) is already very close to kp.

The operation of the aforementioned computer-controlled telephone switching system is now described for a local call between the calling subscriber station ST1 and the called subscriber station ST2. It should be noted that some of these actions are fully described in U.S. Pat. No. 3,507,315.

The line tester LTR tests the states of the line chains such as LICl and LIC2. These states are read by the processor CPU and compared with the states stored in the corresponding line input buffers such as LIB1 and LIB2.

Since the line loop L1 connected to the line circuit LICl is supposed to be closed, the processor CPU detects a discrepancy (change of state) between the state of the test points of the LICl and those stored in the LIBl, and thus brings the LIBl on the latest position.

By means of the network tester NTR, the CPU then collects 30 status information (occupied or free) from the junction circuits and from the links in the switching stages. Using the pool tester PTR, the processor CPU further collects status information from the receiver units.

After collecting this information, the CPU selects a free incoming junctor OJC, a free digit receiver DR and free paths in the 35 switching stages ST1-ST4 and ST8-ST9 between LICl and OJC and between OJC and DR respectively.

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The CP (J accesses the memory block M1 to record the occupied states of OJC and of DR in the respective status buffers JSB (OJC) and SB (DR), respectively.

The CPU also accesses the memory block 5 M2 to set the investment bits SZR in the memory locations M211 and M2x1 which are respectively assigned to DR and OJC of the memory cells M21 and M2x. The CPU also accesses the memory block M3 to increase the counters M31 and M3n associated with the memory cells M21 and M2n by 1, respectively.

The CPU then activates the marker circuit MC which establishes the above-mentioned paths between LIC1 and OJC and between OJC and DR, and then activates the control circuit DC so that the DR sends dial tone to the calling subscriber station ST1.

After the calling subscriber station ST1 has received dial tone, it sends the subscriber number of the called subscriber station ST2 which has the line circuit LIC2 to the DR, from where it is collected by the CPU through the intermediary of the pool tester PTR.

When the CPU has just received this number and stored it in the memory location D16 of M1, it accesses the memory block M2 to set the success bit SUC in the memory location M211 associated with DR of the cell M21.

The CPU then activates the control circuit DC to break the connection between DR and OJC and, in the same manner as briefly described above, searches for a free TJC and for free paths in ST5-ST7 and in ST1-ST4 between OJC and TJC and between TJC and LIC2.

The CPU also accesses the memory block M1 to bring the status of DPR and TJC in the respective status buffers SB (DR) and JSB (TJC) to the last position.

The CPU also accesses the memory block M2 to place the investment bit SZR in the memory location M2yl allocated to TJC of the memory cell M2y.

The CPU then activates the marker MC, which establishes paths between OJC and LIC2 via ST5-ST7, TJC and ST1-ST4.

Thereafter, the CPU activates the control circuit DC so that the OJC sends alarm tone 35 to LIC1 and the TJC sends wake-up current to LIC2.

When the subscriber in the called subscriber station ST2 takes his 7808607 14 micro phone off the hook, a line loop to LIC2 is closed so that ST1 and ST2 can talk to each other. This new state is detected when the MTR mixed chain tester performs its test operation.

After detecting that a successful connection between ST1 and ST2 has been established, the CPU accesses the memory block M2 to store the success bits SUC in the memory locations M2x1 and M2yl belonging to cells M2x and M2y, respectively, belonging to OJC and TJC. to set.

The CPU regularly accesses each of the memory blocks M3 and M4 and compares the values stored in the corresponding counters M31-M3n with the reference values stored in the corresponding memory locations M41.M4n. When during such a comparison a counter value is found to be less than the corresponding reference value, the CPU takes no particular action. On the other hand, if a counter value is found to be at least equal to the corresponding reference value, the CPU accesses the memory block M2 to read out all the memory locations of the corresponding memory cell and then sets up all the bits of this cell and of the relevant counter 0 back. For example, if the counter value M31 is found to exceed the reference value stored in M41, the CPU reads out the contents of all memory locations of the storage cell M21 and then sets the bits of M21 and M31 to 0.

Instead of resetting a counter when the relevant reference value has been reached, it would also be possible not to do this but to increase its reference value. In this case, the counter would accumulate the number of times a chain has been invested since the beginning of an operation; this can be useful for statistical purposes.

The pairs of bits SZ, SUC belonging to different devices of the same group, which are read from the memory locations of a memory cell of M2 assigned to this group, may be in one of the following states; 00: this is a state which should normally not occur since, as explained above, the reference value k is calculated such that with a predetermined high probability 7808607 (99.99%) each device is invested and at least once successful is operated when the total number of times the devices of the group are invested is at least equal to this reference value; 11: this is the normal state indicating that the associated device has been invested and has subsequently been successfully operated at least once; 01: this is obviously an error condition; 10: This is a state that indicates that the associated device has been successfully invested, but has subsequently been unable to perform its function successfully. Such a condition indicates that the device is suspect.

After the above bits SZR, SUC are read, the CPU subjects the devices for which a state was found 15 to extensive tests and then keeps them in operation or decommissioning, while the other abnormal states 00 and 01 are operator are notified.

In the above-described embodiment, an individual investment bit SZR belongs to each chain to register a first investment of this chain and to a group of chains a common counter belongs to register all investments of the chains of this group. In another embodiment, however, one could replace the individual investment bit and the common counter with an individual counter. In this case, however, the number of counters 25 would be relatively high.

Instead of regularly comparing the counter values with the reference values, it would also be possible to preset the counters to initial values chosen to reach the same final value after a corresponding number of investments equal to a reference value is counted. Such an embodiment would avoid the need to store reference values, since the CPU would then only have to check regularly whether or not the counters have reached their same end value, but storing initial values in these counters is a complication.

In connection with the above, it is noted that the number of times a chain is made during a predetermined time interval is 7808607

Claims (5)

From the above it follows that knowing the holding time of a chain is not required to register it as successful or not, but that this knowledge is useful in order to correctly determine the just mentioned scanning frequency. The invention has been described with reference to embodiments which are only exemplary and do not limit the scope of the inventive idea. Conclusions: 1. Automatic telecommunications switching system comprising a switching network with a number of chains and control means capable of investing chains and using them for establishing connections via the network, the control means comprising scanning and detecting means for scanning the chains and detecting at least one type of state changes and other events therein, wherein each of the chains may be in a busy or free state, requiring first recording means from a group of at least one of the chains and in capable of collecting the detected state changes, second recording means associated with each of the chains for recording the other events detected, and reading means for regularly reading the contents of one of the recording means associated with that chain for each chain and to read the contents of the other recording medium when a recording means has collected a predetermined value, characterized in that the sensing and detecting means (CPU) are able to detect for each of the chains that it is involved in a successful operation or not and that the reading means (CPU) read the contents (SUC) of a second recording means (M211, ...) belonging to a chain, when the first recording means (M31, ...) belonging to this chain have collected the predetermined value (M41, ___) which value equals ^ 5 is the minimum number of state changes to be recorded in a first recording means associated with a particular group of chains, to ensure that, with a predetermined high probability, each of these chains is involved in at least one successful operation following such a state-2Q change. Automatic telecommunication switching system according to claim 1, characterized in that each of the first recording means (M31, ...) belongs to a group of the chains and can collect the state changes for all chains of this group. 3 * Automatic telecommunication switching system according to claim 2, characterized in that each of the second recording means (M211, ...) can store the first (SZR) of the state changes. Automatic telecommunication switching system according to 2Q claim 1, characterized in that the control means are a computer (COMP) with a processor (CPU) containing the detection means and the reading means and with a memory (MEM) containing the first ( M211, -) and second (M31, ...) registers. Automatic telecommunication switching system according to claim 1, characterized in that the reading means regularly read the value recorded in each of the first recording means (M211, ...) at a frequency which depends on the holding time of the chain to which the first recording means belongs. 7808607