GB2029670A - Automatic telecommunication switching system - Google Patents

Abstract

In a telecommunication exchange it is desirable to be able to detect circuits, which operate erroneously, and so are often seized and shortly thereafter released because they cannot operate correctly. For each group of like circuits, e.g. outgoing junctors, there is a first register to register the total number of times the circuits of the group have been seized. A second register is individually allocated to each circuit of the group to register the first seizure plus a successful operation thereof. A third register is allocated to the group to store a reference value which is equal to the number of seizures that should be registered in a first register in order that with a high degree of probability each of the circuits of the group should have been involved in at least one successful operation. When the contents of a first register are at least equal to those of the third register, the various corresponding second registers are analysed to find the faulty circuits.

Description

SPECIFICATION Automatic telecommunication switching system This invention relates to an automatic telecommunication switching system including a switching network with a plurality of circuits and control means able to seize and use circuits for setting up connec tionsthrough said network, said control means including scanning and detection means for scanning said circuits and detecting at least one type of change of condition and other events therein, each of said circuits being able to be in a busy or free condition, first register means associated with a group of at least one of said circuits and able to accumulate said detected changes of condition, second register means associated to each of said circuits for registering said detected other events, and reading means for regularly reading for each circuit the contents of one of said register means associated with this circuit and for reading the contents of the other of said register means when said one register means has accumulated a predetermined value.

Such a system is known from the article "Faultytrunk detection algorithms using EADAS/ICUR traffic data" by J.S. Kaufman, published in the Bell System Technical Journal, July-August 1977, pp 918 to 976.

In this known system the scanning and detection means can detect for each of the circuits, e.g. trunks, the changes of condition thereof, e.g. from busy to free, and each of the first register means can count these changes of condition. The scanning and detection means can also detect for each circuit that it is in the busy condition or not and the second register means can count the number of times this busy condition is detected. Finally, the reading means regularly read the value registered in the second register means associated with a circuit, and when this value is found to exceed said predetermined value the reading means compares the value registered in the first register means associated with this circuit with a threshold value.When this registered value is smaller than the threshold value the circuit is considered to be normal, whereas it is considered to be an abnormal or "killer" circuit when the registered value is larger than the threshold value.

The term "killer circuit" as used herein means one which is faulty but which can still be seized. Such seizure is followed almost immediately by release.

Hence such a killer circuit is seized many times, each for a relatively short time.

This known system is based on the insight that the holding time of such a killer circuit is much smaller than that of a normal circuit, so that is should have substantially more state transitions than a normal circuit for a given number of busy conditions counted. To correctly detect the state transitions and the busy conditions it is clear that the scanning and detection means should scan the circuits at sampling intervals substantially equal to the normal holding time of these circuits. This means that in this known system, the knowledge of this holding time is essential to decide that one is in the presence of a killer circuit or not.

An object of the present invention is to provide an automatic telecommunication switching system of the above type but which does not require the knowledge of the normal holding time of a circuit to come to such a decision.

A drawback of the known system is that the second register means has to be capable of storing a relatively large number corresponding to the total number of times a circuit is found busy.

Another object of the invention is therefore to provide a system of the above type but wherein the second register means only needs to be able to register a very restricted number of conditions, e.g.

one of two possible binary conditions.

According to the invention there is provided an automatic telecommunication switching system including a switching network with a plurality of circuits and control means able to seize and use circuits to set up connections through said network, wherein said control means includes scanning and detection means for scanning said circuits and detecting at least one type of change of condition and other events therein, each such circuit being able to be in a busy of free condition, wherein first register means associated with a group of at least one of said circuits can accumulate said detected changes of condition, wherein second register means associated with each of said circuits registers said detected other events, wherein reading means is provided for regularly reading for each circuit the contents of one of said register means associated with that circuit and for reading the contents of the other of said register means when said one register means has accumulated a predetermined value, wherein said scanning and detection means can detect for each said circuit that it has been involved in a successful operation or not, and that said reading means has read the contents of a second register means associated with a circuit when said first register means associated with this circuit has accumulated said predetermined value which predetermined value is equal to the minimum number of said changes of conditions that should be registered in a said first register means associated with a said group of circuits in order that with a predetermined high probability each of these circuits should have been involved in at least one successful operation subsequent to such a change of condition.

Hence the reading means, by reading the contents of the second register means, can check if a circuit whose condition has changed a predetermined number of times, e.g. from 0 to 1 with such a transition corresponding to a seizure of the circuit, has been involved in a successful operation or not subsequent to at least one such seizure. Because the registration of a successful or unsuccessful operation of a circuit in a second register means only requires one bit, this second register means is of a simple structure. A circuit will be found to be a normal or a killer circuit independently from the knowledge of the normal holding time of this circuit because the distinction between both types of circuits is solely based on the fact that it has been involved in a successful operation or not.

Note that British Patent No. 1 505 517 (C.Y.

Tournier 6) discloses an automatic telecommunication switching system wherein a first and a second register means are associated with each circuit, the first register means being a first counter used to count the total number of successful and unsuccessful operations and the second register means being a second counter used to count the number of unsuccessful operations in which this circuit is involved. The contents of the second counter are read when the first counter associated to the same circuit has counted a predetermined value, this value being dependent on the traffic. Conclusions as to the correct or faulty condition of the circuit are then drawn from the number read.In this earlier patent no information is given as to how the traffic dependent predetermined value is calculated and the second counter is more complicated than the second register means used in the present system.

In a preferred embodiment of the invention, the automatic telecommunication switching system includes a switching network with a plurality of circuits and a computer able to seize and use circuits for setting up connections through the network. The computer comprises a processor and a memory with a plurality of first register means each allocated to a group of circuits and used for registering the total number of times any circuit of the group has been seized without discriminating between the circuits, a plurality of second register means each individually allocated to a circuit and used for registering the first seizure as well as a successful operation of this circuit, and a plurality of third register means each allocated to a group of circuits and used for storing a predetermined reference value. said processor being adapted to scan the circuits and detect changes of condition and successful operations of these circuits and to register these events in the corresponding register means. The processor is further able to regularly compare the contents of corresponding first and third register means to detect those groups of circuits for which a number of seizures larger than the predetermined reference value has been registered and to read out the second register means allocated to the circuits of each of these groups in order to find the (killer) circuits which have been seized but have not operated successfully.

An embodiment of the invention will now be described in conjunction with the accompanying drawings, wherein Figure 1 is a schematic diagram of an automatic telecommunication switching system embodying the invention, and Figure 2 repre sent the computer COMP of Figure 1 in more detail.

Referring to Figure 1, the system shown therein is a computer controlled telephone switching system including a switching network SN and a computer COMP which has access to this switching network SN via a peripheral equipment PE.

Of the switching network SN only sufficient to explain the invention is shown, i.e. line circuits LIC1 and LIC2 connected to subscriber stations ST1 and ST2 via telephone lines L1 and L2 respectively, an originating junctor circuit OJC, a terminating junctor circuit TJC, a digit receiver DR and switching stages ST1 to ST9. The switching stages of each of the sets ST1-ST4, ST5-ST7 and ST8-ST9 are interconnected by links (not shown). Each of the subscriber stations ST1 and ST2 includes a telephone set (also not shown).

The peripheral equipment PE includes tester circuits, marker circuits and driver circuits, but only one marker circuit MC, one driver circuit DC and four different types of tester circuits, i.e. LTR, NTR, MTR and PTR, are shown. These circuits are connected to the computer COMP via a bus B1,a peripheral register PER and a bus B2, and also to the consti tuent parts of the switching network SN via schematically represented busses B3 to B1 6. The tester, marker and driver circuits can perform various functions described hereinafter after having received instructions from the computer COMP via the bus B2, the peripheral register PER and the bus B1.

LTR is a line tester and more particularly a cyclic scanner which checks the (open or closed) conditions of the line loops between line circuits and subscriber stations, e.g. between LIC1 and ST1. It can also check the condition (operated or not) of so-called cut-off relays each forming part of one of these line circuits. Each such cut-off relay is operated when a switching path has been successfully established (marked) between the corresponding line circuit and another circuit, e.g. between LIC1 and OJC via ST1-ST4. Such a line tester is described in British Patent No.1156103. (S. Kobus-A. Salle 18-3).

NTR is a network tester which can collect status information (busy or free) from all the switching stage interconnecting links, such as those interconnecting the stages of the sets ST1-ST4, ST5-ST7 and ST8-ST9. It can also test the status (busy or free) of the junctor circuits, such as OJC and TJC. Such a network tester is described in British patent No.

1182216 (A. LAUWERS et al 3-1-1).

MTR is a so-called mixed circuits tester able to interrogate test points in the originating and terminating junctors such as OJC and TJC to obtain the (open or closed) loop conditions of the calling and called lines, i.e. L1 and L2 respectively. This tester is of the same type as the network tester NTR.

PTR is a so-called pool tester which interrogates test points in the signalling units such as in the digit receiver DR. This tester can also check the status (busy or free) of this DR and collect signals received by this unit. It is similar to the tester MTR.

The marker circuit MC can set up paths selected by the computer between defined points in the network.

Such a marking operation is described in British patent No. 1150864 (H. ADELAAR-F. DE WIT 56-4).

Finally, the driver circuit DC can operate and release relays in the junctor circuits such as OJC and TJC and in the signalling units such as DR.

Referring to Figure 2 the computer COMP is of a "classical" type, and has a memory, including four memory blocks M1 to M4, and a processor CPU formed by an arithmetic unit AU, an input-output un)t I/O and a control unit CU for controlling the operations of the unit AU and the unit I/O. These units are interconnected as shown and the unit I/O is connected to the peripheral register PER via the bus B2 and to the memory MEM through a bus B17. In known manner the processor CPU can access the memory MEM, e.g. to write information therein, to read information therefrom and to perform logic operations, such as comparisons, on the data read.

Memory block M1 stores the conditions of various constituent circuits of the network SN, such as LIC1, LIC2, OJC, TJC, DR, these conditions being obtained by the above testers. More particularly: (a) the line input buffer LIB1 stores the loop condition of the telephone line L1 and of the cut-off relay (not shown) in the LIC1. These conditions are obtained by the line tester LTR; (b) the line input buffer LIB2 stores the loop condition of the telephone line L2 and of the cut-off relay (not shown) in the LIC2. These conditions are also obtained by LTR; (c) the junctor status buffer JSB (OJC) stores the status information (busy or free), of the OJC, obtained by the network tester NTR;; (d) the junctor status buffer JSB (TJC) stores the status information (busy or free), of the TJC, obtained by the network tester NTR; (e) the junctor input buffer JIB (OJC) stores the loop condition (open or closed) of a line such as L1 connected to OJC. This condition is obtained by the MTR; (f) the junctor input buffer JIB (TJC) stores the loop condition (open or closed) of a line such as L2 connected to TJC. This condition is obtained by the MTR; (g) the status buffer SB (DR) stores the status information (busy or free), of the DR, obtained by the pool tester PTR; (h) the memory location DIG is used for storing the digits received by the DR. These digits are collected from the DR by the pool tester PTR.

Memory block M2 comprises storage cells M21 to M2n allocated to distinct groups of like circuits of the network SN and each such cell comprises a number of locations individually allocated to distinct circuits of the group. Each such location is used to store two bits: a so-called seizure bit SRZ to indicate that the individually-allocated circuit has been seized (or made busy) forthe first time, and a so-called success bit SUC to indicate that this circuit has been involved in a successful operation. For instance, storage cell M21 is allocated to a group of digit receivers to which DR belongs, and comprises a number of locations individually allocated to distinct receivers of this group, the first location M21 1 of M21 being for instance allocated to the DR shown.Likewise, M2x is for instance associated with a group of junctors to which OJC belongs and the first memory location M2xl of M2x is allocated to the OJC shown.

Similarly M2yl is allocated to the TJC shown.

Memory block M3 stores a number of counters M31 to M3n allocated to distinct ones of the above-mentioned groups of circuits of the network SN. Each of these counters serves for counting the number of times the circuits of the associated group have been seized. For instance, counter M31 is associated with a group of digit receivers to which DR belongs and counts the number of times these receivers have been seized.

Finally, memory block M4 comprises a number of locations M41 to M4n allocated to distinct ones of the above-mentioned groups of circuits and thus also to distinct ones of the above counters M31 to M3n. Each such location serves for storing a predetermined reference value equal to the number of times the circuits of the associated group have to be seized before an appropriate action has to be taken by the computer. For instance, memory location It141 is associated with the above-mentioned group of digit receivers to which DR belongs, and also to the counter M31 and stores a reference or threshold value equal to the number of times these digit receivers have to be seized before the computer has to take an appropriate action.

The reference or threshold value stored in each of the memory locations M41 to M4n of the memory block M4 has been so calculated that when the circuits of the group to which this value is allocated have been seized a number of times equal to that reference value, each such circuit should have been involved in at least one successful operation. For instance, for the digit receiver DR shown, successful operation means that the computer by means of the tester PTR has detected that this receiver has correctly received the telephone number of a called subscriber station ST2 from a calling subscriber station ST1.For the originating and terminating junctors OJC and TJC such a successful operation for instance means that the computer, by means of the MTR, has detected in the TJC that a loop closure of line L2 has occurred in the called station ST2 after ST1 and ST2 have been interconnected via L1, LIC1, ST1-ST4, OJC, ST5-ST7, TJC, ST1-ST4, LIC2 and L2.

The above reference or threshold values take into account that every seizure of a circuit does not necessarily lead to a successful operation thereof and that an unsuccessful operation is not necessarily due to a failure of the circuit. For instance, although it has been correctly seized it may happen that the DR shown has not been able to perform a correct operation beacuse no digits have been received, e.g.

because the calling subscriber has hung up before having started dialling.

The reference or threshold value discussed in the opening paragraphs will now be calculated by first deriving the minimum number of effective seizures r in terms of n. Then, the total number k of (effective and ineffective) seizures out of a group of n circuits, i.e. k, can be found by relating itto r.

The minimum number of effective seizures corresponds to the probability P that with r seizures, each of the n circuits should have been seized at least once. This probability is given by P = e-m (1) where m is a parameter equal both to the mean and to the variance of the probability distribution and defined by m = ne -r (2) n This is derived for instance in "An introduction to probability theory and its applications", Volume 1, W. Feller, 3rd edition, Wiley international edition, 1974, p. 101 to 105, by treating the equivalent problem of a random distribution of r balls in n cells, assuming that each arrangement has probability n-r.

Then the probability of finding a given number of cells empty is found to be a Poisson distribution when n is sufficiently large. In the particular case of no cell being empty, corresponding to each of the n circuits having been seized at least once, the probability P is simply given by equation (1). Eliminating parameter m (with P close to unity m is then given by 1-P), equation (2) gives ras

Taking a practical example with n = 155 originating junctor circuits and with P = 0.9999, r is equal to 2209.

As noted, the above does not distinguish between effective and ineffective seizures, so the threshold value k should be higher than the value of r calculated above since the counters M31 to M3n also count the ineffective seizures. This correction depends on the probability p of a seizure being effective as well as on the distribution of the effective seizures among the total number of effective and ineffective seizures.

To assess the latter and show in fact that it has little significance as compared to the effect of p, one may assume a normal probability distribution for the effective seizures. Contrary to the Poisson distribution used above and for which there is only one parameter m equal to both the mean and the variance, a normal or gaussian distribution has two distinct parameters for the mean and for the variance. The first is kp where p = 1 - q is the equal probability of any of the k seizures being effective while the second is kpq since these are the mean and variance for a binominal distribution giving the probability that an event whose probability of success is p will happen exactly r times in k trials. This is closely approximated by a normal distribution in standard form, i.e.

with the variate z, normally distributed with mean zero and variance one, and given by

This close approximation is valid for sufficiently large values of k and with neither p nor q = 1 - p too close to zero, e.g. with kp, the mean number of effective seizures, or kq each greater than 5.

The normal or gaussian function defined by expression (4) is a symmetrical bell-shaped curve extending to infinity on either side and flattening rapidly upon the r axis. The probability to exceed the previously calculated value of rand given by equation (3) is equal to the total area under the curve on the left of the ordinate +r and which is the cumulative distribution function whose value is unity when r reaches infinity on the righthand side, this corresponding to the total area under the curve.

From tables of this function one can therefore select an ordinate za for the standard variate z and corresponding to the probability that the previously calculated value of r for the number of seizures shall always be exceeded, i.e. that the value ofrgiven by equation (3) is a minimum. Note that the ordinate z, can also be selected from tables of the error function, also known as the probability integral, and which is equal to the area under the same curve between the ordinates +z1 and -ZL. indeed, there is a simple linear relation between the two functions: the difference between twice the cumulative distribution function and the error function is unity.With such a particular value z, for z being inserted in equation (5), the latter provides a quadratic for the ratio between kp and r, i.e.

where the positive parameters is defined by

The product of the two (positive) roots of equation (6) is unity, one root being larger than unity and the other (inverse) smaller. With kp being larger than the previously calculated minimum value of r, equation (6) thus gives

for the larger root, with the second expression for the ratio being an approximation due to s being small with respect to unity.

Indeed, with a probability of 0.9999 that the previously calculated value of rforthe number of seizures shall always be exceeded, the mentioned tables give z = 3.72 and if q = 1 - p is chosen as 0.7, i.e. the probability that a seizure is ineffective and as a highest estimate obtained from practical measurements, the previously obtained value of r = 2209 gives a value of s = 0.0022 from equation (7). For such values, equation (8) gives kp equal to 2360 and accordingly, in view of 0.3 having been experimentally obtained for p, the threshold value of k is 7860.

Thus, as compared to that from kp to k the correction from r to kp is slight and the value obtained from equation (3) is already very close to kp.

The operation of the above disclosed computer controlled telephone switching system is described hereinafter in relation to a local cali between the calling subscriber station ST1 and the called subscriber station ST2. Note that some of these operations are described at length in British patent No. 1181182 (S. KOBUS et al 19-4-1-2-13).

The line tester LTR tests the conditions of the line circuits such as LIC1 and LIC2. These conditions are read by the processor CPU and compared with the conditions stored in the corresponding line input buffers such as LIB1 and LIB2. As the line loop L1 connected to the line circuit LIC1 is assumed to have been closed the processor CPU detects a mismatch (change of condition) between the condition of the test points of the LIC1 and those stored in the LIB1, and hence updates the LIB1.

Via the network tester NTR the CPU then collects status information (busy or free) from the junctor circuits and from the links in the switching states.

With the help of the pool tester PTR, the processor CPU further collects status information from the receiver units. After having collected this information the CPU selects a free originating junctor OJC, a free digit receiver DR and free paths in the switching stages ST1-ST4 and ST8-ST9 between LIC1 and OJC and between OJC and DR respectively.

The CPU accesses the memory block M1 to register the busy status of OJC and of DR in the corresponding status buffers JSB (OJC) and SB (DR) respectively. It also accesses the memory block M2 to set the seizure bits SZR to 1 in memory locations M211 and M2x1 allocated to DR and OJC of the storage cells M21 and M2x respectively. The CPU also accesses the memory block M3 to increment by 1 the counters M31 and M3n associated with the storage cells M21 and M2n respectively.

The CPU then operates the marker circuit MC, which establishes the above-mentioned paths between LIC1 and OJC and between OJC and DR and afterwards operates the the driver circuit DC so that the DR sends dial tone to the calling subscriber station ST1.

After the calling subscriber station ST1 has received dial tone it transmits the number of the called subscriber station ST2 having line circuit LIC2 to the DR from which it is collected by the CPU via 1 the pool tester PTR. When the CPU has correctly received and stored this number in memory location DIG of M1 it accesses the memory block M2 to set to 1 the success bit SUC in the memory location M21 1 associated to DR of the cell M21.

The CPU then operates the driver circuit DC to release the connection between DR and OJC, and as briefly described above, searches for a free TJC and for free paths in ST5-ST7 and in ST1-ST4 between OJC and TJC and between TJC and LIC2. The CPU also accesses the memory block M1 to update the status of DPR and TJC in the corresponding status buffers SB (DR) and JSB (TJC). It also accesses the memory block M2 to set the seizure bit SZR in memory location M2y1 allocated to TJC of the storage cell M2y.

The CPU then operates the market circuit MC, which establishes paths between OJC and LIC2 via ST5-ST7, TJC and ST1-ST4. Afterwards the CPU operates the driver circuit DC so that the OJC can send ringing tone to LIC1 and that the TJC can send ringing current to LIC2.

When the subscriber in the called subscriber station ST2 hooks-off his telephone handset a line loop towards LIC2 is closed so that ST1 and ST2 can communicate. This new condition is detected when the mixed circuits tester MTR performs its test operation.

After the CPU has thus detected that a successful connection has been established between ST1 and ST2 it accesses the memory block M2 to set the successful bits SUC in the memory locations M2x1 and M2yl associated with OJC and TJC of the cells M2x and M2y respectively.

The CPU regularly accesses each of the memory blocks M3 and M4, and compares the values stored in the corresponding counters M31 to M3n with reference values stored in the corresponding memory locations M41 to M4n. When during such a comparison a counter value is found to be smaller than the corresponding reference value the CPU takes no particular action. However, when a counter value is found to be at least equal to the corresponding reference value, the CPU accesses the memory block M2 to read out all the memory locations of the corresponding storage cell and subsequently resets to0 all the bits of this cell and of the corresponding counter.For instance, when the counter value M31 is found to exceed the reference value stored in M41 the CPU reads-out the contents of all the memory locations of the storage cell M21 and subsequently resets to 0 the bits of M21 and of M31.

instead of resetting a counter when the corresponding reference value is reached it would also be possible not to do so but to increase this reference value. In this case the counter would accumulate the number of times a circuit has been seized since the start of an operation; this may be useful for statistical purposes.

The pairs of bits SZR, SUC associated with distinct devices of a same group and read-out from the memory locations of a storage cell of M2 allocated to this group may be in one ofthe following conditions: 00 : this is a condition which should normally not occur because as explained above the refer ence value k has been so calculated that, with a predetermined high probability (99.99%), every device is seized and successfully oper ated at least once when the total number of times the devices of the group are seized is at least equal to this reference value; 11: this is the normal condition indicating that the associated device has been seized and then successfully operated at least once; 01 : this is obviously an erroneous condition; 10 : this is a condition indicating that the associ ated device has been successfully seized but has subsequently not been able to successful ly execute its function. Such a condition indicates that the device is suspect.

After having read the above SZR, SUC bits the CPU submits the devices for which a 10 condition was found to extensive tests and subsequently maintained in service or put out of service, whilst the other abnormal conditions 00 and 01 are communicated to the operator.

In the above described embodiment an individual seizure bit SZR is associated with each circuit to register a first seizure of this circuit, and a common counter is associated with a group of circuits to register all the seizures of the circuits of this group In a different embodiment one could however replace the individual seizure bit and the common counter by an individual counter. But in this case the number of counters would be relatively high.

Instead of regularly comparing the counter values with the reference values it would also be possible to preset the counters to initial values so chosen that they reach a same end value after having counted a corresponding number of seizures equal to a reference value. Such an embodiment would eliminate the need of storing reference values because the CPU would then only have to regularly check if counters have reached their same end value or not, but storing initial values in these counters is a complication.

In connection with the above it should be noted that the number of times a circuit is seized during a predetermined time interval obviously depends on the traffic and on the holding time of this circuit.

More particularly, the number of seizures increases with increasing traffic and decreasing holding time so that the reference or threshold values k for the various groups of circuits will be reached more or less rapidly. In order that reaching a reference or threshold value should always be detected very soon, and as already mentioned above, the processor CPU regularly accesses each of the memory blocks M3 and M4 and compares the values in the corresponding counters M31 to M3n with the reference values stored in the corresponding memory locations M41 to M4n. Hereby the frequency at which such a comparison takes place depends on the maximum number of times the circuits of the corresponding group can be seized during peak traffic taking their normal holding time into account.

For instance, for a group of 95 receiver circuits having a holding time of about 10 seconds the associated memory block is scanned about every 10 minutes; for a group of 155 junctors having a holding time of about 120 seconds the associated memory block is scanned about every 107 minutes.

From the above it follows that the knowledge of the holding time of a circuit is not required to register it as successful or not, but that this knowledge is useful in order to correctly determine the just mentioned scanning frequency.

Claims (6)

1. An automatic telecommunication switching system including a switching network with a plurality of circuits and control means able to seize and use circuits to set up connections through said network, wherein said control means includes scanning and detection means for scanning said circuits and detecting at least one type of change of condition and other events therein, each such circuit being able to be in a busy or free condition, wherein first register means associated with a group of at least one of said circuits can accumulate said detected changes of condition, wherein second register means associated with each of said circuits registers said detected other events, wherein reading means is provided for regularly reading for each circuit the contents of one of said register means associated with that circuit and for reading the contents of the other of said register means when said one register means has accumulated a predetermined value, wherein said scanning and detection means can detect for each said circuit that it has been involved in a successful operation or not, and that said reading means has read the contents of a second register means associated with a circuit when said first register means associated with this circuit has accumulated said predetermined value which predetermined value is equal to the minimum number of said changes of conditions that should be registered in a said first register means associated with a said group of circuits in order that with a predetermined high probability each of these circuits should have been involved in at least one successful operation subsequent to such a change of condition.

2. Asystem according to claim 1, wherein each of said first register means is associated with a group of said circuits and can accumulate said changes of condition for all the circuits of this group.

3. A system according to claim 2, wherein each of said second register means can also store the first of said changes of condition.

4. A system according to claim 1, wherein said control means includes a computer with a processor including said detection means and said evaluating means and with a memory including said first and second register means.

5. A system according to claim 1, wherein said reading means regularly read the value registered in each of said first register means at a frequency depending on the holding time of the circuit to which said first register means is associated.

6. An automatic telecommunication switching system substantially as described with reference to the accompanying drawings.