NL7406760A - - Google Patents

Info

Publication number
NL7406760A
NL7406760A NL7406760A NL7406760A NL7406760A NL 7406760 A NL7406760 A NL 7406760A NL 7406760 A NL7406760 A NL 7406760A NL 7406760 A NL7406760 A NL 7406760A NL 7406760 A NL7406760 A NL 7406760A
Authority
NL
Netherlands
Application number
NL7406760A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19732325687 external-priority patent/DE2325687C3/de
Application filed filed Critical
Publication of NL7406760A publication Critical patent/NL7406760A/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
NL7406760A 1973-05-21 1974-05-20 NL7406760A (enExample)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19732325687 DE2325687C3 (de) 1973-05-21 Verfahren und Vorrichtung zur Festlegung der Reihenfolge, in der mehrere von mehreren Einheiten einer Datenverarbeitungsanlage an eine Einheit der Datenverarbeitungsanlage gestellte Anforderungen verschiedenen Typs durch eine Warteschlangensteuerung abgearbeitet werden

Publications (1)

Publication Number Publication Date
NL7406760A true NL7406760A (enExample) 1974-11-25

Family

ID=5881596

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7406760A NL7406760A (enExample) 1973-05-21 1974-05-20

Country Status (5)

Country Link
BE (1) BE815352A (enExample)
FR (1) FR2231050B1 (enExample)
GB (1) GB1473581A (enExample)
IT (1) IT1012372B (enExample)
NL (1) NL7406760A (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4320456A (en) * 1980-01-18 1982-03-16 International Business Machines Corporation Control apparatus for virtual address translation unit
ATE43730T1 (de) * 1984-07-31 1989-06-15 Siemens Ag Schaltungsanordnung fuer fernmeldevermittlungsanlagen, insbesondere fernsprechvermittlungsanlagen, mit an einer datenbusleitung anschaltbaren zentralen und/oder teilzentralen schalteinrichtungen.
DE3480962D1 (de) * 1984-10-31 1990-02-08 Ibm Deutschland Verfahren und einrichtung zur steuerung einer sammelleitung.
US4788640A (en) * 1986-01-17 1988-11-29 Intel Corporation Priority logic system
US5115507A (en) * 1987-12-23 1992-05-19 U.S. Philips Corp. System for management of the priorities of access to a memory and its application
FR2625341A1 (fr) * 1987-12-23 1989-06-30 Labo Electronique Physique Systeme de gestion des priorites d'acces a une memoire et son application
EP0324662A3 (en) * 1988-01-15 1990-01-17 EVANS & SUTHERLAND COMPUTER CORPORATION Crossbar system for controlled data transfer
US8490107B2 (en) 2011-08-08 2013-07-16 Arm Limited Processing resource allocation within an integrated circuit supporting transaction requests of different priority levels

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3492654A (en) * 1967-05-29 1970-01-27 Burroughs Corp High speed modular data processing system
FR2154968A5 (enExample) * 1971-10-01 1973-05-18 Telemecanique Electrique

Also Published As

Publication number Publication date
IT1012372B (it) 1977-03-10
GB1473581A (en) 1977-05-18
BE815352A (fr) 1974-11-21
DE2325687A1 (de) 1974-12-12
DE2325687B2 (de) 1976-05-13
FR2231050A1 (enExample) 1974-12-20
FR2231050B1 (enExample) 1979-03-09

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Legal Events

Date Code Title Description
BV The patent application has lapsed