NL7306948A - - Google Patents

Info

Publication number
NL7306948A
NL7306948A NL7306948A NL7306948A NL7306948A NL 7306948 A NL7306948 A NL 7306948A NL 7306948 A NL7306948 A NL 7306948A NL 7306948 A NL7306948 A NL 7306948A NL 7306948 A NL7306948 A NL 7306948A
Authority
NL
Netherlands
Application number
NL7306948A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to NL7306948A priority Critical patent/NL7306948A/xx
Priority to CH668474A priority patent/CH588163A5/xx
Priority to IT22800/74A priority patent/IT1012429B/it
Priority to US05/470,387 priority patent/US4000019A/en
Priority to DE2423816A priority patent/DE2423816A1/de
Priority to GB2205474A priority patent/GB1471736A/en
Priority to JP5502974A priority patent/JPS5522022B2/ja
Priority to FR7417426A priority patent/FR2230083B1/fr
Priority to AU69126/74A priority patent/AU6912674A/en
Publication of NL7306948A publication Critical patent/NL7306948A/xx

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02609—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
    • Y10S117/901—Levitation, reduced gravity, microgravity, space
    • Y10S117/902—Specified orientation, shape, crystallography, or size of seed or substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/973—Substrate orientation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/975—Substrate or mask aligning feature

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
NL7306948A 1973-05-18 1973-05-18 NL7306948A (ko)

Priority Applications (9)

Application Number Priority Date Filing Date Title
NL7306948A NL7306948A (ko) 1973-05-18 1973-05-18
CH668474A CH588163A5 (ko) 1973-05-18 1974-05-15
IT22800/74A IT1012429B (it) 1973-05-18 1974-05-15 Metodo per la fabbricazione di di spositivi semiconduttori e dispo sitivi semiconduttori prodotti con tale metodo
US05/470,387 US4000019A (en) 1973-05-18 1974-05-16 Method of retaining substrate profiles during epitaxial deposition
DE2423816A DE2423816A1 (de) 1973-05-18 1974-05-16 Verfahren zur herstellung von halbleiteranordnungen und durch dieses verfahren hergestellte halbleiteranordnungen
GB2205474A GB1471736A (ko) 1973-05-18 1974-05-17
JP5502974A JPS5522022B2 (ko) 1973-05-18 1974-05-18
FR7417426A FR2230083B1 (ko) 1973-05-18 1974-05-20
AU69126/74A AU6912674A (en) 1973-05-18 1974-05-20 Semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7306948A NL7306948A (ko) 1973-05-18 1973-05-18

Publications (1)

Publication Number Publication Date
NL7306948A true NL7306948A (ko) 1974-11-20

Family

ID=19818883

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7306948A NL7306948A (ko) 1973-05-18 1973-05-18

Country Status (9)

Country Link
US (1) US4000019A (ko)
JP (1) JPS5522022B2 (ko)
AU (1) AU6912674A (ko)
CH (1) CH588163A5 (ko)
DE (1) DE2423816A1 (ko)
FR (1) FR2230083B1 (ko)
GB (1) GB1471736A (ko)
IT (1) IT1012429B (ko)
NL (1) NL7306948A (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0020135A1 (en) * 1979-05-29 1980-12-10 Massachusetts Institute Of Technology Three-dimensional integration by graphoepitaxy

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2828607C3 (de) * 1977-06-29 1982-08-12 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa Halbleitervorrichtung
US4278987A (en) * 1977-10-17 1981-07-14 Hitachi, Ltd. Junction isolated IC with thick EPI portion having sides at least 20 degrees from (110) orientations
JPS5691903U (ko) * 1979-12-17 1981-07-22
JPS5694732A (en) * 1979-12-28 1981-07-31 Fujitsu Ltd Semiconductor substrate
US4355072A (en) * 1980-02-12 1982-10-19 U.S. Philips Corporation Magnetic hexagonal ferrite layer on a nonmagnetic hexagonal mixed crystal substrate
JPS5930696A (ja) * 1982-08-05 1984-02-18 本多　浩 汎用位置決めと速度制御が可能なエアシリンダと補助駆動装置からなる複合アクチユエ−タ
JPS6290095U (ko) * 1985-11-22 1987-06-09
JPS6339396U (ko) * 1986-09-01 1988-03-14
JPH01151144U (ko) * 1988-04-12 1989-10-18
JP2603342B2 (ja) * 1988-10-02 1997-04-23 キヤノン株式会社 結晶物品及びその形成方法
JP2570646B2 (ja) * 1994-12-13 1997-01-08 日本電気株式会社 Ｓｉベ−ス半導体結晶基板及びその製造方法
US6171966B1 (en) * 1996-08-15 2001-01-09 Applied Materials, Inc. Delineation pattern for epitaxial depositions
DE19915156A1 (de) * 1999-03-27 2000-09-28 Inst Halbleiterphysik Gmbh Verfahren zur Herstellung dünner gleichförmiger Oxidschichten auf Silizium-Oberflächen
TW483171B (en) * 2000-03-16 2002-04-11 Trw Inc Ultra high speed heterojunction bipolar transistor having a cantilevered base.
JP5075469B2 (ja) 2007-05-08 2012-11-21 株式会社オーディオテクニカ グースネック型マイクロホン
US8389099B1 (en) 2007-06-01 2013-03-05 Rubicon Technology, Inc. Asymmetrical wafer configurations and method for creating the same
US8348720B1 (en) 2007-06-19 2013-01-08 Rubicon Technology, Inc. Ultra-flat, high throughput wafer lapping process

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3325314A (en) * 1961-10-27 1967-06-13 Siemens Ag Semi-conductor product and method for making same
US3379584A (en) * 1964-09-04 1968-04-23 Texas Instruments Inc Semiconductor wafer with at least one epitaxial layer and methods of making same
US3476592A (en) * 1966-01-14 1969-11-04 Ibm Method for producing improved epitaxial films
US3556875A (en) * 1967-01-03 1971-01-19 Philco Ford Corp Process for epitaxially growing gallium arsenide on germanium
US3728166A (en) * 1967-01-11 1973-04-17 Ibm Semiconductor device fabrication method and product thereby
US3697318A (en) * 1967-05-23 1972-10-10 Ibm Monolithic integrated structure including fabrication thereof
JPS4830787B1 (ko) * 1967-12-28 1973-09-22
NL171309C (nl) * 1970-03-02 1983-03-01 Hitachi Ltd Werkwijze voor de vervaardiging van een halfgeleiderlichaam, waarbij een laag van siliciumdioxyde wordt gevormd op een oppervlak van een monokristallijn lichaam van silicium.

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0020135A1 (en) * 1979-05-29 1980-12-10 Massachusetts Institute Of Technology Three-dimensional integration by graphoepitaxy

Also Published As

Publication number Publication date
JPS5020674A (ko) 1975-03-05
US4000019A (en) 1976-12-28
IT1012429B (it) 1977-03-10
JPS5522022B2 (ko) 1980-06-13
CH588163A5 (ko) 1977-05-31
GB1471736A (ko) 1977-04-27
DE2423816A1 (de) 1974-12-05
AU6912674A (en) 1975-11-20
FR2230083B1 (ko) 1977-10-21
FR2230083A1 (ko) 1974-12-13

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