NL7210124A - - Google Patents
Info
- Publication number
- NL7210124A NL7210124A NL7210124A NL7210124A NL7210124A NL 7210124 A NL7210124 A NL 7210124A NL 7210124 A NL7210124 A NL 7210124A NL 7210124 A NL7210124 A NL 7210124A NL 7210124 A NL7210124 A NL 7210124A
- Authority
- NL
- Netherlands
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Static Random-Access Memory (AREA)
- Dram (AREA)
- Read Only Memory (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19712136771 DE2136771C3 (de) | 1971-07-22 | Nach dem dynamischen Prinzip arbeitende Schaltungsanordnung aus MOS-Transistoren zur Decodierung der Adressen für einen MOS-Speicher |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| NL7210124A true NL7210124A (https=) | 1973-01-24 |
Family
ID=5814529
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| NL7210124A NL7210124A (https=) | 1971-07-22 | 1972-07-21 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US3786277A (https=) |
| BE (1) | BE786559A (https=) |
| DK (1) | DK125499B (https=) |
| FR (1) | FR2146248B1 (https=) |
| GB (1) | GB1388425A (https=) |
| IT (1) | IT962976B (https=) |
| LU (1) | LU65762A1 (https=) |
| NL (1) | NL7210124A (https=) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4159541A (en) * | 1977-07-01 | 1979-06-26 | Ncr Corporation | Minimum pin memory device |
| US4145760A (en) * | 1978-04-11 | 1979-03-20 | Ncr Corporation | Memory device having a reduced number of pins |
| US4148099A (en) * | 1978-04-11 | 1979-04-03 | Ncr Corporation | Memory device having a minimum number of pins |
| US4514829A (en) * | 1982-12-30 | 1985-04-30 | International Business Machines Corporation | Word line decoder and driver circuits for high density semiconductor memory |
| US4596004A (en) * | 1983-09-14 | 1986-06-17 | International Business Machines Corporation | High speed memory with a multiplexed address bus |
| FR2552257B1 (fr) * | 1983-09-16 | 1985-10-31 | Labo Electronique Physique | Circuit decodeur pour memoire ram statique |
| US20090109772A1 (en) * | 2007-10-24 | 2009-04-30 | Esin Terzioglu | Ram with independent local clock |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3706975A (en) * | 1970-10-09 | 1972-12-19 | Texas Instruments Inc | High speed mos random access memory |
-
1972
- 1972-05-01 US US00249416A patent/US3786277A/en not_active Expired - Lifetime
- 1972-07-11 GB GB3230172A patent/GB1388425A/en not_active Expired
- 1972-07-11 FR FR7225063A patent/FR2146248B1/fr not_active Expired
- 1972-07-19 IT IT27154/72A patent/IT962976B/it active
- 1972-07-20 BE BE786559D patent/BE786559A/xx unknown
- 1972-07-20 LU LU65762A patent/LU65762A1/xx unknown
- 1972-07-21 NL NL7210124A patent/NL7210124A/xx unknown
- 1972-07-21 DK DK363272AA patent/DK125499B/da unknown
Also Published As
| Publication number | Publication date |
|---|---|
| IT962976B (it) | 1973-12-31 |
| DE2136771B2 (de) | 1975-05-28 |
| LU65762A1 (https=) | 1973-01-26 |
| DE2136771A1 (de) | 1973-02-01 |
| DK125499B (da) | 1973-02-26 |
| FR2146248B1 (https=) | 1976-10-29 |
| BE786559A (fr) | 1973-01-22 |
| US3786277A (en) | 1974-01-15 |
| FR2146248A1 (https=) | 1973-03-02 |
| GB1388425A (en) | 1975-03-26 |