NL7005411A - - Google Patents

Info

Publication number
NL7005411A
NL7005411A NL7005411A NL7005411A NL7005411A NL 7005411 A NL7005411 A NL 7005411A NL 7005411 A NL7005411 A NL 7005411A NL 7005411 A NL7005411 A NL 7005411A NL 7005411 A NL7005411 A NL 7005411A
Authority
NL
Netherlands
Application number
NL7005411A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of NL7005411A publication Critical patent/NL7005411A/xx

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0005—Apparatus or processes for manufacturing printed circuits for designing circuits by computer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • General Physics & Mathematics (AREA)
  • Architecture (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
NL7005411A 1969-04-15 1970-04-15 NL7005411A (xx)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US81620869A 1969-04-15 1969-04-15

Publications (1)

Publication Number Publication Date
NL7005411A true NL7005411A (xx) 1970-10-19

Family

ID=25219970

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7005411A NL7005411A (xx) 1969-04-15 1970-04-15

Country Status (7)

Country Link
US (1) US3617714A (xx)
BE (1) BE748586A (xx)
CA (1) CA920274A (xx)
DE (1) DE2017667A1 (xx)
FR (1) FR2043338A5 (xx)
GB (1) GB1307261A (xx)
NL (1) NL7005411A (xx)

Families Citing this family (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2445368A1 (de) * 1974-09-23 1976-04-01 Siemens Ag Verfahren zur herstellung fuer maskenvorlagen fuer integrierte halbleiterschaltungen
US4495559A (en) * 1981-11-02 1985-01-22 International Business Machines Corporation Optimization of an organization of many discrete elements
US4593363A (en) * 1983-08-12 1986-06-03 International Business Machines Corporation Simultaneous placement and wiring for VLSI chips
US4577276A (en) * 1983-09-12 1986-03-18 At&T Bell Laboratories Placement of components on circuit substrates
JPH0679319B2 (ja) * 1985-04-10 1994-10-05 株式会社日立製作所 配置更新方法
JPH0666393B2 (ja) * 1986-05-23 1994-08-24 日本電気株式会社 レイアウト設計における配置改良方法
US4908772A (en) * 1987-03-30 1990-03-13 Bell Telephone Laboratories Integrated circuits with component placement by rectilinear partitioning
US4815003A (en) * 1987-06-19 1989-03-21 General Electric Company Structured design method for high density standard cell and macrocell layout of VLSI chips
US5140526A (en) * 1989-01-06 1992-08-18 Minc Incorporated Partitioning of Boolean logic equations into physical logic devices
US5187784A (en) * 1989-01-13 1993-02-16 Vlsi Technology, Inc. Integrated circuit placement method using netlist and predetermined ordering constraints to produce a human readable integrated circuit schematic diagram
US5251147A (en) * 1989-06-20 1993-10-05 Digital Equipment Corporation Minimizing the interconnection cost of electronically linked objects
US5448493A (en) * 1989-12-20 1995-09-05 Xilinx, Inc. Structure and method for manually controlling automatic configuration in an integrated circuit logic block array
US5224056A (en) * 1991-10-30 1993-06-29 Xilinx, Inc. Logic placement using positionally asymmetrical partitioning algorithm
WO1992009042A1 (en) * 1990-11-15 1992-05-29 Xilinx, Inc. Logic placement using positionally asymmetrical partitioning algorithm
US5303161A (en) * 1990-12-10 1994-04-12 Hughes Aircraft Company Technology independent integrated circuit mask artwork generator
JP3033203B2 (ja) * 1991-01-25 2000-04-17 株式会社日立製作所 配線経路探索装置及び配線経路探索方法
US5341308A (en) * 1991-05-17 1994-08-23 Altera Corporation Methods for allocating circuit elements between circuit groups
US5299139A (en) * 1991-06-21 1994-03-29 Cadence Design Systems, Inc. Short locator method
US5521836A (en) * 1991-06-28 1996-05-28 Vlsi Technology, Inc. Method for determining instance placements in circuit layouts
US5513124A (en) * 1991-10-30 1996-04-30 Xilinx, Inc. Logic placement using positionally asymmetrical partitioning method
EP0643855A1 (en) * 1992-06-04 1995-03-22 Xilinx, Inc. Timing driven method for laying out a user's circuit onto a programmable integrated circuit device
US5629859A (en) * 1992-10-21 1997-05-13 Texas Instruments Incorporated Method for timing-directed circuit optimizations
US5648913A (en) * 1993-03-29 1997-07-15 Xilinx, Inc. Frequency driven layout system and method for field programmable gate arrays
JPH06332983A (ja) * 1993-05-20 1994-12-02 Mitsubishi Electric Corp 部品配置最適化方法
JP2601177B2 (ja) * 1993-06-08 1997-04-16 日本電気株式会社 同期論理回路における最適クロック周期の決定方法
SG68564A1 (en) * 1994-01-25 1999-11-16 Advantage Logic Inc Apparatus and method for partitioning resources for interconnections
US5818726A (en) * 1994-04-18 1998-10-06 Cadence Design Systems, Inc. System and method for determining acceptable logic cell locations and generating a legal location structure
US5914887A (en) * 1994-04-19 1999-06-22 Lsi Logic Corporation Congestion based cost factor computing apparatus for integrated circuit physical design automation system
US5535134A (en) * 1994-06-03 1996-07-09 International Business Machines Corporation Object placement aid
US5675500A (en) * 1994-10-18 1997-10-07 International Business Machines Corporation Multi-chip device partitioning process
US5546517A (en) * 1994-12-07 1996-08-13 Mitsubishi Electric Information Technology Center America, Inc. Apparatus for determining the structure of a hypermedia document using graph partitioning
JP3373089B2 (ja) * 1995-08-28 2003-02-04 富士通株式会社 集積回路の初期配置決定装置
US5699265A (en) * 1995-09-08 1997-12-16 Lsi Logic Corporation Physical design automation system and process for designing integrated circuit chips using multiway partitioning with constraints
US5784287A (en) * 1995-09-29 1998-07-21 Lsi Logic Corporation Physical design automation system and process for designing integrated circuit chips using generalized assignment
US5787009A (en) * 1996-02-20 1998-07-28 Altera Corporation Methods for allocating circuit design portions among physical circuit portions
US5926632A (en) * 1996-04-11 1999-07-20 Matsushita Electric Industrial Co., Ltd. Circuit partitioning method, circuit partitioning apparatus, and computer-readable recording medium having thereon circuit partitioning program
US5872718A (en) * 1996-06-28 1999-02-16 Lsi Logic Corporation Advanced modular cell placement system
US6030110A (en) * 1996-06-28 2000-02-29 Lsi Logic Corporation Advanced modular cell placement system with median control and increase in resolution
US5835381A (en) * 1996-06-28 1998-11-10 Lsi Logic Corporation Advanced modular cell placement system with minimizing maximal cut driven affinity system
US6067409A (en) * 1996-06-28 2000-05-23 Lsi Logic Corporation Advanced modular cell placement system
US5812740A (en) * 1996-06-28 1998-09-22 Lsi Logic Corporation Advanced modular cell placement system with neighborhood system driven optimization
US5808899A (en) * 1996-06-28 1998-09-15 Lsi Logic Corporation Advanced modular cell placement system with cell placement crystallization
US6085032A (en) * 1996-06-28 2000-07-04 Lsi Logic Corporation Advanced modular cell placement system with sinusoidal optimization
US5892688A (en) * 1996-06-28 1999-04-06 Lsi Logic Corporation Advanced modular cell placement system with iterative one dimensional preplacement optimization
US6026223A (en) * 1996-06-28 2000-02-15 Scepanovic; Ranko Advanced modular cell placement system with overlap remover with minimal noise
US5914888A (en) * 1996-06-28 1999-06-22 Lsi Logic Corporation Advanced modular cell placement system with coarse overflow remover
US5831863A (en) * 1996-06-28 1998-11-03 Lsi Logic Corporation Advanced modular cell placement system with wire length driven affinity system
US5870312A (en) * 1996-06-28 1999-02-09 Lsi Logic Corporation Advanced modular cell placement system with dispersion-driven levelizing system
US5963455A (en) * 1996-06-28 1999-10-05 Lsi Logic Corporation Advanced modular cell placement system with functional sieve optimization technique
US5870311A (en) * 1996-06-28 1999-02-09 Lsi Logic Corporation Advanced modular cell placement system with fast procedure for finding a levelizing cut point
US5867398A (en) * 1996-06-28 1999-02-02 Lsi Logic Corporation Advanced modular cell placement system with density driven capacity penalty system
US5844811A (en) * 1996-06-28 1998-12-01 Lsi Logic Corporation Advanced modular cell placement system with universal affinity driven discrete placement optimization
US5847965A (en) * 1996-08-02 1998-12-08 Avant| Corporation Method for automatic iterative area placement of module cells in an integrated circuit layout
US6301694B1 (en) * 1996-09-25 2001-10-09 Altera Corporation Hierarchical circuit partitioning using sliding windows
US6317860B1 (en) 1996-10-28 2001-11-13 Altera Corporation Electronic design automation tool for display of design profile
US5828961A (en) * 1997-04-21 1998-10-27 Northern Telecom Limited System and method for partitioning a cellular environment
US6080204A (en) * 1997-10-27 2000-06-27 Altera Corporation Method and apparatus for contemporaneously compiling an electronic circuit design by contemporaneously bipartitioning the electronic circuit design using parallel processing
US6367058B1 (en) 1998-03-26 2002-04-02 Altera Corporation Partitioning using hardware
US7024419B1 (en) * 1999-09-13 2006-04-04 International Business Machines Corp. Network visualization tool utilizing iterative rearrangement of nodes on a grid lattice using gradient method
US6519743B1 (en) * 2000-08-24 2003-02-11 Cadence Design Systems, Inc. Method and system for timing and area driven binary and/or matching
US6836753B1 (en) 2001-06-13 2004-12-28 Cadence Design Systems, Inc. Cone slack allocator for computing time budgets
US7376921B2 (en) * 2006-02-17 2008-05-20 Athena Design Systems, Inc. Methods for tiling integrated circuit designs
US10162892B2 (en) * 2011-02-28 2018-12-25 International Business Machines Corporation Identifying information assets within an enterprise using a semantic graph created using feedback re-enforced search and navigation
WO2013145001A1 (ja) * 2012-03-28 2013-10-03 株式会社日立製作所 情報処理システムおよびグラフ処理方法
US10521809B2 (en) 2015-03-04 2019-12-31 Walmart Apollo, Llc System and method for grouping time series data for forecasting purposes

Also Published As

Publication number Publication date
GB1307261A (en) 1973-02-14
DE2017667A1 (de) 1971-02-04
CA920274A (en) 1973-01-30
US3617714A (en) 1971-11-02
BE748586A (fr) 1970-09-16
FR2043338A5 (xx) 1971-02-12

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