NL7000260A - - Google Patents
Info
- Publication number
- NL7000260A NL7000260A NL7000260A NL7000260A NL7000260A NL 7000260 A NL7000260 A NL 7000260A NL 7000260 A NL7000260 A NL 7000260A NL 7000260 A NL7000260 A NL 7000260A NL 7000260 A NL7000260 A NL 7000260A
- Authority
- NL
- Netherlands
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1608—Error detection by comparing the output signals of redundant hardware
- G06F11/1612—Error detection by comparing the output signals of redundant hardware where the redundant component is persistent storage
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
- G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/16—Digital recording or reproducing using non self-clocking codes, i.e. the clock signals are either recorded in a separate clocking track or in a combination of several information tracks
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Signal Processing (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US79029669A | 1969-01-10 | 1969-01-10 |
Publications (1)
Publication Number | Publication Date |
---|---|
NL7000260A true NL7000260A (fr) | 1970-07-14 |
Family
ID=25150253
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
NL7000260A NL7000260A (fr) | 1969-01-10 | 1970-01-09 |
Country Status (8)
Country | Link |
---|---|
US (1) | US3562726A (fr) |
JP (1) | JPS5026923B1 (fr) |
BE (1) | BE744253A (fr) |
CA (1) | CA938727A (fr) |
DE (1) | DE2000899A1 (fr) |
FR (1) | FR2028112A1 (fr) |
GB (1) | GB1302711A (fr) |
NL (1) | NL7000260A (fr) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3685021A (en) * | 1970-07-16 | 1972-08-15 | Intern Computer Products Inc | Method and apparatus for processing data |
US3683334A (en) * | 1970-11-19 | 1972-08-08 | Ncr Co | Digital recorder |
JPS5019250B1 (fr) * | 1970-12-30 | 1975-07-05 | ||
US4129888A (en) * | 1973-07-02 | 1978-12-12 | General Instrument Corporation | Data recording and/or reproducing system |
US3883891A (en) * | 1974-08-22 | 1975-05-13 | Rca Corp | Redundant signal processing error reduction technique |
US4390975A (en) * | 1978-03-20 | 1983-06-28 | Nl Sperry-Sun, Inc. | Data transmission in a drill string |
JPH0170576U (fr) * | 1987-10-30 | 1989-05-11 | ||
US6963064B2 (en) * | 2002-06-14 | 2005-11-08 | Pem Management, Inc. | Multi-resolution reflective optical incremental encoder |
EP2449335B1 (fr) | 2009-06-30 | 2014-03-19 | Durban AB | Système d'ouverture d'urgence pour portière ou vitre de véhicule |
JP6657131B2 (ja) | 2017-02-17 | 2020-03-04 | 日信工業株式会社 | 車両用ブレーキ液圧制御装置 |
-
1969
- 1969-01-10 US US790296A patent/US3562726A/en not_active Expired - Lifetime
- 1969-12-09 CA CA069413A patent/CA938727A/en not_active Expired
-
1970
- 1970-01-08 JP JP45002325A patent/JPS5026923B1/ja active Pending
- 1970-01-09 DE DE19702000899 patent/DE2000899A1/de active Pending
- 1970-01-09 BE BE744253D patent/BE744253A/fr unknown
- 1970-01-09 NL NL7000260A patent/NL7000260A/xx unknown
- 1970-01-09 FR FR7000702A patent/FR2028112A1/fr not_active Withdrawn
- 1970-01-12 GB GB147770A patent/GB1302711A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
FR2028112A1 (fr) | 1970-10-09 |
GB1302711A (fr) | 1973-01-10 |
JPS5026923B1 (fr) | 1975-09-04 |
US3562726A (en) | 1971-02-09 |
BE744253A (fr) | 1970-06-15 |
DE2000899A1 (de) | 1970-09-03 |
CA938727A (en) | 1973-12-18 |