NL6606453A - - Google Patents

Info

Publication number
NL6606453A
NL6606453A NL6606453A NL6606453A NL6606453A NL 6606453 A NL6606453 A NL 6606453A NL 6606453 A NL6606453 A NL 6606453A NL 6606453 A NL6606453 A NL 6606453A NL 6606453 A NL6606453 A NL 6606453A
Authority
NL
Netherlands
Application number
NL6606453A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of NL6606453A publication Critical patent/NL6606453A/xx

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293Organic, e.g. plastic
    • H01L23/295Organic, e.g. plastic containing a filler
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/18Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/611Combinations of BJTs and one or more of diodes, resistors or capacitors
    • H10D84/613Combinations of vertical BJTs and one or more of diodes, resistors or capacitors
    • H10D84/615Combinations of vertical BJTs and one or more of resistors or capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/043Dual dielectric

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Weting (AREA)
NL6606453A 1965-05-11 1966-05-11 NL6606453A (en:Method)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DES0097037 1965-05-11

Publications (1)

Publication Number Publication Date
NL6606453A true NL6606453A (en:Method) 1966-11-14

Family

ID=7520460

Family Applications (1)

Application Number Title Priority Date Filing Date
NL6606453A NL6606453A (en:Method) 1965-05-11 1966-05-11

Country Status (7)

Country Link
US (1) US3466741A (en:Method)
AT (1) AT262381B (en:Method)
CH (1) CH455052A (en:Method)
DE (1) DE1514460A1 (en:Method)
GB (1) GB1142816A (en:Method)
NL (1) NL6606453A (en:Method)
SE (1) SE315661B (en:Method)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL6714336A (en:Method) * 1967-10-21 1969-04-23
US3947952A (en) * 1970-12-28 1976-04-06 Bell Telephone Laboratories, Incorporated Method of encapsulating beam lead semiconductor devices
US3660732A (en) * 1971-02-08 1972-05-02 Signetics Corp Semiconductor structure with dielectric and air isolation and method
US4587719A (en) * 1983-08-01 1986-05-13 The Board Of Trustees Of The Leland Stanford Junior University Method of fabrication of long arrays using a short substrate
US4815208A (en) * 1987-05-22 1989-03-28 Texas Instruments Incorporated Method of joining substrates for planar electrical interconnections of hybrid circuits
US5874346A (en) * 1996-05-23 1999-02-23 Advanced Micro Devices, Inc. Subtrench conductor formation with large tilt angle implant
US6182342B1 (en) 1999-04-02 2001-02-06 Andersen Laboratories, Inc. Method of encapsulating a saw device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3079254A (en) * 1959-01-26 1963-02-26 George W Crowley Photographic fabrication of semiconductor devices
US3158788A (en) * 1960-08-15 1964-11-24 Fairchild Camera Instr Co Solid-state circuitry having discrete regions of semi-conductor material isolated by an insulating material
US3206647A (en) * 1960-10-31 1965-09-14 Sprague Electric Co Semiconductor unit
DE1188731B (de) * 1961-03-17 1965-03-11 Intermetall Verfahren zum gleichzeitigen Herstellen von mehreren Halbleiteranordnungen
US3300832A (en) * 1963-06-28 1967-01-31 Rca Corp Method of making composite insulatorsemiconductor wafer
US3290753A (en) * 1963-08-19 1966-12-13 Bell Telephone Labor Inc Method of making semiconductor integrated circuit elements
US3307239A (en) * 1964-02-18 1967-03-07 Bell Telephone Labor Inc Method of making integrated semiconductor devices

Also Published As

Publication number Publication date
SE315661B (en:Method) 1969-10-06
DE1514460A1 (de) 1969-05-22
US3466741A (en) 1969-09-16
GB1142816A (en) 1969-02-12
CH455052A (de) 1968-04-30
AT262381B (de) 1968-06-10

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