NL6517226A - - Google Patents

Info

Publication number
NL6517226A
NL6517226A NL6517226A NL6517226A NL6517226A NL 6517226 A NL6517226 A NL 6517226A NL 6517226 A NL6517226 A NL 6517226A NL 6517226 A NL6517226 A NL 6517226A NL 6517226 A NL6517226 A NL 6517226A
Authority
NL
Netherlands
Application number
NL6517226A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of NL6517226A publication Critical patent/NL6517226A/xx

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76294Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/051Etching
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/085Isolated-integrated
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/102Mask alignment
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/977Thinning or removal of substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Pressure Sensors (AREA)
  • Recrystallisation Techniques (AREA)
NL6517226A 1965-01-01 1965-12-31 NL6517226A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB58/65A GB1066911A (en) 1965-01-01 1965-01-01 Semiconductor devices

Publications (1)

Publication Number Publication Date
NL6517226A true NL6517226A (fr) 1966-07-04

Family

ID=9697659

Family Applications (1)

Application Number Title Priority Date Filing Date
NL6517226A NL6517226A (fr) 1965-01-01 1965-12-31

Country Status (4)

Country Link
US (1) US3428499A (fr)
DE (1) DE1514073B2 (fr)
GB (1) GB1066911A (fr)
NL (1) NL6517226A (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1421766A (en) * 1972-03-21 1976-01-21 Ici Ltd Salicylaldoximes and their use in metal extraction processes
GB1520925A (en) * 1975-10-06 1978-08-09 Mullard Ltd Semiconductor device manufacture
US4321747A (en) * 1978-05-30 1982-03-30 Tokyo Shibaura Denki Kabushiki Kaisha Method of manufacturing a solid-state image sensing device
EP0547677A3 (en) * 1991-12-17 1996-10-16 Philips Nv Use of vapor-phase etching in fabrication of semiconductor-on-insulator structure
US5294808A (en) * 1992-10-23 1994-03-15 Cornell Research Foundation, Inc. Pseudomorphic and dislocation free heteroepitaxial structures
US6033489A (en) * 1998-05-29 2000-03-07 Fairchild Semiconductor Corp. Semiconductor substrate and method of making same
WO2003098632A2 (fr) * 2002-05-16 2003-11-27 Nova Research, Inc. Procedes de fabrication de dispositifs de memoire magnetoresistants

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL268294A (fr) * 1960-10-10
DE1258983B (de) * 1961-12-05 1968-01-18 Telefunken Patent Verfahren zum Herstellen einer Halbleiteranordnung mit epitaktischer Schicht und mindestens einem pn-UEbergang
US3320485A (en) * 1964-03-30 1967-05-16 Trw Inc Dielectric isolation for monolithic circuit
US3312879A (en) * 1964-07-29 1967-04-04 North American Aviation Inc Semiconductor structure including opposite conductivity segments
NL133717C (fr) * 1965-06-28 1900-01-01

Also Published As

Publication number Publication date
US3428499A (en) 1969-02-18
DE1514073B2 (de) 1971-01-21
DE1514073A1 (de) 1969-06-12
GB1066911A (en) 1967-04-26

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