Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
  • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
  • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
  • G06F7/50—Adding; Subtracting
  • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
  • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
  • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
  • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
  • G06F7/50—Adding; Subtracting
  • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
  • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
  • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
  • G06F2207/506—Indexing scheme relating to groups G06F7/506 - G06F7/508
  • G06F2207/5063—2-input gates, i.e. only using 2-input logical gates, e.g. binary carry look-ahead, e.g. Kogge-Stone or Ladner-Fischer adder

Landscapes

• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Pure & Applied Mathematics (AREA)
• Mathematical Analysis (AREA)
• Computational Mathematics (AREA)
• Computing Systems (AREA)
• Mathematical Optimization (AREA)
• General Engineering & Computer Science (AREA)
• Complex Calculations (AREA)
• Error Detection And Correction (AREA)
• Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Applications Claiming Priority (1)

Publications (1)

Family

ID=19754800

Family Applications (1)

Country Status (7)

Families Citing this family (1)

• 0
  • NL NL294369D patent/NL294369A/xx unknown
• 1964
  • 1964-06-16 DE DEN25122A patent/DE1194606B/de active Pending
  • 1964-06-17 CH CH787664A patent/CH424323A/de unknown
  • 1964-06-17 AT AT518064A patent/AT248743B/de active
  • 1964-06-17 GB GB2507064A patent/GB1040778A/en not_active Expired
  • 1964-06-17 SE SE744164A patent/SE306188B/xx unknown
  • 1964-06-19 BE BE649532A patent/BE649532A/xx unknown

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