AT248743B - In Abschnitte unterteilter, binär rechnender Addierer - Google Patents

In Abschnitte unterteilter, binär rechnender Addierer

Info

Publication number
AT248743B
AT248743B AT518064A AT518064A AT248743B AT 248743 B AT248743 B AT 248743B AT 518064 A AT518064 A AT 518064A AT 518064 A AT518064 A AT 518064A AT 248743 B AT248743 B AT 248743B
Authority
AT
Austria
Prior art keywords
sections
binary calculating
adder divided
calculating adder
divided
Prior art date
Application number
AT518064A
Other languages
English (en)
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Application granted granted Critical
Publication of AT248743B publication Critical patent/AT248743B/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/506—Indexing scheme relating to groups G06F7/506 - G06F7/508
    • G06F2207/5063—2-input gates, i.e. only using 2-input logical gates, e.g. binary carry look-ahead, e.g. Kogge-Stone or Ladner-Fischer adder

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Error Detection And Correction (AREA)
  • Complex Calculations (AREA)
AT518064A 1963-06-20 1964-06-17 In Abschnitte unterteilter, binär rechnender Addierer AT248743B (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL294369 1963-06-20

Publications (1)

Publication Number Publication Date
AT248743B true AT248743B (de) 1966-08-10

Family

ID=19754800

Family Applications (1)

Application Number Title Priority Date Filing Date
AT518064A AT248743B (de) 1963-06-20 1964-06-17 In Abschnitte unterteilter, binär rechnender Addierer

Country Status (7)

Country Link
AT (1) AT248743B (de)
BE (1) BE649532A (de)
CH (1) CH424323A (de)
DE (1) DE1194606B (de)
GB (1) GB1040778A (de)
NL (1) NL294369A (de)
SE (1) SE306188B (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6149233A (ja) * 1984-08-17 1986-03-11 Nec Corp 高速デジタル加減算回路

Also Published As

Publication number Publication date
DE1194606B (de) 1965-06-10
CH424323A (de) 1966-11-15
BE649532A (de) 1964-12-21
GB1040778A (en) 1966-09-01
SE306188B (de) 1968-11-18
NL294369A (de)

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