NL213922A - - Google Patents

Info

Publication number
NL213922A
NL213922A NL213922DA NL213922A NL 213922 A NL213922 A NL 213922A NL 213922D A NL213922D A NL 213922DA NL 213922 A NL213922 A NL 213922A
Authority
NL
Netherlands
Application number
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Publication of NL213922A publication Critical patent/NL213922A/xx

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50Adding; Subtracting
    • G06F7/505Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50Adding; Subtracting
    • G06F7/501Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/5016Half or full adders, i.e. basic adder cells for one denomination forming at least one of the output signals directly from the minterms of the input signals, i.e. with a minimum number of gate levels

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
NL213922D 1957-01-22 NL213922A (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL213922A NL103751C (de) 1957-01-22 1957-01-22
NL224679A NL113236C (de) 1957-01-22 1958-02-05

Publications (1)

Publication Number Publication Date
NL213922A true NL213922A (de)

Family

ID=26641616

Family Applications (4)

Application Number Title Priority Date Filing Date
NL224679D NL224679A (de) 1957-01-22
NL213922D NL213922A (de) 1957-01-22
NL213922A NL103751C (de) 1957-01-22 1957-01-22
NL224679A NL113236C (de) 1957-01-22 1958-02-05

Family Applications Before (1)

Application Number Title Priority Date Filing Date
NL224679D NL224679A (de) 1957-01-22

Family Applications After (2)

Application Number Title Priority Date Filing Date
NL213922A NL103751C (de) 1957-01-22 1957-01-22
NL224679A NL113236C (de) 1957-01-22 1958-02-05

Country Status (7)

Country Link
US (1) US3056551A (de)
CH (2) CH365235A (de)
DE (2) DE1096649B (de)
FR (2) FR1193001A (de)
GB (2) GB876989A (de)
NL (4) NL103751C (de)
OA (1) OA00798A (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1184125B (de) * 1961-11-17 1964-12-23 Telefunken Patent Zweistufiges Rechenwerk
DE2007353C3 (de) * 1970-02-18 1973-11-29 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Vierteiliges Addierwerk
US4737926A (en) * 1986-01-21 1988-04-12 Intel Corporation Optimally partitioned regenerative carry lookahead adder

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2719670A (en) * 1949-10-18 1955-10-04 Jacobs Electrical and electronic digital computers
US2803401A (en) * 1950-10-10 1957-08-20 Hughes Aircraft Co Arithmetic units for digital computers
US2819839A (en) * 1951-02-23 1958-01-14 Donald H Jacobs High speed register using gating circuits to bypass delay elements
GB750817A (en) * 1953-10-19 1956-06-20 Powers Samas Account Mach Ltd Improvements in or relating to electronic adding circuits
US2954168A (en) * 1955-11-21 1960-09-27 Philco Corp Parallel binary adder-subtracter circuits
US2879001A (en) * 1956-09-10 1959-03-24 Weinberger Arnold High-speed binary adder having simultaneous carry generation

Also Published As

Publication number Publication date
FR1193001A (fr) 1959-10-29
GB879159A (en) 1961-10-04
OA00798A (fr) 1967-11-15
NL103751C (de) 1962-05-15
FR74905E (fr) 1961-03-03
US3056551A (en) 1962-10-02
CH374841A (de) 1964-01-31
NL113236C (de) 1965-12-15
GB876989A (en) 1961-09-06
DE1096649B (de) 1961-01-05
NL224679A (de)
CH365235A (de) 1962-10-31
DE1123144B (de) 1962-02-01

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