Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
  • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
  • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
  • G06F7/50—Adding; Subtracting
  • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
  • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
  • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
  • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
  • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
  • G06F7/50—Adding; Subtracting
  • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
  • G06F7/5016—Half or full adders, i.e. basic adder cells for one denomination forming at least one of the output signals directly from the minterms of the input signals, i.e. with a minimum number of gate levels

Landscapes

• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Computational Mathematics (AREA)
• Mathematical Analysis (AREA)
• Pure & Applied Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Computing Systems (AREA)
• Mathematical Optimization (AREA)
• General Engineering & Computer Science (AREA)
• Complex Calculations (AREA)
• Management, Administration, Business Operations System, And Electronic Commerce (AREA)

Applications Claiming Priority (2)

Publications (1)

Family

ID=26641616

Family Applications (4)

Family Applications After (3)

Country Status (7)

Families Citing this family (4)

Family Cites Families (6)

• 0
  • NL NL213922D patent/NL213922A/xx unknown
  • NL NL224679D patent/NL224679A/xx unknown
• 1957
  • 1957-01-22 NL NL213922A patent/NL103751C/xx active
• 1958
  • 1958-01-11 DE DEN14550A patent/DE1096649B/de active Pending
  • 1958-01-14 US US708917A patent/US3056551A/en not_active Expired - Lifetime
  • 1958-01-20 CH CH5486558A patent/CH365235A/de unknown
  • 1958-01-22 GB GB2197/58A patent/GB876989A/en not_active Expired
  • 1958-01-22 FR FR1193001D patent/FR1193001A/fr not_active Expired
  • 1958-02-05 NL NL224679A patent/NL113236C/xx active
• 1959
  • 1959-02-02 GB GB3592/59A patent/GB879159A/en not_active Expired
  • 1959-02-02 CH CH6901559A patent/CH374841A/de unknown
  • 1959-02-04 FR FR785754A patent/FR74905E/fr not_active Expired
  • 1959-10-31 DE DEN16195A patent/DE1123144B/de active Pending
• 1964
  • 1964-12-16 OA OA50889A patent/OA00798A/xx unknown

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