NL2027146B1 - A radiofrequency power package and device with improved ESD performance - Google Patents
A radiofrequency power package and device with improved ESD performance Download PDFInfo
- Publication number
- NL2027146B1 NL2027146B1 NL2027146A NL2027146A NL2027146B1 NL 2027146 B1 NL2027146 B1 NL 2027146B1 NL 2027146 A NL2027146 A NL 2027146A NL 2027146 A NL2027146 A NL 2027146A NL 2027146 B1 NL2027146 B1 NL 2027146B1
- Authority
- NL
- Netherlands
- Prior art keywords
- esd
- terminal
- package
- contact
- power package
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/52—Circuit arrangements for protecting such amplifiers
- H03F1/523—Circuit arrangements for protecting such amplifiers for amplifiers using field-effect devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
- H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/195—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
- H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48111—Disposition the wire connector extending above another semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
- H01L23/047—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
Abstract
The present invention relates to a radiofrequency, ‘RF’, power package. More in particular, the present invention relates to an RF power package in which an ESD device is arranged inside the package body or housing. The present invention further relates to an RF power device comprising such an RF power package. According to the present invention, an ESD device is provided inside the package and is arranged on a terminal of the RF power package. In this manner, the ESD sensitive contact of the amplifying circuit inside the RF power package can be better protected against ESD damage even 10 during mounting of the RF power package.
Description
A radiofrequency power package and device with improved ESD performance The present invention relates to a radiofrequency, ‘RF’, power package. More in particular, the present invention relates to an RF power package in which an ESD device is arranged inside the package body or housing. The present invention further relates to an RF power device comprising such an RF power package.
RF power packages are known in the art. These packages are configured to deliver power at levels in the range between IW and 5kW at frequencies from 100 kHz up to 40 GHz. These packages comprise a plurality of terminals through which electrical signals are inputted or outputted and through which power or ground is supplied.
The RF power package is mounted on a printed circuit board, ‘PCB’. Such board is part of a larger RF power device. Such device comprises electrical contacts that are accessible from outside of the device. These contacts may be exposed to electrostatic discharge events. As a result of these discharge events, the components of the RF power device, such as the RF power package, may become damaged.
The performance of a device under high electrostatic voltage stress can be determined using a model such as the charge device model or the human body model. Using the human body model, an electrostatic discharge, ‘ESD’, is simulated that may occur when a human touches the device. For example, according to the JEDEC JS-001 standard, the human body is modelled by a 100 pF capacitor and a 1500 Ohm discharging resistor. During testing, the capacitor is charged up to a discharge voltage, e.g. 2 kV, and is then discharged through the discharging resistor that is arranged in series with a terminal of the device under test.
Typically, a device should meet certain ESD requirements with respect to the discharge voltage levels it should be able to withstand without breaking down due to ESD related damage.
The ESD performance of any device is mostly determined by the electronic circuitry that is arranged inside. An RF power package comprises amplifying circuitry, such as a field-effect transistor, ‘FET’, as well as passive circuitry used for impedance matching and/or biasing. Each of these components may be prone to ESD damage.
Recently, Gallium Nitride, GaN’, has emerged as a promising material for realizing RF power amplifying devices. In these devices, a GaN based power FET is used that comprises a gate, source, and drain contact. The gate contact is formed by a Schottky contact that has a low leakage current under reverse bias.
The relatively low leakage current under reverse bias makes the GaN FET susceptible for ESD related damage. For example, if a HBM test is performed by applying a positive voltage at the source contact or the drain contact with the gate contact being grounded, only a small percentage of the discharging voltage will fall over the discharging resistor as the reverse biased Schottky diode effectively presents a high series resistance. Consequently, excessive voltages may be present at the source of drain contact and the GaN FET may break down.
RF power packages are known in the art. An exemplary RF power package comprises a package body or housing, and an electrically conductive substrate at least partially arranged in the package body or housing. This RF power package further comprises a semiconductor die mounted on the conductive substrate and arranged in the package body or housing, wherein the semiconductor die comprises an amplifying circuit having an ESD sensitive contact for inputting or outputting electrical signals. The RF power package additionally comprises a plurality of terminals that are physically separated from the conductive substrate and that each comprise a first terminal surface provided outside of the package body or housing, and a second terminal surface provided inside the package body or housing, wherein a terminal among the plurality of terminals constitutes an RF terminal that is configured for inputting a signal to be amplified by the amplifying circuit or for outputting a signal amplified by the amplifying circuit. The RF terminal is electrically connected to the ESD sensitive contact of the amplifying circuit using an RF terminal connection.
The known RF power package is configured to be mounted on a PCB. On the PCB, ESD devices are generally arranged to provide the required ESD protection. These devices typically comprise a first and second ESD contact. During operation, one of the first ESD contact and second ESD contact is grounded whereas the other of the first ESD contact and second ESD contact is connected, either directly or through other components, to the terminal of the RF power package that requires ESD protection. The ESD device prevents or limits any ESD pulses associated with an electrical discharge from reaching the ESD sensitive contact(s).
The ESD device may comprise a plurality of diodes, transistors, or silicon controlled rectifiers arranged in between the first ESD contact and second ESD contact. For example, one or more diodes can be arranged with their anode connected to the first ESD contact and their cathode to the second ESD contact, whereas one or more other diodes can be arranged with their anode connected to the second ESD contact and their cathode to the first ESD contact. In this manner, a low ohmic discharging path can be provided for positive and negative voltages occurring at the terminal to be protected. By providing a low ohmic discharging path, most of the discharge current will flow through the ESD device thereby protecting the device or component having the ESD sensitive contact(s).
The Applicant has found that the process of mounting the known RF power package may lead to fails. The Applicant further found that these fails can be attributed to ESD damage that occurred during the mounting of the known RF power package.
It is an object of the present invention to provide an RF power package that can be mounted or handled without risking ESD damage or at least to a lesser extent.
According to the present invention, this object is achieved using the RF power package as defined in claim | and that is characterized in that the RF power package further comprises an ESD device for protecting the amplifying circuit against damage caused by an electrostatic discharge. The ESD device comprises a first ESD contact and a second ESD contact. Furthermore, a terminal among the plurality of terminals constitutes a mounting, ‘MNT’, terminal on which the ESD device is mounted. The first ESD contact is electrically connected, using a first ESD connection, either directly to the ESD sensitive contact of the amplifying circuit or indirectly through at least a part of the RF terminal connection, and the second ESD contact is, at least during use, electrically grounded.
According to the present invention, the ESD device is provided inside the package and is arranged on a terminal of the RF power package. In this manner, the ESD sensitive contact of the amplifying circuit can be better protected against ESD damage even during mounting of the RF power package.
The conductive substrate can be configured to be electrically connected to ground at least during use. Additionally or alternatively, a terminal among the plurality of terminals may constitute a ground, ‘GND’, terminal, that, during use, is electrically grounded. Such GND terminal is preferably arranged adjacent to the MNT terminal. The second ESD contact of the ESD device may be electrically connected to a GND terminal or to the conductive substrate using a second ESD connection.
The first ESD connection may comprise a common part that is shared with the RF terminal connection and an individual part extending between an end of the common part and the first ESD contact. An impedance looking towards the ESD device at the end of the common part is preferably considerably higher than an impedance seen at the end of the common part looking away from the amplifying circuit. In this manner, the ESD device does not significantly affect the RF performance of the RF power package. This particularly holds if the impedance is assessed at the operating frequency of the RF power package, which typically lies in the range between 100 kHz and 40 GHz.
The amplifying circuit may comprise a field-effect transistor, ‘FET’, for example a gallium nitride based FET or silicon based laterally diffused metal oxide semiconductor, ‘LDMOS’, transistor. In this case, the ESD sensitive contact of the amplifying circuit is electrically connected to or formed by a gate or drain of the FET. Additionally or alternatively, the ESD sensitive contact of the amplifying circuit can be a bondpad or bondbar that is electrically connected to the drain or gate of the FET. Moreover, the RF terminal connection may comprise an RF bondwire that has one end bonded to the bondpad or bondbar. Another end of the RF bondwire may be bonded to the RF terminal. Alternatively, the RF terminal connection may comprise an impedance matching network that incorporates the RF bondwire. Such impedance matching network may comprise a shunt capacitance having a non-grounded terminal and a grounded terminal configured to be electrically grounded at least during use.
In this case, the another end of the RF bondwire can be bonded to the non-grounded terminal of the shunt capacitor, and the RF terminal connection may comprise a further RF bondwire between the non-grounded terminal of the shunt capacitor and the RF terminal.
An impedance matching network is typically used at the input, i.e. gate, of the amplifying circuit.
However, impedance matching network may also be used at the output, i.e. drain, of the amplifying circuit.
The ESD device may comprise an ESD semiconductor die on which ESD circuitry is integrated and that comprises a semiconductor substrate with a back surface with which the ESD semiconductor die is fixedly connected to the second surface of the MNT terminal.
The first and second ESD contacts can be arranged on a front surface of the ESD semiconductor die opposite to the back surface of the semiconductor substrate.
Moreover, the first ESD connection may comprise a bondwire electrically connecting the RF terminal connection to the first ESD contact, and the second ESD connection may comprise a bondwire electrically connecting the second ESD contact to a GND terminal or the conductive substrate.
The bondwire of the first ESD connection may extend between the RF terminal and the first ESD contact or between the ESD sensitive contact and the first ESD contact.
Additionally, a terminal among the plurality of terminals may constitute a non-connected, ‘NC’, terminal.
In this case, the MNT terminal can be a GND terminal, the RF terminal, or a NC terminal.
Within the context of the present invention, a NC terminal is a terminal that is not electrically connected to the electronic circuitry on the PCB on which the RF power package is mounted.
Typically, the voltage at a NC terminal is floating during operation.
Alternatively, the ESD device may comprise an ESD semiconductor die on which ESD circuitry is integrated and that comprises an electrically conductive semiconductor substrate with a back surface with which the ESD semiconductor die is fixedly connected to the second surface of the MNT terminal.
In this case, the back surface forms the first ESD contact and the second ESD contact is arranged on a front surface of the ESD semiconductor die opposite to the back surface of the semiconductor substrate.
The second ESD connection may comprise a bondwire that electrically connects the second ESD contact to a GND terminal or the conductive substrate.
Furthermore, the MNT terminal can be the RF terminal.
Alternatively, a terminal among the plurality of terminals may constitute a non-connected, ‘NC’, terminal.
In this latter case, the MNT terminal can be a NC terminal and the first ESD connection may comprise a bondwire electrically connecting the MNT terminal to the RF terminal connection.
In this latter case, the bondwire of the first ESD connection may extend between the RF terminal and the MNT terminal or between the ESD sensitive contact and the MNT terminal.
Alternatively, the ESD device may comprise an ESD semiconductor die on which ESD circuitry is integrated and that comprises an electrically conductive semiconductor substrate with a back surface with which the ESD semiconductor die is fixedly connected to the second surface of the MINT terminal. In this case, the back surface forms the second ESD contact, and the first ESD contact is arranged on a front surface of the ESD semiconductor die opposite to the back surface of the semiconductor substrate. The first ESD connection may comprise a bondwire electrically 5 connecting the first ESD contact to the RF terminal connection. In this case, the bondwire of the first ESD connection may extend between the RF terminal and the first ESD contact or between the ESD sensitive contact and the first ESD contact. Furthermore, the MNT terminal can be a GND terminal, or a terminal among the plurality of terminals constitutes a non-connected, ‘NC’, terminal. In this latter case, the MNT terminal may be a NC terminal and the second ESD I0 connection may comprise a bondwire electrically connecting the MNT terminal to a GND terminal or to the conductive substrate.
The conductive substrate may comprise a substantially rectangular base spaced apart in a first direction from the MNT terminal, and a protrusion that is integrally connected to the substantially rectangular base and that extends in the first direction such that an end of the {5 protrusion is arranged spaced apart from MNT terminal in a second direction that is perpendicular to the first direction. A substantially rectangular base may be identical to a rectangular base apart from the substantially rectangular base having rounded or chamfered corners. In so far the second ESD connection comprises a bondwire that is connected to the conductive substrate, that bondwire is connected to the conductive substrate protrusion, and preferably extends parallel to the second direction. In this embodiment, the conductive substrate has a different shaped than the common rectangular form for allowing the ESD device to be grounded. Moreover, as the bondwires that extend from the output of the amplifying circuit, e.g. drain, typically extend in the first direction toward the RF terminal, there is little to no electromagnetic coupling between the bondwire of the second ESD connection and such bondwires. Similar considerations hold when using the ESD device to protect the input of the amplifying circuit.
The RF power package may be a flat no-leads package, such as a QFN or DFN package. In this case, each of the plurality of terminals may correspond to a respective land of the flat no-lead package. Alternatively, the RF power package may be a molded leadframe package or a non- molded leadframe package such as a ceramic leadframe package, wherein each of the plurality of terminals corresponds to a respective lead of the molded or non-molded leadframe package. For the package types mentioned above, the conductive substrate is exposed on a backside of the package. In this manner, efficient cooling and/or electrical grounding can be obtained.
In case of a molded leadframe package, the leads were part of a leadframe prior to separating the RF power package from the leadframe. In this case, the conductive substrate was physically and electrically connected to the leadframe using a plurality of spaced apart connecting members prior to separating the package from the leadframe, and wherein during the separating of the package from the leadframe each connecting member was divided, for example by means of cutting, punching or pushing, into a first connecting member part that remained connected to the conductive substrate and a second connecting member part that remained connected to the leadframe. The RF power package may further comprise a frame part that physically connects to and extends from at least one first connecting member part, wherein the ESD device is mounted on the frame part. Furthermore, the frame part may extend between a pair of first connecting member parts. More in particular, the frame part and the first connecting member part(s) can be integrally formed. The ESD device may configured similarly to the ESD semiconductor dies described above, i.e. it may have a first and second ESD contact on top of the semiconductor die or one of those contacts arranged on a backside of the semiconductor substrate of the ESD semiconductor die.
According to a second aspect, the present invention provides an RF power device that comprises a printed circuit board comprising a plurality of pads, and the abovementioned RF power package. The RF power package is mounted to the printed circuit board such that each terminal of the RF power package is fixedly connected, e.g. by means of soldering, to a respective pad among the plurality of pads. The printed circuit board may comprise a separate pad or a coin integrated in the printed circuit board that is fixedly connected, e.g. by means of soldering, to the conductive substrate of the RF power package.
Next, the present invention will be described referring to the appended drawings, wherein identical reference signs will be used to refer to identical or similar components, and wherein: Figures 1-7 illustrate schematic top views of various embodiments of an RF power package in accordance with the present invention; Figure 8 illustrates a perspective view of a molded package in accordance with the present invention; Figure 9 illustrates a cross sectional view of the molded package of figure 8; and Figure 10 illustrates an example of an RF power device in accordance with the present invention.
Figure 1A illastrates an embodiment of an RF power package 1A in accordance with the present invention. Package 1A is DEN type package comprising a conductive substrate in the form of a die pad 10 on which a semiconductor die 30 is mounted. An RF power FET is integrated on semiconductor die 10. Figure 1A only illustrates a bondbar 31 that is connected to the gate of the power FET and a bondbar 32 that is connected to the drain of the power FET. The source of the power FET is not illustrated but this contact is connected to ground through vias in the semiconductor substrate of semiconductor die 30 or by means of the semiconductor substrate being conductive. Here, it is noted that when RF power package 1A is mounted on a PCB, grounding of the RF power FET is achieved through die pad 10 which is fixedly mounted to a ground pad on or a coin in the PCB. At the same time, thermal cooling of RF power FET is also achieved through die pad 10. As shown, RF power package | A comprises two additional semiconductor dies. A first semiconductor die 40 is arranged in between input terminal RF] and gate bondbar 31.
Semiconductor die 40 comprises an integrated capacitor of which a first terminal is connected to a bondbar 41. A second terminal of this capacitor is connected to ground. This can be achieved by means of vias in semiconductor die 40 or by means of the semiconductor substrate of semiconductor die 40 being conductive. Grounding is further achieved through die pad 10 on which semiconductor die 40 is mounted.
A plurality of bondwires B6 extends between input terminal RF1 and the non-grounded terminal of the capacitor on semiconductor die 40. Another plurality of bondwires B5 extends between the non-grounded terminal of the capacitor and gate bondbar 31. In this manner, an LC type of impedance matching network is realized.
A further semiconductor die 50 is arranged between semiconductor die 30 and output terminal RF2. Also this die comprises a capacitor having one terminal that is connected to a bondbar 51. The other terminal is connected to ground in a similar manner as the capacitor on semiconductor die 40.
A plurality of bondwires B3 extends between drain bondbar 32 and output terminal RF2. These bondwires form an RF terminal connection between the drain contact and output terminal RF2. A further plurality of bondwires B4 extends between drain bondbar 32 and the non-grounded terminal of the capacitor on semiconductor die 50. In this manner a shunt LC series network is formed that is connected to drain bondbar 32.
The RE power FET on semiconductor die 30 comprises an output capacitance. For large devices, the output capacitance may have a deteriorating effect on the RF performance of the FET.
To prevent such deterioration, the shunt LC network is configured to act as a shunt inductance that resonates with the output capacitance at a frequency identical or close to the operating frequency of the RF power package. The series capacitance of the shunt LC series network prevents a DC path to ground.
Figure 1 illustrates additional terminals 20. Ground terminals GND are provided that are connected to ground when package 1A is mounted to the PCB. Non-connected terminals NC are not electrically connected to the circuitry on the PCB. These terminals may be connected to pads on the PCB, e.g. by means of soldering, but these pads are not connected to other electronic circuitry and may have a floating or otherwise non-defined potential during operation.
In figure 1, an ESD device in the form of an ESD semiconductor die 60 is mounted on a non-connected terminal NC. The terminal on which ESD semiconductor die 60 is also referred to as mounting terminal MNT. ESD semiconductor die 60 comprises a first ESD contact in the form of a first bondpad 61 and a second ESD contact in the form of a second bondpad 62. Output terminal RF2 is connected to first bondpad 61 using a first ESD connection in the form of a bondwire B1. Second bondpad 62 is connected to conductive substrate 10 using a second ESD connection in the form of a bondwire B2.
In figure 1, ESD semiconductor die 60 is configured to protect RF power FET against ESD related damage as a consequence of an electrostatic discharge that occurs at output terminal RF2 and that reaches the drain contact of the power FET. In this case, the drain of the power FET is considered to be the ESD sensitive contact. As shown in figure 1, the first ESD contact is indirectly electrically connected to this ESD sensitive contact, using the first ESD connection, through at least a part of the RF terminal connection formed by bondwires B3. The second ESD contact is grounded via bondwires B2 and through conductive substrate 10.
The connection between the first ESD contact and the ESD sensitive contact can also be a direct connection. An example thereof is shown in figure 2. In this case, semiconductor die 60 has a conductive semiconductor substrate. The first ESD contact has the form of a first bondpad 61 arranged on a top side of semiconductor die 60 whereas the second ESD contact is formed by a conductive metal arranged on the backside of the semiconductor substrate of semiconductor die 60.
The first ESD connection again comprises a bondwire Bl. However, bondwire Bl now extends directly between drain bondbar 32 and first bondpad 61. The second ESD contact is grounded via grounded terminal GND.
In figure 3, an ESD semiconductor die 70 is also provided to protect the RF power FET against ESD related damage as a consequence of an electrostatic discharge that occurs at input terminal RF1 and that reaches the gate contact of the RF power FET. In this case, the gate of the power FET is considered {o be the ESD sensitive contact. Similar to ESD semiconductor die 60, ESD semiconductor die 70 comprises a first ESD contact in the form of a first bondpad 71 and a second ESD contact in the form of a second bondpad 72. First bondpad 71 is connected using a bondwire B7 to input terminal RF1. Second bondpad 72 is grounded via bondwire B8 that is connected to the conductive substrate 10.
Figures 4-6 illustrate further embodiments of a DEN type RF power package in accordance with the present invention. These embodiments differ in a) whether the ESD semiconductor die comprises the first and second ESD contact on a top surface thereof or whether one of these contacts is arranged on a backside of the conductive semiconductor substrate of the ESD semiconductor die, and b) the mounting terminal MNT on which the ESD semiconductor die is mounted.
first ESD contact | second ESD contact The skilled person will readily understand that the ESD protective measures illustrated in figures 4-6 could additionally or alternatively be realized at the input for protecting the gate of the RF power FET.
Figure 7 illustrates an embodiment of an RF power package IG in which conductive substrate 10 comprises a protrusion 12 that extends along a first direction D1 away from an essentially rectangular base 11. Protrusion 12 and base 11 are integrally connected. In this embodiment, the second ESD connection comprises a bondwire B2 that connects second bondpad 62 to protrusion 12 for grounding. As shown, bondwire B2 extends along a second direction D2 perpendicular to first direction D1. The first ESD contact is realized on a backside of the conductive semiconductor substrate of ESD semiconductor die 60.
In the figure 7 embodiment, electromagnetic coupling between bondwire B2 and any of the bondwires B3 and B4 is minimized due to the mutual orthogonal arrangements of these wires.
Such electromagnetic coupling could result in the loss of RF signal thereby lowering efficiency of the package.
In figures 1-7, several embodiments are shown with different configurations of the ESD semiconductor die(s). The skilled person will readily understand that other configurations are equally possible within the context of the present invention. Furthermore, in figures 1-7, the molding compound has been omitted. In flat no-leads packages, such as DEN or QFN packages, a molding compound covers conductive substrate 10, terminals 20, and semiconductor dies 30, 40, 50, 60, 70 in a manner known in the art. Figure 8 illustrates a molded leadframe package 100. This type of package is realized by first connecting a leadframe that comprises a plurality of leads 20 to conductive heat sink 10 using connecting members that protrude from the leadframe. These connecting members are riveted to heat sink 10 using rivets 103. The combination of leadframe and heat sink 10 is thereafter arranged in a mold for applying the molding compound. Once solidified, the molding compound provides a mutual fixation between heat sink 10 and leads 20 meaning that when package 100 is separated from the leadframe and the connecting members are severed, heat sink 10 and leads 20 remain mutually fixed.
Figure 8 illustrates package 100 after separation from the leadframe and without the molding compound. As a result of separating package 100 from the leadframe, the connecting members provided at the corners of heat sink 10 have each been divided into a first connecting member part 102 that remained connected to heat sink 10 and a second connecting member part {not shown) that remained connected to the leadframe. Package 100 comprises, on both sides of heat sink 10, a frame part 101 that is integrally connected to first connecting member parts 102. Frame part 101 comprises openings 104 for stress relief purposes. Similar openings 105 may be provided in output lead RF2 that is spaced apart by a distance 101A from first connecting member part 102 and frame part 101.
In package 100, ESD semiconductor die 60 is arranged on top of frame part 101. To attach semiconductor die 30 to heat sink 10, an adhesive is used that is at least partially liquid at the IO moment of attaching semiconductor die 30. Consequently, part of the adhesive may flow out to other areas on heat sink 10. For small-sized packages, the area between adjacently arranged dies on heat sink 10 should be minimized as much as possible. However, when the dies are too close, a risk exists in that the adhesive from one die flows to the other die. There, it may cause an inadvertent short with a contact at the topside of the die. In figure 8, as frame part 101 is at an elevated position relative to semiconductor die 30, there is less risk of such liquid adhesive causing inadvertent shorts between the first ESD contact of ESD semiconductor die 60 and ground.
Figure 8 further illustrates a large output lead RF2 and multiple smaller input leads 20 of which one lead RF1 is connected, either directly or indirectly, to the gate of the RF power FET. It should be noted that additional leads may be provided at the input or output.
In figure 8, a single die 30 is shown having a drain bondbar 32 and an input bondpad 31 that are connected to a respective lead. It should be noted that input bondpad 31 could be connected directly to a gate of the RF power FET that is arranged on semiconductor die 30 or via an impedance matching network. Similarly, additional circuitry may be provided on die 30 or on other dies in package 100 (not shown) at the input and at the output.
Figure 9 illustrates a cross sectional view of package 100 of figure 8 along line C-C. As shown, package 100 is provided with a cover 108 that comprises a cover base 108A and cover sidewalls 108B that extend from cover base 108A. The applied molding compound forms a package body 110 that comprises a lower part | 10B mutually fixating leads 20, RF1, RF2 and heat sink 10, and an upper part 110A. Leads 20, RF1, RF2 protrude through package body 110. Inside the package, bondwires are bonded to an exposed surface of leads 20, RF1, RF2, An adhesive 111 is arranged between upper part 110A and cover sidewalls 108B for fixedly attaching cover 108 to package body 110. In this manner, an air cavity 109 is formed inside package 100. This type of package is therefore known as an air-cavity molded package. It should be noted that cover 108 may be realized using the same molding compound as package body 110.
In other embodiments, cover 108 is formed at the same time as providing the molding compound for realizing package body 110. In these packages, no air cavity is present and all necessary electrical connections need to be realized before applying the molding compound. Compared to these fully molded packages, air-cavity molded packages offer superior RF performance due to the absence of losses in the molding compound that would otherwise surround the electrical components such as bondwires.
Figure 10 illustrates an example of an RF power device 200 in accordance with the present invention. Device 200 comprises an RF power package, such as package 1A of figure 1A, that is mounted on a PCB 201. PCB 201 is typically a multilayer board allowing metal traces on several different layers.
PCB 201 comprises pads 202A, 202B on which leads 20 and conductive substrate 10) are fixedly mounted, e.g. using soldering. As shown, leads RF1 and RF2 are connected to metal traces 203 {only partially shown) on PCB 201. Non-connected leads NC are connected to a pad 202A but these pads are not connected to further electronic circuitry on PCB 201. Ground leads GND are connected to a ground layer of PCB 201 using vias 204. It should be clear to the skilled person that many more configurations are possible for RF power device 200, for example for accommodating different types of packages such as the molded packages shown in figures 8 and 9. In the above, the present invention has been explained using detailed embodiments thereof. It should be noted however that various modifications are possible without deviating from the scope of the invention which is defined by the appended claims. For example, instead of providing protection against damage occurring due to discharges reaching the gate or drain of an RF power FET, ESD protection in the form described above may equally be provided for protecting other contacts of circuitry inside the package. Also in these embodiments, the ESD semiconductor die would be arranged on a terminal. Similarly, the Applicant realized that the inventive concept described above could also be applied for other types of packages not being an RF power package but still having a package body or housing, conductive substrate, a plurality of terminals and a semiconductor die mounted on the conductive substrate. An example of such package could be an electronic package in which the semiconductor die comprises electronic circuitry having one or more ESD sensitive contacts.
Claims (23)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL2027146A NL2027146B1 (en) | 2020-12-17 | 2020-12-17 | A radiofrequency power package and device with improved ESD performance |
CN202111551972.6A CN114649317A (en) | 2020-12-17 | 2021-12-17 | Radio frequency power package and radio frequency power device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL2027146A NL2027146B1 (en) | 2020-12-17 | 2020-12-17 | A radiofrequency power package and device with improved ESD performance |
Publications (1)
Publication Number | Publication Date |
---|---|
NL2027146B1 true NL2027146B1 (en) | 2022-07-11 |
Family
ID=75439394
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
NL2027146A NL2027146B1 (en) | 2020-12-17 | 2020-12-17 | A radiofrequency power package and device with improved ESD performance |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN114649317A (en) |
NL (1) | NL2027146B1 (en) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2226700A (en) * | 1988-12-27 | 1990-07-04 | Rohm Co Ltd | Resin encapsulated diodes |
US20190123553A1 (en) * | 2016-10-07 | 2019-04-25 | Murata Manufacturing Co., Ltd. | Filter having an esd protection device |
US20190214335A1 (en) * | 2018-01-09 | 2019-07-11 | Macom Technology Solutions Holdings, Inc. | Intra-package interference isolation |
US20200235062A1 (en) * | 2017-03-28 | 2020-07-23 | Mitsubishi Electric Corporation | Semiconductor device |
US20200381424A1 (en) * | 2019-06-03 | 2020-12-03 | Texas Instruments Incorporated | Monolithic multi-channel diode array |
-
2020
- 2020-12-17 NL NL2027146A patent/NL2027146B1/en active
-
2021
- 2021-12-17 CN CN202111551972.6A patent/CN114649317A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2226700A (en) * | 1988-12-27 | 1990-07-04 | Rohm Co Ltd | Resin encapsulated diodes |
US20190123553A1 (en) * | 2016-10-07 | 2019-04-25 | Murata Manufacturing Co., Ltd. | Filter having an esd protection device |
US20200235062A1 (en) * | 2017-03-28 | 2020-07-23 | Mitsubishi Electric Corporation | Semiconductor device |
US20190214335A1 (en) * | 2018-01-09 | 2019-07-11 | Macom Technology Solutions Holdings, Inc. | Intra-package interference isolation |
US20200381424A1 (en) * | 2019-06-03 | 2020-12-03 | Texas Instruments Incorporated | Monolithic multi-channel diode array |
Also Published As
Publication number | Publication date |
---|---|
CN114649317A (en) | 2022-06-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9159720B2 (en) | Semiconductor module with a semiconductor chip and a passive component and method for producing the same | |
US20080180871A1 (en) | Structure and method for self protection of power device | |
TWI798670B (en) | Stacked rf circuit topology | |
EP2879174B1 (en) | Packaged RF power transistor device having next to each other ground leads and a video lead for connecting decoupling capacitors, RF power amplifier | |
CN109997223B (en) | Power semiconductor module | |
JP2004254086A (en) | Switching circuit device | |
JP2001036140A (en) | Static countermeasure devised surface-mounting led | |
NL2027146B1 (en) | A radiofrequency power package and device with improved ESD performance | |
KR100874795B1 (en) | High frequency power transistor device and capacitor structure for same | |
US9866186B2 (en) | Amplifier | |
US20160056131A1 (en) | Semiconductor device | |
EP3971972A1 (en) | Esd protection device with reduced harmonic distortion background | |
NL2025182B1 (en) | Electronic package and electronic device comprising the same | |
US11749578B2 (en) | Semiconductor module, power semiconductor module, and power electronic equipment using the semiconductor module or the power semiconductor module | |
KR20210147950A (en) | Microelectronic package fabrication utilizing interconnected substrate arrays containing electrostatic discharge protection grids | |
US20220173057A1 (en) | RF Amplifier Package | |
US11929317B2 (en) | Capacitor networks for harmonic control in power devices | |
US20220293535A1 (en) | Semiconductor Package with Temporary ESD Protection Element | |
US20230129759A1 (en) | Isolation device with safety fuse | |
NL2027022B1 (en) | Electronic package and device comprising the same | |
US5808356A (en) | Lead-frame having unused input/output terminals separated from input/output terminals connected to input/output strip lines | |
CN114759888A (en) | RF amplifier with series coupled output bond wire array and parallel capacitor bond wire array |