NL2023245B1 - Three level PWM Class D amplifier - Google Patents

Abstract

A three level pulse width modulating differential Class D amplifier modulating an input signal into a three level pulse width modulating differential output voltage between first and second output terminals by three level pulse width modulating said input signal into a three level PWM signal having first, second and third levels, and by connecting at said first level first and second output terminals to first and second supply voltages, respectively, by connecting at said second level the first and second output terminals to the second and first supply voltages, respectively, and by disconnecting at said third level both first and second output terminals from both first and second supply voltages and mutually interconnecting these terminals.

Description

Three level PWM Class D amplifier The invention relates to three level pulse width (“PWM”) differential ended Class-D amplifiers {hereafter also referred to as “DE amplifier”) with improved power saving techniques and more specifically to a technique reducing parasitically accumulated energy, which otherwise would generate e.g. excess heat, annoying signal distortions and/or EMI noise.

Such three level PWM DE amplifiers are used to receive and amplify input analog signals having frequency components in the audio frequency range or frequency components in other frequency ranges, which can be lower than, overlapping or higher than the audio frequency range, including ranges within the RF transmission spectrum.

A prior art three level PWM Class-D DE amplifier is known from e.g.

US patent 6,211,728. Disclosed therein is a full H-bridge driver D shown schematically in its first to fourth states of operations in respective Figures 3A to 3D.

This known driver D comprises first and second serial arrangements coupled in parallel between first and second supply voltages, Vs and GND at zero level, respectively including first and second switches S1 and 52 and third and fourth switches S3 and S4. The respective common node of the first and second switches, 51 and S2, and of the third and fourth switches S3 and S4, are coupled to first and second output terminals, O1 and O2 respectively.

In this known full H-bridge driver D, the first and second PWM subsignals occurring at the first and second terminals O1 and O2 are themselves 2 level switching PWM signals varying between the first and second supply voltages, Vs and GND.

The modulation scheme of this known DE amplifier is chosen such, that the voltage difference between these first and second two level PWM subsignals provides for a three level differential PWM output signal, having first and second levels obtained in respective first and second states of operation as shown in Figures 3A and 3B.

A third level is zero level, which is obtained in a third state of operation as shown in Figure 3C, by pulling both output terminals O1 and O2 to the first supply voltage Vs at the same time, or in a fourth state of operation as shown in Figure 3D, by pulling both terminals O1 and O2 to the second supply voltage GND at the same time.

The first and second output terminals O1 and O2 are connectable to a load L, which is shown to include loudspeaker or an audio filter together with a loudspeaker.

The above cited reference, however, neither deals with nor even identify the sources of power loss and EMI noise, which are inherent to the three level PWM DE amplifier disclosed therein.

In particular, significant loss of power is caused by the relatively large parasitic capacitances occurring at nodes (hereafter “external nodes”) that connect components embedded in circuitry printed on the printed circuit board (“PCB”) to one or more external PCB components. Such relatively large parasitic capacitances in particular occur at the first and second output terminals O1 and O2 connecting the driver circuitry to the load L. This is illustrated in Figure 4B by curve b representing a typical time diagram of a two level PWM subsignal occurring at e.g. the first output terminal O1 of the above referenced three level PWM DE amplifier. The voltage transitions occurring at each of both first and second output terminals O1 and O2 of this known three level PWM Class-D DE amplifier inherently amount to the full voltage supply range Vs (with GND at zero voltage). As a consequence, the parasitic capacitance Cpar0Q1 at the first output terminal O1 is being charged at each positive edge of the first two level subsignal by leakage currents of approximately: leakQ1 = CparO1*fclock*Vs. Likewise, the parasitic capacitance CparO2 at the second output terminal 02 is being charged at each positive edge of the first two level subsignal by a similar leakage current lleakO2, bringing the power loss of this known differential type PWM Class D amplifier at a significant level of approximately: lleakT = 2*CparQ1*fclock*Vs, Apart therefrom, the first and second two level PWM subsignals are mutually in phase during duty cycle dependent periods, therewith introducing EMI noise on the common mode voltage. The above prior art three level PWM DE amplifier is therefore limited in power efficiency as well as EMI noise suppression.

ft is a first object of the invention to improve the performance of three level PWM DE amplifiers on EMI reduction and power efficiency, in particular at typical small or close to zero audio signals. it is a second object of the invention to offer a robust and simple three level PWM DE amplifier architecture without giving in on performance.

It is a third object of the invention to optimize the price/performance ratio of such three level PWM DE amplifiers. Now, therefore, a three level PWM differential ended Class-D amplifier comprising respective first and second serial arrangements of first and second, respectively third and fourth switches, coupled in parallel between first and second supply voltages, a common node of said first and second switches being coupled to a first output terminal and a common node of said third and fourth switches being coupled to a second output terminal, is therefore characterized by a fifth switch included in a shunt path between the first and second output terminals, a control circuit receiving an input signal and providing pulse width modulated control signals to control terminals of said first to fifth switches such that in a first state of operation a differential voltage signal is generated between the first and second output terminals determined by the difference between the first and second supply voltages, in a second state of operation a differential voltage signal is generated between the first and second output terminals determined by the difference between the second and first supply voltages, and in a third state of operation both first and second output terminals are being disconnected from both first and second supply voltages, and mutually interconnected through said fifth switch.

A method to amplify an input signal into a three level pulse width modulating differential output voltage between first and second output terminals by three level pulse width modulating said input signal into a three level PWM signal having first, second and third levels, and by connecting at said first level first and second output terminals to first and second supply voltages, respectively, by connecting at said second level the first and second output terminals to the second and first supply voltages, respectively, is therefore characterized by disconnecting at said third level both first and second output terminals from both first and second supply voltages and mutually interconnecting these terminals.

Compared to the voltage transitions of the PWM subsignals at the respective first and second output terminals of the cited prior art, the voltage transitions at the respective first and second output terminals of the amplifier according to the invention are approximately 50% smaller in amplitude, and due to the third state of operation, in which no power is being consumed as both first and second terminals are being disconnected from both first and second supply voltages, reduced by approximately 50% in frequency of occurrence.

The invention therewith reduces the power loss of the cited prior art by approximately 75% to about 25%. Furthermore, the invention prevents the first and second two level PWM subsignals from varying mutually in phase, resulting in a strong suppression of common mode EMI noise. In addition thereto, the invention provides for a simple three level PWM modulation scheme which allows for a simple, robust and low cost implementation, being in particular suitable to be used in the field of battery operated consumer audio and RF products.

The above and other object features and advantages of the present invention will be discussed in more detail hereinafter with reference to the disclosure of preferred embodiments, in which like or similar components are designated by the same numeral through the several views and in particular with reference to the appended Figures.

Well known circuits have been shown therein in functional schematic diagram form in order not to obscure the present invention in unnecessary detail.

For the most part, details concerning timing and processing considerations and the like, such as dead times, have been omitted inasmuch as such details are not necessary to obtain a complete understanding of the present invention and are within the skill of persons of ordinary skill in the relevant art.

Figure 1A is a schematic diagram of an embodiment of the three level PWM DE amplifier according to the invention.

Figure 1B is a schematic diagram of a control circuit generating control signals for the switches of the driver D of the three level PWM DE amplifier of Figure 1A.

Figure 1C is a schematic diagram of a load of the three level PWM DE amplifier of Figure 1A functioning as an audio amplifier.

Figure 1D is a schematic diagram of a load of the three level PWM DE amplifier of Figure 1A functioning as an RF antenna amplifier.

Figures 2A, 2B and 2C are schematic diagrams showing the state of first to fifth switches S1 to 55 and the various currents in the respective first, second and third states of operation of the DE embodiment of a Class-D amplifier of Figure 1A.

Figures 3A, 3B, 3C and 3D are schematic diagrams showing the state of the various switches and the currents in the respective first, second, third and fourth states of operation of the prior art DE type three level PWM Class D amplifier disclosed in the above cited US patent 6,211,728. Figure 4A are plots illustrating signal waveforms of a three level PWM modulator M included in the control circuit of Figure 1B having first, second and third levels at amplitudes +1,-1 and 0, and the first three level PWM subsignal of the amplifier of Figure 1A, having first, second and third levels at amplitudes 0.5Vs, -0.5Vs and 0 when choosing V1 and V2 at 0.5Vs and V2=-0.5Vs, respectively ; Figure 4B are plots illustrating signal waveforms of the first two level PWM subsignal of the prior art three level PWM DE amplifier of above cited US patent 6,211,728; Figure 4C are plots illustrating signal waveforms of the pulsed leakage currents a’ occurring in the three level PWM DE amplifier of Figure 1A and the pulsed leakage currents b’ occurring in Class-D amplifier known from US patent 6,211,728.

Figure 5A is a plot illustrating the PWM differential output signal of the three level PWM DE amplifier of Figure 1A, and the input signal s scaled with the gain of said three level PWM DE amplifier. Figure 5B is a plot illustrating the PWM output signal of Figure 5A after being filtered in the filter included in the load.

5 Figure 1A shows a three level PWM differential Class D amplifier according to the invention comprising a driver D having respective first and second serial arrangements SA1 and SA2 of first and second S1 and 52, respectively third and fourth switches 53 and S4, coupled in parallel between first and second supply voltages V1 and V2, a common node of said first and second switches S1 and S2 being coupled to a first output terminal O1 and a common node of said third and fourth switches 53 and $4 being coupled to a second output terminal Q2. A fifth switch S5 included in a shunt path SP between the first and second output terminals O1 and O2. These switches S1 to S5 may be high speed MOSFET type switches, suitable to process RF signals, each being controlled by a binary switching control signal cs to switch on, close or bring it into a conductive state, e.g. at a binary value cs=1 and switch off, open or bring it into a non- conductive state at a binary value cs = 0.

The control circuit CC generates a first switching control signal cs1 being provided to control terminals of the first and fourth switches, S1 and 54, respectively, a second switching control signal cs2 being provided to control terminals of the second and third switches S2 and S3, respectively, and a third first switching control signal cs3 being provided to the control terminal of the fifth switch S5. The first, second and third switching control signals csi, cs2 and cs3, respectively, are chosen such that, in a first state of operation of the driver D, a differential voltage signal is generated between the first and second output terminals O1 and O2 determined by the difference between the first and second supply voltages V1 and V2, in a second state of operation a differential voltage signal is generated between the first and second output terminals O1 and O2 determined by the difference between the second and first supply voltages V2 and V1, respectively, and in a third state of operation both first and second output terminals O1 and 02 are being disconnected from both first and second supply voltages V1 and V2, and mutually interconnected through said fifth switch S5.

More in particular, Figure 2A shows that the first state of operation is obtained by controlling the first and fourth switches, S1 and S4, respectively, to close (with cs1 = 1) and by controlling the second, third and fifth switches, S2, $3, and S5, respectively, to open {with cs2 = cs3 = 0). The set of binary values of the first to third switching control signals, cs1, cs2 and cs3 respectively, in this first state of operation may be indicated as (1,0,0).

In this first state of operation the driver D generates a differential output voltage between the first and second output terminals, O1 and O2 respectively, at a first amplitude level, equal to the difference between first and second supply voltages V1 and V2, i.e. (V1-V2). The three level PWM differential Class D amplifier according to the invention of Figure 1A may function as an audio amplifier, receiving an audio input signal at the input of the three level PWM modulator M, in which case the load L includes an audio filter AF coupled to a loud speaker LS as shown in Figure 1C. The three level PWM differential Class D amplifier according to the invention of Figure 1A may alternatively function as an RF transmission amplifier receiving an RF input signal at the input of the three level PWM modulator M, in which case the load L includes an RF filter RF coupled to an RF transmitting antennae ANT as shown in Figure 1D. Figure 2B shows that the second state of operation is obtained by controlling the second and third switches, S2 and S3, respectively, to close (with cs2 = 1} and by controlling the first, fourth and fifth switches, 51, 54, and S5, respectively, to open {with cs1 = cs3 = 0). The set of binary values of the first to third switching control signals, cs1, cs2 and cs3 respectively, in this second state of operation may be indicated as {0,1,0). In this second state of operation the driver D generates a differential output voltage between the first and second output terminals, O1 and O2 respectively, at a second amplitude level, equal to the difference between the second and first supply voltages V2 and V2, i.e. (V2-V1)}.

Figure 2C shows that the third state of operation is obtained by controlling the first to fourth switches, S1, 52, S3 and S4, respectively, to open {with cs1 = cs2 = 0) and by controlling the fifth switch S5 to close (with cs3 = 1), The set of binary values of the first to third switching control signals, cs1, cs2 and cs3 respectively, in this third state of operation may be indicated as (0,0,1). in this third state of operation the driver D generates a differential output voltage between the first and second output terminals, O1 and O2 respectively, at a third or intermediate amplitude level, which due to the interconnection between O1 and O2 through the fifth switch 55, equals in practice approximately 0, positioned approximately equidistant between said first and second amplitude levels. A functional block diagram of the control circuit CC is shown in Figure 1B and includes a three level PWM modulator M followed by a gate driver circuit GDC. An input signal IS, which may be an analog audio signal or RF signal, is being provided to the modulator M and modulated therein into a three level PWM modulated signal. Figure 4A illustrates by way of example said input signal IS with a dotted curve s and the three level PWM modulated signal generated therefrom by the modulator M with curve a, First,

second and third signal levels at respective amplitudes +1, -1 and 0 of this three level PWM modulated signal a are being obtained in respective first, second and third states of operation of the modulator M. Such modulator M is itself known, e.g. from At the reception of these first, second and third levels, the gate driver circuit GDC generates the respective sets of binary values of the first to third switching control signals (1,0,0), (0,1,0) and {0,0,1). The driver D therewith follows the modulation scheme of the modulator M with both driver D and modulator M mutually corresponding in state of operation. This results in an amplification of the three level PWM signal of the modulator M in the driver D into the three level differential PWM output signal obtained between the first and second terminals O1 and O2. Given the above functionalities of the various switches of the driver D in the first, second and third states of operation necessary to obtain the above amplification according to the invention, the translating thereof to an actual realization of the control circuit CC is straightforward to a person skilled in the art and shall therefore not be described in further detail.

As mentioned above, the first and second subsignals at the first and second output terminals, O1 and O2 respectively, of the DE amplifier of Figure 1A with V1=0.5Vs and V2=-0.5Vs are basically three level PWM signals with first, second and third levels at 0.5Vs, -0.5Vs and 0, mutually identical and varying in phase opposition. The first subsignal at the first output terminal O1 is illustrated by way of example by curve a in Figure 4A. At similar supply voltages, the above conventional three level PWM Class D generates at its first output terminal O1 corresponding to the first output terminal O1 of the differential Class-D amplifier according to the invention, a two level PWM subsignal illustrated in Figure 4B by curve b. Figure 4C illustrates in curve b’ the pulse wise leakage currents HeakO1 charging the parasitic capacitances CparQ1 at each positive edge of the first two level PWM subsignal at the first terminal O1 of said conventional amplifier. Curves a’ of Figure 4C illustrate the pulse wise leakage currents lleakO1 charging the parasitic capacitances CparO1 at each positive edge of the first three level PWM subsignal at the first terminal O1 of the amplifier according to the invention.

The leakage currents a’ are in amplitude half the amplitude of the leakage currents b’, reducing the original power leakage of the above conventional three level PWM Class D amplifier by 50%.

Furthermore, the leakage currents b’ occur during the full duration of the curve s, whereas the leakage currents a’ occur only during the positive halves thereof, resulting in another reduction of the original power leakage by 50%, resulting in a total of reduction to 0.5 x 0.5 = 0.25 or 25%.

Apart therefrom the conventional amplifier introduces EMI noise common mode variations due to the shortcircuiting of the first and second terminals 1 and 2 in the third state of operation through the first supply voltage Vs, and the fourth state of operation through the second supply voltage GND.

The invention however avoids such common mode variations, as in the third state of operation the intermediate level is obtained by shortcircuiting the first and second output terminal O1 and O2 while disconnecting these terminals from both supply voltages.

Figure 5A is a plot illustrating with curve os the PWM differential output signal of the three level PWM DE amplifier of Figure 1A, having first, second and third levels at Vs, -Vs and 0.

The modulation signal included in this PWM differential output signal is illustrated with curve s’ representing the input signal s scaled with the gain of said three level PWM DE amplifier. Figure 5B is a plot illustrating with curve fos the PWM output signal of Figure 5A after being filtered in the filter included in the load. This filter may be an audio filter, when the three level PWM DE amplifier of Figure 1A is dimensioned to function as an audio amplifier, receiving an audio input signal, or an RF filter, when the three level PWM DE amplifier of Figure 1A is dimensioned to function as an RF transmission amplifier, receiving an RF input signal.

The invention is not limited to the embodiments explicitly disclosed. The person skilled in the art of Class D amplifier design will recognize further policies to be followed within the ambit of the present invention. For example the invention may well be applied mutatis mutandis to pulse density modulation amplifiers.

The invention is embodied in each new characteristic and each combination of characteristics. Any reference signs do not limit the scope of the claims. The word "comprising" does not exclude the presence of other elements than those listed in a claim. Use of the word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

Claims (2)

Conclusions: A three level pulse width modulation differential Class-D amplifier comprising first and second series connections of first and second (51 and 52), third and fourth (S3 and 54} switches, respectively, coupled in parallel between first and second supply voltages (V1 and V2}, wherein a common node of said first and second switches {S1 and S2} is coupled to a first output terminal (01) and a common node of said third and fourth switches (53 and 54} is coupled to a second output terminal (02 ), characterized by a fifth switch (S5), which is included in a shunt path (SP) between the first and second output terminals (O1) and (02), a control circuit receiving an input signal and pulse width modulated control signals at control inputs of said first up to fifth switches (51-55), such that in a first operating state a differential voltage signal is generated between n the first and second output terminals {01 and 02) determined by the difference between the first and second supply voltage (V1-V2), in a second operating state a differential voltage signal is generated between the first and second output terminals (O1 and O2} determined by the difference between the second and first supply voltage (V2-V1), and in a third operating state both the first and second output terminals (O1 and O2} are disconnected from both first and second supply voltages (V1 and V2) and interconnected via the fifth switch (S5). 2. A method of amplifying an input signal to a three level pulse width modulation differential output voltage between first and second output terminals by a three level pulse width modulation of the input signal into a three level pulse width modulation PWM signal with first, second and third levels, and by pressing the first level to connect the first and second output terminals (O1 and 02) to first and second supply voltages (V1, V2, respectively), respectively, by connecting the first and second output terminals (O1, O2, respectively) to the second and first supply voltages (V2, V1 respectively), characterized by disconnecting on the third level both first and second second output terminals (O1 and O2} from both the first and the second supply voltage (V1, V2) and by these terminals (O1 and 02) interconnect.