CN113258908A

CN113258908A - Dual bootstrapping for open loop pulse width modulation drivers

Info

Publication number: CN113258908A
Application number: CN202110177205.7A
Authority: CN
Inventors: 白婧; 特贾斯维·达斯; 赵欣; 朱磊; 费晓凡
Original assignee: Cirrus Logic International Semiconductor Ltd
Current assignee: Cirrus Logic International Semiconductor Ltd
Priority date: 2020-02-07
Filing date: 2021-02-07
Publication date: 2021-08-13
Also published as: GB202100699D0; GB2593279A

Abstract

A driver system and method for use in a driver system may include a first n-type field effect transistor coupled at its non-gate terminal between an output of the driver system and a first terminal of a supply voltage and configured to drive the output when the first n-type field effect transistor is activated; a second n-type field effect transistor coupled at its non-gate terminal between the output of the driver system and a second terminal of the supply voltage and configured to drive the output when the second n-type field effect transistor is activated; a high-side capacitor coupled to an output of the driver system; and a low-side capacitor coupled to a second terminal of the supply voltage, wherein the high-side capacitor and the low-side capacitor are configured to track and correct a mismatch between a first resistance of the first n-type field effect transistor and a second resistance of the second field effect transistor.

Description

Dual bootstrapping for open loop pulse width modulation drivers

RELATED APPLICATIONS

This application is a continuation-in-part application of U.S. patent application No. 16/162,960 filed on 17.10.2018, which claims priority to U.S. provisional patent application No. 62/632,291 filed on 19.2.2018, which is incorporated herein by reference in its entirety.

Technical Field

The present disclosure relates generally to circuits for audio and haptic devices, including but not limited to personal audio devices such as wireless telephones and media players, or devices incorporating haptic modules.

Background

Personal audio devices, including wireless telephones such as mobile/cellular telephones, cordless telephones, mp3 players and other consumer audio devices are widely used. Such personal audio devices may include circuitry for driving a pair of headphones or one or more speakers. Such circuits typically include a power amplifier for driving an audio output signal to a headphone or speaker. In general, a power amplifier amplifies an audio signal by drawing energy from a power source and controlling an audio output signal to match the shape of the input signal but with a larger amplitude.

One example of an audio amplifier is a class D amplifier. Class D amplifiers (also referred to as "switching amplifiers") may include electronic amplifiers in which the amplifying device (e.g., a transistor, typically a metal oxide semiconductor field effect transistor) operates as an electronic switch. In a class D amplifier, the signal to be amplified may be converted to a series of pulses by Pulse Width Modulation (PWM), pulse density modulation, or another method of modulation, such that the signal is converted to a modulated signal in which the characteristics of the pulses of the modulated signal (e.g., pulse width, pulse density, etc.) are a function of the signal amplitude. After amplification with a class D amplifier, the output pulse train may be converted to an unmodulated analog signal by passing through a passive low pass filter, where such low pass filter may be a load inherent in or driven by the class D amplifier. Class D amplifiers are commonly used due to the fact that they are more power efficient than linear analog amplifiers, since they may consume less power as heat in an active device than linear analog amplifiers.

Typically, the closed loop PWM amplifier is selected to provide an accurate load voltage with the desired Total Harmonic Distortion (THD) and Power Supply Rejection Ratio (PSRR). Closed loop PWM amplifiers typically employ an analog voltage input and a sensed feedback voltage signal that is fed through a closed loop analog PWM modulator to drive the voltage across the speaker load.

The option of using a single PWM amplification circuit in either an open loop or a closed loop to drive the load instead may be desirable depending on the particular application. However, conventional open loop PWM amplifiers are known to have non-linearity due to the lack of a feedback loop. Such non-linearity may be caused by a mismatch between a high-side device (e.g., a device for driving an output of the device to a first voltage) and a low-side device (e.g., a device for driving an output of the device to a second voltage, lower than the first voltage, such as ground). In conventional approaches, open-loop drivers are typically implemented using inverters formed of p-type field effect transistors and n-type field effect transistors, and matching p-type to n-type devices is often difficult, especially at process, voltage, and temperature corners. Such linearity may also be caused by a mismatch between the positive polarity side and the negative polarity side in a differential driver (e.g., an H-bridge driver). The presence of non-polarity may increase the total harmonic distortion and also cause mixing of high frequency out-of-band noise with in-band content, thereby increasing the in-band noise floor of the drive.

Accordingly, systems and methods that reduce or eliminate non-linearities in open loop pulse width modulation drivers are desired.

Disclosure of Invention

In accordance with the teachings of the present disclosure, one or more of the disadvantages and problems associated with previous approaches to processing signals using amplifiers may be reduced or eliminated.

According to an embodiment of the present disclosure, a driver system may comprise a first n-type field effect transistor coupled at its non-gate terminal between an output of its driver system and a first terminal of a supply voltage and configured to drive the output when the first n-type field effect transistor is activated; a second n-type field effect transistor coupled at its non-gate terminal between the output of its driver system and a second terminal of the supply voltage and configured to drive the output when the second n-type field effect transistor is activated; a high-side capacitor coupled to an output of the driver system; and a low-side capacitor coupled to the second terminal of the supply voltage, wherein the high-side capacitor and the low-side capacitor are configured to track and correct for a mismatch between a first resistance of the first n-type field effect transistor and a second resistance of the second n-type field effect transistor.

In accordance with these and other embodiments of the present disclosure, there may be provided a method for use in a driver system, the driver system comprising a first n-type field effect transistor coupled at its non-gate terminal between an output of the driver system and a first terminal of a supply voltage and configured to drive the output when the first n-type field effect transistor is activated; a second n-type field effect transistor coupled at its non-gate terminal between the output of the driver system and a second terminal of the supply voltage and configured to drive the output when the second n-type field effect transistor is activated; a high-side capacitor coupled to an output of the driver system; and a low-side capacitor coupled to a second terminal of the supply voltage. The method may include tracking, by the high-side capacitor and the low-side capacitor, a mismatch between a first resistance of the first n-type field effect transistor and a second resistance of the second n-type field effect transistor, and correcting the mismatch by the high-side capacitor and the low-side capacitor.

The technical advantages of the present disclosure will be readily apparent to one skilled in the art from the figures, descriptions, and claims included herein. The objects and advantages of the embodiments will be realized and attained by means of the elements, features and combinations particularly pointed out in the appended claims.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the claims as set forth in the disclosure.

Drawings

A more complete understanding of the present embodiments and advantages thereof may be acquired by referring to the following detailed description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features, and wherein:

fig. 1 is an illustration of an example personal audio device, in accordance with an embodiment of the present disclosure.

FIG. 2 is a block diagram of selected components of an example audio integrated circuit of a personal audio device, according to an embodiment of the present disclosure.

Fig. 3 is a block diagram of selected components of an example reconfigurable PWM modulator, according to an embodiment of the present disclosure.

Fig. 4 is a block diagram of selected components of an example reconfigurable PWM modulator, including components for calibrating path gain, according to an embodiment of the present disclosure.

Fig. 5 is a block diagram of selected components of another example reconfigurable PWM modulator, including components for calibrating path gain, according to an embodiment of the present disclosure.

Fig. 6 is a block diagram of selected components of an open loop pulse width modulation driver according to an embodiment of the present disclosure.

Fig. 7 illustrates example voltage waveforms on various electrical nodes of the open loop pulse width modulation driver shown in fig. 6, in accordance with an embodiment of the present disclosure.

Detailed Description

Fig. 1 is an illustration of an example personal audio device 1 according to an embodiment of the present disclosure. Fig. 1 shows a personal audio device 1 coupled to a headset 3 in the form of a pair of

earbud speakers

8A and 8B. The headphones 3 shown in fig. 1 are but one example, and it should be understood that the personal audio device 1 may be used in connection with a variety of audio transducers, including but not limited to headphones, earphones, in-ear headphones, and external speakers. The plug 4 may provide a connection for the headset 3 to an electronic terminal of the personal audio device 1. The personal audio device 1 may provide a display screen to the user and receive user input through the use of the touch screen 2, or alternatively, a standard Liquid Crystal Display (LCD) may be combined with various keys, sliders and/or dials disposed on the front and/or sides of the personal audio device 1. As also shown in fig. 1, the personal audio device 1 may include an audio Integrated Circuit (IC)9 for generating analog audio signals for transmission to the headphones 3 and/or another audio transducer (e.g., a speaker).

FIG. 2 is a block diagram of selected components of an example audio IC 9 of a personal audio device, according to an embodiment of the present disclosure. In some embodiments, the example audio IC 9 may be used to implement the audio IC 9 of fig. 1. As shown IN FIG. 2, a microcontroller core 18 (e.g., a digital signal processor or "DSP") may provide a digital audio input signal DIG _ IN to a digital-to-analog converter (DAC)14, which may convert the digital audio input signal to an analog input signal V_IN. DAC 14 may provide an analog signal V_INTo an amplifier 16 which may amplify or attenuate the analog input signal V_INTo provide an audio output signal V_OUTWhich may operate speakers, headphone transducers, line level signal outputs, and/or other suitable inputs.

Fig. 3 is a block diagram of selected components of an example reconfigurable pulse width modulation amplifier 22, in accordance with an embodiment of the present disclosure. In some embodiments, an example reconfigurable pulse width modulation amplifier 22 may be used to implement the amplifier 16 of fig. 2. As shown in fig. 3, an example reconfigurable pulse width modulation amplifier 22 may include a digital PWM modulator subsystem 24 and an analog PWM modulator 26, along with a direct bypass function implemented by a multiplexer 28.

Reconfigurable PWM modulation amplifier 22 may be configured to operate in an ANALOG closed loop mode through the use of ANALOG PWM MODULATOR 26 when the ANALOG MODULATOR BYPASS (ANALOG MODULATOR BYPASS) control signal received by multiplexer 28 is deasserted (deasserted). In analog closed-loop mode, the input signal V_INMay be modulated by digital PWM modulator subsystem 24, analog PWM modulator 26 may receive its input from digital PWM modulator subsystem 24, and analog PWM modulator 26 may be employed such that analog PWM modulator 26 as output signal V when received and driven by driver stage 34B_OUTIs driven. Driver stage 34B may include a plurality of output switches configured to generate output signal V from the modulated signal generated by analog PWM modulator 26_OUT。

Reconfigurable PWM modulation amplifier 22 may also be configured to operate in a digital open loop mode through the use of digital PWM MODULATOR subsystem 24 when an ANALOG MODULATOR BYPASS control signal (ANALOG MODULATOR BYPASS) received by multiplexer 28 is asserted (asserted). In the digital open loop mode, analog PWM modulator 26 and driver stage 34B driven by analog PWM modulator 26 may be bypassed by multiplexer 28, and digital PWM modulator subsystem 24 may be employed such that input signal V_INIs modulated by digital PWM modulator subsystem 24, and causes the output of digital PWM modulator subsystem 24, when received and driven by open loop driver stage 34A, to be output signal V_OUTIs driven. Driver stage 34A may include a plurality of output switches configured to generate output signal V from the modulated signal generated by digital PWM modulator subsystem 24_OUT。

Which of driver stage 34A and driver stage B is selected to drive output signal V through the use of multiplexer 28_OUTIt is possible to switch the reconfigurable PWM modulation amplifier 22 from an analog closed loop mode and a digital open loop mode (or vice versa).

In some embodiments, control circuitry (not shown) may be used to control the multiplexer 28 to select the signal processing path for the reconfigurable PWM modulation amplifier 22. For example, the selection of such a multiplexer control signal may be based on the input signal V to the amplifier_INOf the input signal (e.g. signal amplitude, signal peak, signal envelope, signal frequency or input signal V)_INOther characteristics of). Further, the reconfigurable PWM modulation amplifier 22 may include a digital pulse width modulator subsystem (e.g., digital PWM modulator subsystem 24); a first path coupled to the output of the digital pulse width modulator subsystemAnd configured to drive an open-loop driver stage (e.g., driver stage 34A); and a second path coupled to an output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator (e.g., analog PWM modulator 26), wherein one of the first and second paths is based on one or more characteristics of the signal (e.g., signal amplitude, signal peak, signal envelope, or input signal V_INOther characteristics) is selected for processing the signal. At the input signal V_INIn embodiments that are audio signals, the selection of the path for processing may be based not only on the characteristics of the audio signal in the audible frequency band, but also on the output signal V_OUTThe out-of-band component of the propagated signal.

Fig. 4 is a block diagram of selected components of an example reconfigurable PWM modulation amplifier 22A, according to an embodiment of the present disclosure. In some embodiments, reconfigurable PWM modulation amplifier 22A may be used to implement reconfigurable PWM modulation amplifier 22 of fig. 3. As shown in fig. 4, a single digital PWM modulator 24A may be used to implement the digital PWM modulator subsystem 24.

Fig. 5 is a block diagram of selected components of an example reconfigurable PWM modulation amplifier 22B, in accordance with an embodiment of the present disclosure. In some embodiments, reconfigurable PWM modulation amplifier 22B may be used to implement reconfigurable PWM modulation amplifier 22 of fig. 3. As shown in fig. 5, the digital PWM modulation subsystem 24 of fig. 2 may be implemented using a first digital PWM modulator 24B and a second digital PWM modulator subsystem 24C. Digital PWM modulator 24B may drive open-loop driver stage 34A, while digital PWM modulator 24C may drive analog PWM modulator 26.

Although fig. 3-5 show configurations configured to select as output signal V between the output of pass driver stage 34A and the output of pass driver stage 34B_OUTMultiplexer 28, one skilled in the art will recognize that any other suitable circuit, system, device, or apparatus may be used in addition to or in place of multiplexer 28 to select between the output of pass driver stage 34A and the output of pass driver stage 34B as output signal V_OUT. As a non-limiting exampleBy way of illustrative example, in some embodiments,

driver stages

34A and 34B may have tri-state outputs that together may be configured to perform a function functionally equivalent to multiplexer 28.

Advantageously, the above-described method provides a system and method for implementing and using a system that includes a reconfigurable amplifier that can be switched between an analog closed-loop modulation amplifier and a digital open-loop modulation amplifier with minimal additional digital logic compared to existing amplifier systems.

Fig. 6 is a block diagram of selected components of open loop PWM driver stage 40, according to an embodiment of the present disclosure. In some embodiments, the open-loop PWM driver stage 40 may be used to implement all or a portion of the driver stage 34A of FIGS. 3-5. As shown in fig. 6, the open-loop PWM driver stage 40 may be implemented with an output driver using two n-type metal-oxide-semiconductor field effect transistors (n-MOSFETs) including a high-side n-MOSFET 42 and a low-side n-MOSFET 44. The high-side n-MOSFET 42 may be coupled at its drain terminal to a first terminal of a supply voltage (e.g., to a voltage V)_DDD) Coupled at its source terminal to the output node of the open loop PWM driver stage 40 and coupled at its gate terminal to the output of the high side pre-driver 46. The low side n-MOSFET 44 may be coupled at a drain terminal to an output node of the open loop PWM driver stage 40, at a source terminal thereof to a second terminal of the supply voltage (e.g., to ground), and at a gate terminal thereof to an output of the low side pre-driver 48.

The open-loop PWM driver stage 40 may also include a high-side bootstrapped n-mosfet coupled at its source terminal to a first terminal of the supply voltage (e.g., to the voltage V_DDD) Coupled at its drain terminal to a first terminal of the high-side bootstrap capacitor 54 and coupled at its gate to the high-side switch signal Vg _ sw _ h. The high-side bootstrap capacitor 54 may also be coupled at its second terminal to the output node of the open-loop PWM driver stage 40. Thus, the high-side pre-driver 46 may be coupled to respective terminals of a high-side bootstrap capacitor 54 through its differential supply voltage inputs. In operation,the gate terminal of high-side pre-driver 46 may be driven to open-loop PWM driver stage 40 by an inversion of a PWM input signal, where such inverted PWM input signal is between a voltage VDD _ FLY (described in more detail below with reference to fig. 7) and an output voltage V_OUTIs level shifted.

The open-loop PWM driver stage 40 may also include a low-side bootstrapped p-type metal-oxide-semiconductor field effect transistor (p-MOSFET)56 coupled at its source terminal to a first terminal of the supply voltage (e.g., V |)_DDD) Coupled at its drain terminal to a first terminal of the low side bootstrap capacitor 58 and at its gate to a low side switch signal Vg _ sw _ l, which may be the complement of the high side switch signal Vg _ sw _ h. Each of the low-side and high-side switching signals Vg _ sw _ l, Vg _ sw _ h may be a PWM input waveform. The maximum voltage of the high-side switch signal Vg _ sw _ h may be level shifted, or pumped, above the voltage V_DDDAnd the sum of the threshold voltage of the high-side bootstrap n-MOSFET 52, so that the high-side bootstrap n-MOSFET 52 is sufficiently activated, and its minimum voltage should be lower than the voltage V_DDDSo as to fully deactivate the high-side bootstrap n-MOSFET 52. The low-side bootstrap capacitor 58 may also be coupled at its second terminal to a second terminal of the supply voltage (e.g., ground voltage). Thus, the low side pre-driver 48 may be coupled through its differential supply voltage inputs to respective terminals of the low side bootstrap capacitor 58. In operation, the gate terminal of the low-side pre-driver 48 may be driven by the PWM input signal to the open-loop PWM driver stage 40.

Fig. 7 illustrates example voltage waveforms on various electrical nodes of the open loop pulse width modulation driver stage 40 shown in fig. 6, where VDD _ FLY represents the voltage present at an electronic node shared by the drain terminal of the high-side bootstrap n-MOSFET 52 and the first terminal of the high-side bootstrap capacitor 54, and VDD _ INTERNAL represents the voltage present at an electronic node shared by the drain terminal of the low-side bootstrap p-MOSFET 56 and the first terminal of the low-side bootstrap capacitor 58, in accordance with an embodiment of the present disclosure. Thus, those skilled in the art will recognize that in operation, when the output voltage V is applied_OUTFrom 0 to V_DDDWhen the high-side bootstrap n-mosfet 52 is turned off, and VDD _ FLY can be from V_DDDRise to 2V_DDDOffset 1. The offset1 voltage may be caused by capacitor 54 discharging to charge the Cgs capacitance of the high-side n-MOSFET 42. The value of offset1 can be reduced or minimized by using a larger capacitor 54. The low-side bootstrap p-MOSFET 56 may be turned on (e.g., with a small delay) and may charge the capacitor 58 to V_DDD。

When the output voltage V is_OUTFrom V_DDDWhen falling to 0, the low side bootstrap p-MOSFET 56 turns off and VDD _ INTERNAL falls to V_DDDOffset 2. VDD _ FLY can be from 2V_DDD-offset1 falls to V_DDDOffset 1. The offset2 voltage may be caused by capacitor 56 discharging to charge the Cgs capacitance of the low side n-MOSFET 44. With a small delay, the high-side bootstrap n-MOSFET 52 may be turned on and charge the capacitor 54 to V_DDD。

If

capacitors

54 and 58 are matched and high side n-MOSFET 42 is matched to low side n-MOSFET 44, offset1 may be equal to offset2 and thus the drain-source levels on the resistances of

MOSFETs

42 and 44 will be matched.

During fabrication of the open-loop pulse width modulation driver stage 40, various high-side components (e.g., the high-side n-MOSFET 42, the high-side bootstrap n-MOSFET 52, the high-side pre-driver 46, the high-side bootstrap capacitor 54) may be matched to have substantially the same process parameters as various low-side components (e.g., the low-side n-MOSFET 44, the low-side bootstrap p-MOSFET 56, the low-side pre-driver 48, the low-side bootstrap capacitor 58) such that the high-side components and the low-side components experience substantially the same variations in process, supply voltage, temperature, and other parameters.

During operation, the gate-source voltages of the high-side n-MOSFET 42 and the low-side n-MOSFET 44 should remain matched. Thus, the high-side bootstrap capacitor 54 and the low-side bootstrap capacitor 58 may be configured to track and correct a mismatch between the gate-to-source resistance of the high-side n-MOSFET 42 when the high-side n-MOSFET 42 is activated and the gate-to-source resistance of the low-side n-MOSFET 44 when the low-side n-MOSFET 44 is activated.

In addition, the high-side bootstrap capacitor 54 may track any offset that may occur at the gate terminal of the high-side n-MOSFET 42, as well as offset that occurs at the output node of the open-loop pulse width modulation driver stage 40. Also, the low side bootstrap capacitor 58 may track any offset that may occur at the gate terminal of the low side n-MOSFET 44, track any offset that may occur at the gate terminal of the high side n-MOSFET 42, and may correct one or more of these offsets at the output node of the open loop pulse width modulation driver stage 40. Thus: (i) the high-side bootstrap capacitor 54 tracks the first offset occurring at the gate terminal of the high-side n-MOSFET 42 and corrects the first offset at the output node of the open-loop pulse width modulation driver stage 40; (ii) the low side bootstrap capacitor 58 tracks the second offset occurring at the gate terminal of the low side n-MOSFET 44 and corrects the second offset at the output node of the open loop pulse width modulation driver stage 40; and (iii) the low-side bootstrap capacitor 58 tracks the second offset in a manner that corrects the first offset.

Further, as shown in fig. 7, tracking and correction of the offset is implemented by controlling at least one of the high-side n-MOSFET 42 and the low-side n-MOSFET 44 during and after each edge transition of the output signal at the output node of the open-loop pulse width modulation driver stage 40. Such control may include feedback of current at the output signal V based on voltage feedback through the gate terminal of the high-side n-MOSFET 42 and/or through the output node of the open-loop pulse width modulation driver stage 40_OUTControls the high-side n-MOSFET 42DE gate-source resistance during the first edge transition. Additionally or alternatively, such control may include feedback of the current at the output signal V based on voltage feedback through the gate terminal of the low-side n-MOSFET 44 and/or through the output node of the open-loop pulse width modulation driver stage 40_OUTControls the gate-source resistance of the low-side n-MOSFET 44 during the second edge transition. Additionally or alternatively, to correct for the mismatch between the gate-source resistance of the high side n-MOSFET 42 and the gate-source resistance of the low side n-MOSFET 44, the control after the edge transition will control at least one of the first resistance and the second resistance.

Although FIG. 6 shows the high-side n-MOSFET 42, the high-side bootstrap n-MOSFET 52 and the low-side bootstrap p-MOSFET 56 are allCoupled to the same supply voltage V_DDDHowever, in some embodiments, the high-side bootstrapped n-MOSFET 52 and the low-side bootstrapped p-MOSFET 56 may be coupled to a different source voltage than that coupled to the high-side n-MOSFET 42.

As used herein, when two or more elements are referred to as being "coupled" to each other, such terms indicate that the two or more elements are in electrical or mechanical communication, whether connected indirectly or directly, with or without intervening elements, if applicable.

The present disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend where appropriate. Furthermore, references in the appended claims to a device or system, or a component of a device or system, adapted to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompass the device, system, or component, whether active, open, or unlocked, as long as the device, system, or component is so adapted, capable, configured, enabled, operable, or operative. Thus, modifications, additions, or omissions may be made to the systems, apparatuses, and methods described herein without departing from the scope of the disclosure. For example, components of the system and apparatus may be integrated or separated. Further, the operations of the systems and apparatus disclosed herein may be performed by more, fewer, or other components, and the methods described may include more, fewer, or other steps. Additionally, the steps may be performed in any suitable order. As used in this document, "each" refers to each member of a set, or each member of a subset of a set.

Although exemplary embodiments are illustrated in the drawings and described below, the principles of the present disclosure may be implemented using any number of techniques, whether currently known or not. The present disclosure should in no way be limited to the exemplary embodiments and techniques illustrated in the drawings and described above.

The articles shown in the drawings are not necessarily drawn to scale unless specifically indicated otherwise.

All examples and conditional language recited herein are intended for pedagogical objects to aid the reader in understanding the disclosure and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Although the embodiments of the present disclosure have been described in detail, it should be understood that various changes, substitutions, and alterations can be made hereto without departing from the spirit and scope of the invention.

While specific advantages have been enumerated above, various embodiments may include some, none, or all of the enumerated advantages. Still other technical advantages will be readily apparent to one skilled in the art from a reading of the following figures and description.

To assist the patent office and any reader of any patent issued on this application in interpreting the claims appended hereto, applicants intend to note that they do not intend for any of the appended claims or claim elements to refer to 35u.s.c. § 112(f), unless the word "method for.

Claims

1. A driver system comprises

A first n-type field effect transistor coupled at its non-gate terminal between an output of the driver system and a first terminal of a supply voltage and configured to drive the output when the first n-type field effect transistor is activated;

a second n-type field effect transistor coupled at its non-gate terminal between an output of the driver system and a second terminal of the supply voltage and configured to drive the output when the second n-type field effect transistor is activated;

a high side capacitor coupled to an output of the driver system; and

a low-side capacitor coupled to a second terminal of the supply voltage;

wherein the high-side capacitor and the low-side capacitor are configured to track and correct a mismatch between a first resistance of the first n-type field effect transistor and a second resistance of the second field effect transistor.

2. The driver system of claim 1, wherein the high-side capacitor is further configured to track a first offset occurring at a gate terminal of the first n-type field effect transistor and correct the first offset at the output.

3. The driver system of claim 2, wherein the low side capacitor is further configured to track a second offset occurring at a gate terminal of the second n-type field effect transistor and correct the second offset at the output.

4. The driver system of claim 3, wherein the low side capacitor is further configured to track the second offset in a manner that corrects the first offset.

5. The driver system of claim 1, wherein the tracking and correcting comprises controlling at least one of the first n-type field effect transistor and the second n-type field effect transistor during and after each edge transition of the output signal at the output.

6. The driver system of claim 5, wherein the controlling comprises controlling the first resistance during a first edge transition of the output signal based on one of voltage feedback through a gate of the first n-type field effect transistor and current feedback through the output.

7. The driver system of claim 6, wherein the controlling comprises controlling the second resistance during a second edge transition of the output signal based on one of voltage feedback through a gate of the second n-type field effect transistor and current feedback through the output.

8. The driver system of claim 5, wherein the control after an edge transition controls at least one of the first resistance and the second resistance to correct for a mismatch between the first resistance and the second resistance.

9. The driver system of claim 1, further comprising a dual bootstrap system configured to track and correct for mismatch between the first and second resistances, wherein the dual bootstrap system comprises:

a high-side bootstrapped switch coupled at a non-gate terminal thereof between a second supply voltage and the high-side capacitor such that the high-side capacitor is coupled between the high-side bootstrapped switch and the output;

a high-side pre-driver configured to drive a gate of the first n-type field effect transistor, wherein respective supply power supply terminals of the high-side pre-driver are coupled to respective terminals of the high-side capacitor;

a low side bootstrapped switch coupled at a non-gate terminal thereof between the second supply voltage and the low side capacitor such that the low side capacitor is coupled between the low side bootstrapped switch and a second terminal of the supply voltage; and

a low side pre-driver configured to drive a gate of the second n-type field effect transistor, wherein a respective power supply terminal of the low side pre-driver is coupled to a respective terminal of the low side capacitor.

10. The driver system of claim 9, wherein the supply voltage and the second supply voltage are the same voltage.

11. In a drive system, a method, the drive system comprising: a first n-type field effect transistor coupled at its non-gate terminal between an output of the driver system and a first terminal of a supply voltage and configured to drive the output when the first n-type field effect transistor is activated; a second n-type field effect transistor coupled at its non-gate terminal between the output of the driver system and a second terminal of the supply voltage and configured to drive an output when the second n-type field effect transistor is activated; a high side capacitor coupled to an output of the driver system; and a low-side capacitor coupled to a second terminal of the supply voltage, the method comprising:

tracking, by the high-side capacitor and the low-side capacitor, a mismatch between a first resistance of the first n-type field effect transistor and a second resistance of the second n-type field effect transistor; and is

The mismatch is corrected by the high-side capacitor and the low-side capacitor.

12. The method of claim 11, further comprising:

tracking, by the high-side capacitor, a first offset occurring at a gate terminal of the first n-type field effect transistor; and is

Correcting a first offset at the output by the high side capacitor.

13. The method of claim 12, further comprising:

tracking, by the low-side capacitor, a second offset occurring at a gate terminal of the second n-type field effect transistor; and is

Correcting a second offset at the output by the low-side capacitor.

14. The method of claim 13, further comprising tracking, by the low-side capacitor, the second offset in a manner that corrects for the first offset.

15. The method of claim 11, wherein the tracking and correcting comprises controlling at least one of the first n-type field effect transistor and the second n-type field effect transistor during and after each edge transition of the output signal at the output.

16. The method of claim 15, wherein the controlling comprises controlling the first resistance during a first edge transition of the output signal based on one of voltage feedback through a gate of the first n-type field effect transistor and current feedback through the output.

17. The method of claim 16, wherein the controlling comprises controlling the second resistance during a second edge transition of the output signal based on one of voltage feedback through a gate of the second n-type field effect transistor and the current feedback through the output.

18. The method of claim 15, wherein the controlling after an edge transition controls at least one of the first resistance and the second resistance to correct for a mismatch between the first resistance and the second resistance.

19. The method of claim 11, further comprising tracking and correcting a mismatch between the first resistance and the second resistance by a dual bootstrap system, the dual bootstrap system comprising:

20. The method of claim 19, wherein the supply voltage and the second supply voltage are the same voltage.