NL2012315C2 - System-on-module comprising a field programmable gate array component and a connector for connecting the system-on-module to a carrier board, as well as a carrier board comprising a system-on-module. - Google Patents

System-on-module comprising a field programmable gate array component and a connector for connecting the system-on-module to a carrier board, as well as a carrier board comprising a system-on-module. Download PDF

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Publication number
NL2012315C2
NL2012315C2 NL2012315A NL2012315A NL2012315C2 NL 2012315 C2 NL2012315 C2 NL 2012315C2 NL 2012315 A NL2012315 A NL 2012315A NL 2012315 A NL2012315 A NL 2012315A NL 2012315 C2 NL2012315 C2 NL 2012315C2
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NL
Netherlands
Prior art keywords
pins
system
power
module
configurable
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Application number
NL2012315A
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Dutch (nl)
Inventor
René Paul Peter Zenden
Dirk Otto Heuvel
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Topic Embedded Systems B V
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Application filed by Topic Embedded Systems B V filed Critical Topic Embedded Systems B V
Priority to NL2012315A priority Critical patent/NL2012315C2/en
Priority to NL2012315 priority
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Publication of NL2012315C2 publication Critical patent/NL2012315C2/en

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Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748Structural details of configuration resources
    • H03K19/17772Structural details of configuration resources for powering on or off
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof

Abstract

System-on-Module, comprising a field programmable gate array, FPGA, component comprising configurable pins and power pins, a connector, comprising a plurality of connector pins for connecting said System-on-Module to a carrier board, wherein at least a subset of said connector pins is connected to at least a subset of said configurable pins, respectively, power grid for providing a plurality of voltage output levels to said power pins, wherein said FPGA component further comprises a power plane matrix, having a first side connected to each of said power pins, respectively, and a second side connected to each of said configurable pins, respectively, and wherein said configurable pins may be configurably connectable to each of said power pins using said power plane matrix, wherein the system-on-module may further comprise a programmable clock for providing a plurality of clock signals..

Description

Title

System-on-Module comprising a field programmable gate array component and a connector for connecting the System-on-Module to a carrier board, as well as a carrier board comprising a System-On-Module.

Background A System-on-Module (SOM) is a type of a single-board computer (SBC), which is a subtype of an embedded computer system. A System-on-Module is basically an extension of the concept of a System on Chip (SoC) and a System in Package (SiP). A System-on-Module is in the art also referred to as a Computer-on-Module.

Typically, a System-on-Module consists of a single Printed Circuit Board, and is to be mounted on a carrier board, motherboard, baseboard, or the like, via a backbone connector. The carrier board may comprise standard peripheral connectors for connecting busses present on the System-on-Module to the outside world. In some cases, instead of the carrier board, the System-on-Module may comprise one or more peripheral connectors. A design of a System-on-Module is usually centered on a single microprocessor having a memory, for example SDRAM, and several input/output interfaces, such as, for example, a Local Area Network (LAN), Universal Serial Bus (USB), Serial interface, Video interface, PCI-Express interface, etc. The present invention is directed to a System-on-Module which also incorporates a Field Programmable Gate Array (FPGA), or at least a Field Programmable Gate Array component.

System-on-modules are typically used to reduce development costs by reducing the design complexity of carrier boards, and as such reduce development time. System-on-modules are also used for increasing the flexibility of the design, as system-on-module may simply be replaced by another one, having another type of design. This may be relevant for relatively low volume applications. A System-on-Module may also be used in, for example, small or specialized applications requiring low power consumption or small physical size as may be needed in embedded systems. One of the typical applications is directed to video processing, i.e. video coding and/or decoding.

Using a System-on-Module may be advantageous as it may include cost savings, reduced risk, a variety of processor systems, decreased customer design requirements, a small footprint, and, since software developers may use off the shelf hardware with the same processing core as a finished product, the ability to perform hardware and software development in parallel.

Another advantage of using a System-on-Module, next to a carrier board, is that it simplifies design concepts. Design overhead may be introduced in case a carrier board is specifically directed to a certain application. Flexibility of the design is provided in case the actual processors and Input/output controllers are located on a System-on-Module, in stead of on the carrier board. Upgrading a processor, in such a case, is made much more simplified as the carrier does not need to be redesigned. The above is especially true in cases where the backbone connector of the System-on-Module remains compatible between the upgrades.

Typically, FPGA’s are designed for a specific, dedicated and single application. As such, every physical pin of the FPGA generally represent a predetermined functionality, i.e. it is used for data communication, as a connection to a power supply unit, for debugging purposes, etc. As these pins may be physically connected to pins of the backbone connector, also the functionality of these pins is predetermined.

Document US 2003/0107399 discloses an application specific integrated circuit (ASIC) comprising a standard cell, wherein the standard cell includes a plurality of logic functions. The ASIC further comprises at least one FPGA interconnect coupled to the plurality of functions, wherein the at least one FPGA interconnect can be configured to select one of the plurality of logic functions. In such a case, predefined logic present in the ASIC can be routed to any of the pins of the ASIC. A drawback of any of the known System-on-Modules comprising an FPGA component is related to the compatibility of these modules with different types of carrier boards. As explained above, the functionality of the pins of the backbone connector connected to the FPGA of the System-on-Module are predefined. In case a carrier board is unable to cope with the functionality provided on these pins, a mismatch between the carrier board and the System-on-Module exists, which can not be resolved easily.

It is therefore an objective of the present invention to provide for a System-on-Module comprising functionality such that the System-on-Module may be suitable for many different types of carrier boards.

It is a further objective of the invention to provide for a carrier board comprising a System-on-Module, wherein

Summary

In order to accomplish that objective, the invention, according to a first aspect thereof, provides for a System-on-Module, comprising a field programmable gate array, FPGA, component comprising configurable pins and power pins; a connector, comprising a plurality of connector pins for connecting the system-on-Module to a carrier board, wherein at least a subset of the connector pins is connected to at least a subset of the configurable pins, respectively; power grid for providing a plurality of voltage output levels to the power pins; wherein the FGPA component further comprises a power plane matrix, having a first side connected to each of the power pins, respectively, and a second side connected to each of the configurable pins, respectively, and wherein the configurable pins may be configurably connectable to each of the power pins using said power plane matrix.

The invention is based on the principle that the compatibility of a system-on-Module is further improved in case the electrical properties of the configurable pins are also configurable.

As such, the output voltage levels at the configurable pins may be amended by selectively connecting these configurable pins to different power pins of the FPGA component. A user is then, for example, able to configure the reconfigurable pins, i.e. input and/or output pins, to the power plane matrix to thereby make sure that the input/output levels are compliant to the required standards.

Configurably connectable, according to the present invention, comprises that connections between the power input pins and the configurable pins may be set by an end user.

These configurable pins may be used, for example, for General Purpose Input Output connections, GPIO, Inter IC-bus, 12c, Universal asynchronous receiver/transmitter, UART, Serial Peripheral Interface, SPI, etc., each of which may require a different voltage output and/or input level. As such, the inventors noted that it is not only sufficient to make sure that the functionality may be configurably connected to the configurable pins, but that also these voltage levels should be made configurable. Using the power plane matrix according to the present invention, it is possible to amend, i.e. alter, the output/input voltage levels of each of the configurable pins, such that any of the above mentioned standards may be allocated to any of the configurable pins.

In an embodiment of the present invention, the electrical properties of the configurable pins may be configurable, wherein the electrical properties comprise at least one of impedance, voltage, frequency, drive power, I/O technology of said configurable pins. These electrical properties may be configured by, for example, using any of the available voltages at the power input pins of the FPGA component.

In another embodiment of the invention, each of the configurable pins are connected to functional blocks of said FPGA.

The FPGA component is a semiconductor device comprising programmable logic components and programmable interconnects. A hierarchy of programmable interconnects, in the form of functional blocks, allows the logic blocks of an FPGA component to be interconnected. These logic blocks and interconnects can be programmed after the manufacturing process by the customer/designer so that the FPGA component can perform any logical function.

In an example of the present inventions, the FPGA component is a reconfigurable FPGA, such that the functionality of the FPGA, i.e. the functional blocks, may be configured during run time. As such, even at run time, the functionality coupled to any of the configurable pins may be configured by an end user, as the reconfigurable hardware device provides the possibility to amend the functionality, and as the power plane matrix according to the present invention allows the voltage output and/or input levels to be configured, i.e. set.

In an embodiment of the present invention, the power grid comprises a plurality of voltage regulators, each of which providing a different output level. A voltage regulator is designed to automatically maintain a constant voltage level. Depending on the design, a voltage regulator may be used to regulate one or more Direct Current voltages. The power grid may comprise a plurality of different types of switched power supplies, each of which arranged to provide an output voltage to one of the power pins of the FPGA component.

In another embodiment, the plurality of voltage regulators are each configurable such that said output voltage level may be configured. For example, the power grid may be arranged to provide a 5V, a 3.3V and a 2.5V to the power pins of the FPGA component. In case an end user wants to implement a standard which required a different operating voltage as the ones disclosed above, the user may configure the voltage regulator such that at least one of these three voltages is amended to the desired output voltage. This could be helpful, for example, in case the end user want to implement, for example, a 1,8V UART. In such a case, the end user needs to amend one of the three voltages, by configuring the power grid to output 1.8V to one of the power pins of the FPGA component. Next, the end user may configure the power plane matrix such that the 1.8V is connected to configurable pins intended to be used for the 1.8V UART.

The output levels of the voltage regulators may be configured by control means, for example present in the FPGA component. In another example, the control means are arranged as a software architecture running on any of controllers present on the system on module.

In another embodiment, the FPGA component is a reconfigurable FPGA arranged for reconfiguring functionality of functional blocks in said FPGA during run-time, and wherein each of the configurable pins may be selectably connected to functional blocks in said FPGA.

In an example, the FPGA component may be implemented in a single casing, wherein the FPGA component is comprised, or wherein at least one processor and the FPGA component are comprised, such as, for example, an FPGA with integrated ISP or pure FPGA fabric with a softcore Instruction Set Processor, ISP, device, or may be implemented in multiple casings, for example at least one processor separated from the FPGA component.

In yet another embodiment, the FPGA component comprises reconfiguring means arranged for selectably connecting the configurable pins to the power pins, respectively.

In a further embodiment, the FPGA component further comprises safety means for preventing that a configurable pin may be connected to multiple power pins using said power plane matrix.

One of the advantages hereof is that it is not possible to create a shortcut by directly connecting multiple voltage levels inputted at the power input pins to each other. As such, it is possible to, using the power plane matrix, connect a single voltage level to multiple configurable pins, but it is not possible to connect a single configurable pin to multiple power input pins.

In a second aspect, the invention provides in a carrier board, comprising a carrier board connector, and a System-on-Module according to any of embodiments disclosed above, connected to the carrier board via the carrier board connector.

Brief description of the Drawings

Figure 1 shows, in a schematic form, a typical layout scheme of a conventional System-on-Module mounted on a carrier board, illustrating the drawback in compatibility and/or flexibility in functionality.

Figure 2 shows, in a schematic form, a typical layout scheme of an FPGA component according to the present invention.

Detailed description

Figure 1 shows, in a schematic form, a typical layout scheme of a conventional System-on-Module 1 mounted on a carrier board 29, illustrating the drawback in compatibility and/or flexibility in functionality.

Here, it is clear that the flexibility of the FPGA is decreased as the voltages of the inputs and/or output are set on the carrier board 29.

The System-on-Module 1 comprises a field programmable gate array, FPGA, component 2 comprising configurable pins 3 and power pins 4. The FPGA component 2 may further comprise pins having a predefined functionality (not shown).

Further, a connector 6 is present, which connector 6 comprises a plurality of connector pins 7 for connecting the System-on-Module 1 to the carrier board 29, wherein at least a subset of said connector pins is connected to at least a subset of said configurable pins 3, respectively;

In the present example, the FGPA component 2 is comprised in a single casing along with a processing system 8. The processing system 8 comprises, for example, an ARM processor 9 connected to a logical interconnect 10.

The interconnect 10 is connected to a plurality of Input/output standard functionality blocks, such as a SPI 11, a I2C 12, a UART 13 or a USB 14. These functionality blocks 11, 12, 13, 14 are connected to a processor I/O multiplexer 15 for connecting these blocks 11, 12, 13, 14 to input and/or output pins of the processing system 8. Further, a Flash controller 16 is connected, i.e. for a NOR, NAND, SRAM, etc.

Different types of ports may be present for connecting the processing system 8 to the FPGA component 2, such as general purpose ports 17 and EMIO port 18.

The FPGA component 2 is further arranged with power pins 4, for connecting a power supply 20 to the FPGA component 2. The power supply 20 is used for powering the FPGA component 2 and/or the processing system 8.

Configurable pins 3 are comprised at the FPGA component 2, which configurable pins 3 may be arranged to be involved in a particular communication standard, and are connected to each the connector pins 7 of the connector 6.

For example, configurable pins 21 are configured as GPIO pins for providing general purpose Input and/or output to the carrier board 29. In the present example, to alter the voltage output level of the signals at the configurable pins 21, a further power supply 24 is connected to these pins, for level conversion. As such, even if the FPGA component 2 outputs a voltage of, for example, 3.3V, these voltages may amended by the further power supply 24, such that these output voltages are in line with what the carrier board is expecting.

In the present example, configurable pins 22 are connected to an even further power supply 25, which power supply is arranged to convert the voltage levels on the configurable pins 22 to 2.5V.

In the present example, the all the power supplies 20, 24, 25 are present on the carrier board 29. The reason therefor is that this simplifies the design of the system-on-module, as the level conversion is performed on the carrier board 29.

The above is an excellent example of a drawback of the prior art. In case an end user wants to use configurable 22 for the GPIO connection connected to the configurable pins 21, a problem may occur. The output voltage of the further power supply 24 is not compatible with the output voltage of the even further power supply 25. As such, the functionality of the configurable pins 21, 22 can not be swapped. As such, the flexibility of the FPGA is at least partly decreased.

In another example, a level conversion element 26 may be used for converting the input and/or output voltage levels of the configurable pins 23.

Figure 2 shows, in a schematic form, a typical layout scheme of an system on module 51 according to the present invention.

Here, the same reference numerals are used for indicating the same, or a similar function as compared to the elements, blocks and/or aspects as compared to the ones shown in figure 1.

Instead of the further power supply 24 and the even further power supply 25, present on the carrier board 29 of figure 1, the system on module 51 comprises a power grid 61, providing a variety of output levels to the power pins 52 of the FPGA component 53.

The power grid 61 may be configured, i.e. set, using a control interface 67, which connects from the power grid 61 to the processing system 8 via the processor I/O multiplexer 15. In another example, the control interface is not connected to the processing system 8 but directly to the FPGA component 53.

In order to amend the output levels of the different configurable pins 54, 55, 56, a power plane matrix 57 is arranged in the FPGA component 53. One side of the power plane matrix 57 is connected to the each of the power input pins 52 of the FPGA component 53, and another side of the power plane matrix 57 is connected to each of the configurable pins 54, 55, 56.

The power plane matrix 57 is arranged to be configured by a user, for example using a software architecture, in the sense that connection from any of the configurable pins 54, 55, 56, may be connected to the power input pins 52 of the FPGA component. In the present example a couple of these connections 60 are made, indicating that the output voltage levels of the configurable pins 54, 55, 56 are each different as these configurable pins are each connected to a different input power pin 52.

One of the advantage of the present example is that the system on module is much more flexible and is compatible with a variety of carrier boards. Another advantage is that it is possible to amend the function of the design, including the respective votlages at the input and/or output pins. Functionality of input and/or output pins defined at the carrier board may be taken in to account when assigning the functionality of the configurable pins of the FPGA component. Complete freedom is provided as any functionality may be assigned to any of the configurable pins, including the working voltage, i.e. the output voltage required at these configurable pins.

The present invention has been explained in the foregoing by means of a number of examples, As those skilled in the art will appreciate, several modifications and additions can be realized without departing from the scope of the invention as defined in the appended claims.

Claims (11)

  1. A system-on-module ("system-on-module"), comprising: a field-programmable gate array (FP), FPGA, component comprising configurable pins and power pins; a connector comprising a plurality of connector pins for connecting the system-on-module to a base board ("carrier board"), wherein at least a subset of the connector pins is connected to at least a subset of the configurable pins, respectively; power grid (power grid) for providing a plurality of power output levels to the power pins; wherein the FGPA component further comprises a power plane matrix, with a first side connected to each of the power pins, respectively, and a second side connected to each of the configurable pins, respectively, and wherein the configurable pins may be configured to be connected to each of the power pins using the power plane matrix.
  2. The system-on-module according to claim 1, wherein each of the configurable pins are connected to functional blocks of the FGPA.
  3. The system-on-module according to any of the preceding claims, wherein the power grid comprises a plurality of voltage regulators, each of these providing a different output level.
  4. The system-on-module according to claim 3, wherein the plurality of voltage regulators are each configurable such that the output voltage level may be configured.
  5. The system-on-module according to claim 4, wherein the voltage regulators are each configurable by means of control means.
  6. The system-on-module according to any of the preceding claims, wherein the FPGA component is a reconfigurable FPGA adapted to reconfigure functionality of functional blocks in the FPGA during operating time ("run-time").
  7. The system-on-module according to any of the preceding claims, wherein each of the configurable pins may be selected to be connected to functional blocks in the FPGA.
  8. A system-on-module according to any one of the preceding claims, wherein the configurable pins may be configurably connected to each of the power pins using the power plane matrix during operating time.
  9. The system-on-module according to any of the preceding claims, wherein the FPGA component comprises reconfiguration means adapted to selectively connect the configurable pins to the power pins, respectively.
  10. The system-on-module according to any of the preceding claims, wherein the FPGA component further comprises security means for preventing a configurable pin from being connected to multiple power pins using the power plane matrix.
  11. A base board (carrier board), comprising: a base board connector, and a System-on-Module according to any of claims 1 to 9, connected to the base board via the base board connector.
NL2012315A 2014-02-24 2014-02-24 System-on-module comprising a field programmable gate array component and a connector for connecting the system-on-module to a carrier board, as well as a carrier board comprising a system-on-module. NL2012315C2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
NL2012315A NL2012315C2 (en) 2014-02-24 2014-02-24 System-on-module comprising a field programmable gate array component and a connector for connecting the system-on-module to a carrier board, as well as a carrier board comprising a system-on-module.
NL2012315 2014-02-24

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL2012315A NL2012315C2 (en) 2014-02-24 2014-02-24 System-on-module comprising a field programmable gate array component and a connector for connecting the system-on-module to a carrier board, as well as a carrier board comprising a system-on-module.
PCT/NL2015/050112 WO2015126253A1 (en) 2014-02-24 2015-02-20 System-on-module comprising a field programmable gate array component and a connector for connecting the system-on-module to a carrier board, as well as a carrier board comprising a system-on-module.

Publications (1)

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NL2012315C2 true NL2012315C2 (en) 2015-08-25

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NL2012315A NL2012315C2 (en) 2014-02-24 2014-02-24 System-on-module comprising a field programmable gate array component and a connector for connecting the system-on-module to a carrier board, as well as a carrier board comprising a system-on-module.

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030107399A1 (en) * 2001-12-10 2003-06-12 International Business Machines Corporation Method and system for use of an embedded field programmable gate array interconnect for flexible I/O connectivity
US20050088201A1 (en) * 2001-02-16 2005-04-28 Nallatech, Ltd. Programmable power supply system

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8201127B1 (en) * 2008-11-18 2012-06-12 Xilinx, Inc. Method and apparatus for reducing clock signal power consumption within an integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050088201A1 (en) * 2001-02-16 2005-04-28 Nallatech, Ltd. Programmable power supply system
US20030107399A1 (en) * 2001-12-10 2003-06-12 International Business Machines Corporation Method and system for use of an embedded field programmable gate array interconnect for flexible I/O connectivity

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