NL2007941C2 - Qualification of silicon wafers for photo-voltaic cells by optical imaging. - Google Patents
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- 235000012431 wafers Nutrition 0.000 title description 59
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title description 8
- 238000012634 optical imaging Methods 0.000 title description 8
- 229910052710 silicon Inorganic materials 0.000 title description 8
- 239000010703 silicon Substances 0.000 title description 8
- 238000012797 qualification Methods 0.000 title description 4
- 238000000034 method Methods 0.000 claims description 41
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- 238000012545 processing Methods 0.000 claims description 20
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02S—GENERATION OF ELECTRIC POWER BY CONVERSION OF INFRARED RADIATION, VISIBLE LIGHT OR ULTRAVIOLET LIGHT, e.g. USING PHOTOVOLTAIC [PV] MODULES
- H02S50/00—Monitoring or testing of PV systems, e.g. load balancing or fault identification
- H02S50/10—Testing of PV devices, e.g. of PV modules or single PV cells
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
- G01N21/9501—Semiconductor wafers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
- G06T7/0002—Inspection of images, e.g. flaw detection
- G06T7/0004—Industrial image inspection
- G06T7/0006—Industrial image inspection using a design-rule based approach
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/30—Subject of image; Context of image processing
- G06T2207/30108—Industrial image inspection
- G06T2207/30148—Semiconductor; IC; Wafer
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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Description
Title: Qualification of silicon wafers for photo-voltaic cells by optical imaging
Field of the invention
The invention relates to qualification of silicon wafers by optical imaging. Moreover, the invention relates to a method of measuring properties of a 5 semi-conductor substrate for use in manufacturing a photo-voltaic cell, and a method of manufacturing a photo-voltaic cell.
Background 10 Photovoltaic cells, such as solar cells may be manufactured from crystalline wafers of semi-conductor material like silicon. Crystalline wafers contain dislocations, for example as a result of thermal stresses over the ingot during the crystal growth process. The dislocation density varies over the ingot and the density and spatial distribution of dislocations may vary from wafer to 15 wafer. After a wafer has been processed to a solar cell, these dislocations give rise to lower lifetimes of the minority charge carriers. The lower lifetime is a result from imperfect crystal structure or from enhanced concentration of metal ions that are not gettered or passivated during manufacturing of the solar cell. Lower life time of minority charge carriers results in reduced 20 performance of the finished solar (photovoltaic) cell.
It is desirable to identify wafers or regions of wafers that are likely to contain a high dislocation density. This may be used to reject wafers, or to classify the quality of the manufactured cells on the basis of wafer properties. For cost effectiveness, qualification of wafers should take place as early as 25 possible in the solar cell manufacturing process, and should be real-time (i.e. executable without need to delay the manufacturing process other than for capturing data) and non-intrusive.
2
Identification of dislocation areas is possible by various methods, such as photo luminescence (PL), optical imaging (01) and electroluminescence (EL). PL and 01 are methods that can be applied on bare wafers. EL requires the presence of electrodes and is therefore usually only applied on finished 5 solar cells. For PL sample preparation is not strictly required but better images are often obtained after applying some steps that are part of the solar cell processing such as etching, or applying the emitter layer.
Optical imaging can easily be combined with well-known methods of digital image processing. Quantification of the optical image properties can 10 then be coupled to models that predict the performance on the basis of the presence of dislocations.
Characterization of wafers by optical imaging has been pursued at NREL, by the group of B. Sopori. High speed characterization of wafers using a camera to obtain an optical image is described in an article titled “A 15 reflectance spectroscopy-based tool for high-speed characterization of silicon wafers and solar cells in commercial production”, Photovoltaic Specialists Conference (PVSC), 2010 35th IEEE, 002238-002241 (2010), by B. Sopori et al. The emphasis is on the wide range of data that can be obtained in this way. Sopori has described the effect of dislocations through a 2D network model. In 20 an article titled “Use of optical scattering to characterize dislocations in semiconductors”, Appl.Opt., 27, 4676-4683 (1988) Sopori has described that the degree of scattering can be a basis for methods to measure the dislocation density, the dislocation size and to make mappings of dislocations.
The use of a flatbed scanner to measure the optical reflectance of a 25 wafer was recently described by Korte et al. in an article titled “Measurements of effective optical reflectivity using a conventional flatbed scanner-Fast assessment of optical layer properties”, Solar Energy Materials and Solar Cells, 92, 844-850 (2008). A feature is that the flatbed scanner or photocopier catches the light that is scattered, i.e. specular reflections are not included. A 30 photocopier and a flatbed scanner are similar devices that allow fast scanning 3 of the entire surface. Alternatively a camera can be used. A camera has the opposite properties: light falls on the dislocations from all directions and as a result of the scattering properties a dislocation has some reflection in the direction of the camera.
5 For optical imaging an etching process is required. Specially designed etches, containing mixtures of acids like HF, nitric acid, acetic acid been developed to optimize the quality of optical images. The etching process results in a rougher texture at the dislocation sites which means that reflected light from these locations is highly scattered. Without such an etching process 10 the prior art does not provide for reliable dislocation measurements.
Electroluminescence methods and optical imaging that require special etchings are not suitable for use in a manufacturing process. The PL method is costly, and when applied in a stage before emitter diffusion does not seem able to distinguish between persistent defects and certain defects that 15 disappear in further processing.
Summary
Among others, it is an object to provide for a method of measuring 20 dislocation density on wafers that is compatible with use of the wafers in a manufacturing process and produces reliable measurements of dislocation density.
A solar cell manufacturing process according to claim 1 is provided. Herein optical inspection is used during a manufacturing process. It has been 25 found that when an image of scattered light, rather than specularly reflected light is obtained and the image is processed to emphasize edges (e.g. to detect image positions where edges are detected), it is possible to estimate defect density after an etch step that is used as part of the solar cell manufacturing process. The number of defects may be estimated as the number of image 30 points where edges have been detected, for example. In this way inline 4 inspection can be used to control the application of subsequent further steps of processing during the manufacture of the solar cell.
In an embodiment application of a metallization pattern during the manufacturing process is adapted dependent on a prediction of performance.
5 In this way the metallization pattern and/or orientation of the metallization pattern that yields best predicted performance can be selected and the steps of further processing may be adapted to apply the selected pattern and/or orientation.
10 Brief description of the drawing
These and other objects and advantages will become apparent from a description of exemplary embodiments with reference to the following figures.
15 Figure 1 shows an optical inspection system
Figure 2 shows a flow-chart of a manufacturing process
Detailed description of exemplary embodiments 20 Figure 1 shows an optical inspection system comprising a wafer support table 10, a light source 12, a detector 14, a scanning mechanism 16, and a computer system 17. By way of example a wafer 18 is shown on wafer support table 10. Light source 12 may be a linear light source for example, configured to generate light along a line on wafer 18. Similarly, detector 14 25 may be a line detector, configured to measure light intensities from wafer 18 at a series of positions along the line. Light source 12 and detector 14 are positioned relative to each other so that the direction of light from light source 12 to wafer and light to and detector 14 are at mutually different angles with respect to the normal to the surface of wafer 18 (that is at angles so that 30 detector 14 does not capture specularly reflected light, which occurs when the 5 detector 14 and light source 12 lie in planes through the line that are on opposite sides to a normal plane through the line that is normal to the surface of wafer 18, at the same angle to that normal plane). Detector 14 has an output coupled to computer system 17. Computer system 17 is coupled to 5 scanning mechanism 16 to control scanning, or at least receive information that indicates positions during scanning.
Scanning mechanism 16 is configured to scan support table 10 and the combination of light source 12 and detector 14 relative to each other. Support table 10 may be moved in a direction transverse to the line of light on 10 wafer 18.
Figure 2 shows a flow-chart of a manufacturing process. In a first step 21a wafer is sawed. In a second step 22 an etch process is performed using a wet-chemical process, with an acidic etchant containing for example an aqueous mixture of acids. Such an etching process produces pits in the surface 15 at the position of dislocations in a silicon wafer. An etching process that is a conventional part of solar cell manufacture may be used for this purpose. For example, the etching step may be an etching step for etching away saw damage and/or to create a 2D texture on the surface of the wafer. A wet-chemical process, with as etchant an aqueous mixture of acids like hydrofluoric 20 acid, nitric acid or acetic acid may be used for example. Such a process forms a surface texture (pattern of height variations) that is sensitive to dislocation areas. Preferably an etchant is used that forms etch pits on the surface of the wafer in areas containing dislocations.
In a third step 23 computer system 17 captures output signals from 25 detector 14 for points along the line on wafer 18 and for successive lines during scanning. The captured signals define an image of wafer 18.
In a fourth step 24 computer system 17 applies an edge detection operator to the image. As is known per se, edges are sharp, abrupt changes in intensity in the image. A well-known way to detect edges is the Canny edge 30 detection algorithm, described on pages 719-725 of the book “Digital Image 6
Processing” by R. C. Gonzalez and R. E. Woods, published by Pearson Education International, 2008. The Canny edge detection comprises filtering the image with a plurality of gradient filters (e.g. four filters), optionally in combination with smoothing the image, e.g. by a Gaussian filter, or a FIR filter 5 that approximates a Gaussian filter response. A gradient filter is designed to produce output signals for image locations in proportion to the intensity gradient in a predetermined direction. A FIR filter with a 5x5 pixel may be used for example. In the Canny edge detector the plurality of gradient filters contains filters for gradients in different directions (e.g. a horizontal direction, 10 a vertical direction and two diagonal directions (/ and \)). An edge signal may be obtained by combining, at each pixel position, the amplitudes of the results that are obtained by applying the gradient filters to the image respectively.
The result represents an edge magnitude as a function of pixel position. Result values at pixel positions where the result value is not a local maximum are 15 suppressed. A double (low and high) thresholding operation may be applied to the results to reduce the number of false edge points. In practice, the parameters of these operations may be optimized for the characterization of wafers. These operations transform the image to a processed image called the Canny edge image with pixels that have a first value at locations where edges 20 are detected (values between the thresholds) and a second, different value where no edge has been detected.
In a fifth step 25 the Canny edge image is used to calculate the Canny edge fraction (CEF = number of edge pixels in image / total number of pixels of image) or to make a (binary) map of the dislocation distribution. In an 25 embodiment mapping the latter may comprise: - dividing the image into sub-blocks and calculating the number of edges per sub-block of the image - identifying blocks for which the edge density exceeds a further threshold, as dislocation areas.
7
Instead of using binary edge detections, edge signals may be used, such as the outputs from the gradient filters and the values of the edge signals may be used as a weight with which the corresponding edge point contributes to a count of edges. In an alternative embodiment, fourth step 24 5 another edge detection algorithm may be used than the Canny algorithm. The parameters of such an edge detection algorithm may also be tuned.
In an embodiment fifth step 25 may comprise a weighting operation, wherein the numbers of edges are multiplied by weights that depend on position in the image. In a further embodiment selected areas of the image 10 may be mask out (corresponding to weights that are either one or zero).
A line filter may be applied to the Canny edge image before calculating the Canny edge fraction, to remove detected linear edges that do not relate to dislocations, for example by testing Canny edge image values of a set of pixels positions along a line, and suppressing the edge detections if edge 15 points have been detected for all pixel positions along a segment of predetermined length along this line, or all pixel positions but no more than a predetermined number op pixel positions that do not form a continuous sub-segment.
In an alternative embodiment, fourth step 24 comprises using a 20 gradient method instead of Canny edge detection. Gradient methods are known from e.g. pages706-714 of the book by R. C. Gonzalez and R. E. Woods. Fourth step 24 may then comprise applying a highpass filter (e.g. Laplacian mask) to the captured image, and fifth step 25 may then comprise - computing a histogram of the filtered image (frequency vs.
25 intensity value), or computing a plurality of such histograms, each for a different sub-block - computing an integral of the intensity values of the histogram between a low and a high intensity value for the histogram, or for each histogram 8
In a sixth step 26 the information from fifth step 25 is used to obtain performance prediction. Correlation may be used for this purpose. Different predicted performance values may be pre-stored in association with pre-stored different density values, and the results of fifth step may be used to retrieve 5 associated predicted performance values. In an embodiment, an averaged density of dislocations obtained from fifth step 25 (number of edge pixels in image divided by the total number of pixels of image.) is used to retrieve predicted performance values. In another embodiment the average density as calculated by the number of dislocations sub-blocks divided by the total 10 number of sub-blocks or the full spatial mapping of dislocation sub-blocks is used to retrieve predicted performance values. This introduces two additional parameters that can be tuned, i.e. the block size and the threshold that selects the dislocation blocks.
In a seventh step 27 an evaluation is performed based on the 15 predicted performance, for example to control further use of the wafer. The predicted performance may be compared with a pre-established threshold for the performance.
If the wafer meets the threshold, the wafer may be processed using further steps of a predetermined manufacture process to manufacture a solar 20 cell, which are known per se. If not, a different treatment may be given to the wafer. Moreover it may save costs if wafers can be rejected before application of further steps, dependent on the test results.
The further steps may include an emitter diffusion step for example, wherein the substrate is doped to create a p-n junction. The etching step may 25 be a last etching step before emitter diffusion. Preferably, the etching process of second step 22, after which image capture step 23 is performed, is an earliest etching step e.g. a step for removal of saw damage.
Emitter diffusion may have the effect of obscuring the dislocations at the surface, but the dislocations may run through the wafer, and therefore 30 they may continue to give rise to problems even if the dislocations are 9 obscured. Similarly, later steps that add layers on the silicon surface may obscure dislocations. Therefore it is preferred to capture the image when the captured silicon surface does not contain an emitter diffusion, or more preferably also not other diffusion such as a back or front surface field 5 diffusion, or later added covering layers such as a dielectric layer or a conductor layer.
In some manufacturing processes the doping to create the p-n junction is performed by doping the substrate on both sides, after which the doped layer from one of the sides is removed by etching, to obtain a material 10 with a single junction. The method can also be applied by performing image capture step 23 to capture the image of the etched surface obtained by such a single-side etching step. Although this is after application of the emitter, the one sided etch ensures that a surface without emitter diffusion can be captured.
15
Performance prediction algorithm A prediction of the cell performance can predict values of a performance property such as the open circuit potential Voc of the solar cell 20 once manufactured, the cell efficiency q once manufactured, or both. The efficiency is the most relevant characteristic for evaluating performance, but the Voc is usually easier to calculate and will probably capture most of the effects related with low minority charge carrier life times.
In an embodiment a “heuristic model” may be used where a linear 25 regression of the performance property vs. the dislocation fraction is used. The dislocation fraction may be obtained directly from the Canny edge calculation, or from an intermediate mapping based on sub-blocks of the Canny image, by calculating the associated performance property value of the Canny edge calculation according to the linear regression.
10
In an embodiment an analytical model may be used, in which the physics of the photovoltaic cell is represented. This can be done on the basis of an equivalent circuit for a PV cell.
A first example involves applying the equations for the single-diode 5 equivalent circuit of a solar cell. A distinction is made between areas without dislocations, which are assigned a first (low) diode dark saturation current density, and areas with dislocations, which are assigned a second (higher) diode dark saturation current. The surface averaged value of the diode dark saturation current is then used as a parameter for the equivalent circuit, from 10 which a value of the performance property is computed.
Furthermore, an improved value of the efficiency q can be obtained by the same procedure but now including the series resistance of the emitter layer and the metallization pattern. In addition the locally generated photon current density can be made dependent on the presences of dislocations. This 15 may be done similarly to the approach followed for the dark saturation current: a certain value is assigned to areas without dislocations, and a lower value is assigned to areas with dislocations. The model may be extended by additional elements in the equivalent circuit such as shunts, additional diodes, series resistances, contact resistances etc.
20 In a second example use may be made of a model that describes the solar cell as a two-dimensional network of parallel solar cell single-diode circuits. The network has diodes of a first and second type (bad and good), and diodes at different positions in the network are selected to be of the first or second type dependent on whether sub-blocks at corresponding positions in the 25 image is identified as an edge block or nor the corresponding to the maps described above.
In the model this diode network may be combined with a model of a metallization pattern that may be applied later during manufacture. In this model, the circuits are connected through series resistances, which is the 30 combined effect of the metallization and emitter resistance. This defines in a 11 partial differential equation with the cell voltage fixed at the points of current collection as boundary condition. The differential equation may be solved numerically with an appropriate method such as a Finite Element Method.
The dark saturation current may be used as a property that 5 characterizes the dislocation but also in this case the model can be extended by using a location dependent photon generation current density and by adding additional elements into equivalent circuit (see 2c above). This particular type of modeling enables the use the spatially resolved information on the dislocations.
10 This makes it possible to predict the effect of different possible metallization patterns dependent on the dislocations. In articles by Sopori et al. “Performance limitations of mc-Si solar cells caused by defect clusters”, ECS Trans., 18, 1049-1058 (2009) and “Influence of distributed defects on the photoelectric characteristics of a large-area device”, J.Cryst.Growth, 210, 375-15 378 (2000), such a network model has already been described, in relation with studies of the effects of dislocations on solar cell performance.
Evaluation step 20 The predicted performance is obtained based on the image captured after the etching step early in the manufacturing process and before remaining steps in the process to manufacture a solar cell. The predicted performance of the wafer is compared with a pre-established threshold. It may be tested whether the predicted efficiency is a above such a threshold, whether the 25 predicted Voc is above such a threshold, or both. If the predicted performance of a wafer meets the threshold, the remaining steps of the process are performed in a predetermined way.
If the predicted performance of a wafer does not meet the pre-established threshold for the performance, one of several measures can be 30 taken 12 1) The wafer may be rejected, i.e. not subjected to the remaining processing steps needed to manufacture a solar cell.
2) The wafer can be sent to a different production line, for lower grade wafers.
5 3) The wafer may be subjected to a production process that is adapted dependent on the predicted performance.
In an embodiment of the latter case the process steps for applying metallization to the wafer may be adapted. For example, when a “H” or pattern or interdigitated “E” patterns of metallization is or are used, the 10 pattern may be applied to the wafer at a zero or ninety degree rotation relative to the wafer (i.e. the wafer may be rotated before applying the steps to apply the metallization, or the equipment used to apply the pattern, such as a printing screen, may be rotated, or a different printing pattern may be used). The rotation may be selected dependent on the prediction of performance 15 obtained with models with differently rotated metallization patterns, the rotation with best predicted performance being selected. This may result in better performance. Studies with the 2D model network have shown that the position of dislocation with respect to the metallization can be of significant importance.
20 In an embodiment of adaptation a spacing of fingers of the metallization pattern may be adapted. The spacing may be selected dependent on the prediction of performance obtained with models with metallization patterns with differently spaced fingers, the spacing with best predicted performance being selected. This may be combined with selection of the 25 rotation, or it may be applied using a predetermined rotation.
In an embodiment a metallization application technique such inkjet printing may be used, which allows for more variation in the metallization pattern than just rotation and/or spacing. A pattern may be selected dependent on the prediction of performance obtained with models with that 13 metallization pattern, the pattern with best predicted performance being selected.
The monitoring of wafer quality with concurrent performance prediction can identify instabilities or problems in the production, i.e. it can 5 distinguish between such issues and wafer quality variation. In an embodiment, performance (e.g. Voc or efficiency) is measured after completing the manufacturing process, or at a manufacturing stage later than the stage where the image is captured. The measured performance of a wafer is compared with the prediction of the performance of the wafer and if a 10 deviation exceeds a threshold, an alarm is generated, indicating possible malfunction of the production process. Without use of the prediction, such malfunction may be undetectable because it cannot be distinguished from the effect of unknown wafer defects.
Feed-back can be given to suppliers of wafers regarding the quality, 15 recommendations for improvement of the crystal growth process can be given.
Claims (12)
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NL2007941A NL2007941C2 (en) | 2011-12-09 | 2011-12-09 | Qualification of silicon wafers for photo-voltaic cells by optical imaging. |
CN201280067547.2A CN104067512A (en) | 2011-12-09 | 2012-12-07 | Qualification of silicon wafers for photo-voltaic cells by optical imaging |
PCT/NL2012/050858 WO2013085385A1 (en) | 2011-12-09 | 2012-12-07 | Qualification of silicon wafers for photo-voltaic cells by optical imaging |
TW101146044A TW201330136A (en) | 2011-12-09 | 2012-12-07 | Qualification of silicon wafers for photo-voltaic cells by optical imaging |
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US9996766B2 (en) | 2015-05-01 | 2018-06-12 | Corning Incorporated | Imaging-based methods for detecting and measuring defects in extruded cellular ceramic articles |
WO2016187180A1 (en) | 2015-05-21 | 2016-11-24 | Corning Incorporated | Methods for inspecting cellular articles |
CN105719984A (en) * | 2016-02-22 | 2016-06-29 | 成都振中电气有限公司 | Solar cell performance detection system |
JP6341229B2 (en) * | 2016-05-30 | 2018-06-13 | 株式会社Sumco | Crystal defect evaluation method, silicon wafer manufacturing method, and crystal defect evaluation apparatus |
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CN114975157B (en) * | 2022-08-01 | 2022-10-21 | 波粒(北京)光电科技有限公司 | Photoluminescence detection device of solar cell |
CN117241483B (en) * | 2023-10-25 | 2024-04-12 | 广东达源设备科技有限公司 | Spraying device and method for circuit board production |
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