NL2006164C2

NL2006164C2 - A method of manufacturing a solar cell and solar cell thus obtained.

Info

Publication number: NL2006164C2
Application number: NL2006164A
Authority: NL
Inventors: Johannes Reinder Marc Luchies; Robertus Adrianus Maria Wolters
Original assignee: Tsc Solar B V
Priority date: 2011-02-08
Filing date: 2011-02-08
Publication date: 2012-08-09

Description

A method of manufacturing a solar cell and solar cell thus obtained

FIELD OF THE INVENTION

5 The invention relates to the manufacturing of a solar cell

The invention further relates to a solar cell thus obtained. BACKGROUND OF THE INVENTION

10 Solar cells are large area semiconductor devices which convert radiation (i.e. sunlight) into electricity. One important class of solar cells is the group of back-contacted solar cells, meaning that both terminals to the two oppositely doped regions - the emitter region as the 15 emitter and the field region responsible for the back surface field - of the solar cells are placed on the second, i.e. rear or non-illuminated surface of the solar cell. This class of solar cells avoids shadowing losses caused by the front metal contact grid on standard solar cells. Suitably, 20 an emitter is provided on the front or first side (the terms side and surface are hereinafter used exchangably) of the semiconductor substrate (hereinafter also referred to as substrate). Therewith it is achieved that the junction between the oppositely charged regions in the substrate is 25 close to the front surface which receives the incoming radiation. Suitably, the emitter extends along walls of through-holes through the substrate to the second side of the substrate. Conductors are provided in the through-holes - defining vias - for coupling the one or more emitter 30 regions to first terminals on the second side of the substrate. This solar cell concept is known as a wrap through cell, for instance a metal wrap through (MWT) cell or an emitter wrap through (EWT) cell.

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An example of such a solar cell is known from US3.903.428. This patent proposes the vias for the conductors. Patent EP0985233 is another example. After creating the via, phosphorous or any other dopant is 5 introduced in both surfaces of the substrate including the walls of the vias in order to create a homogeneous and continuous emitter on both surfaces of the substrate. This results in a double carrier collecting junction, since the junction is not only present near the front surface, but 10 also near the back surface, and hence is double. The patent gives the example wherein the substrate is p-type doped and the emitter is n-type doped. Possible techniques to form an n-emitter include the screen printing of a phosphorous containing paste on the areas of the cell where an emitter 15 is to be created; the use of a gaseous source such as POCI3; spin-on and spray-on deposition techniques. Techniques such as ion implantation would be possible but not at an industrial level yet; the solar cell is a large scale and relatively cheap product per m2 surface area, when compared 20 to other silicon based products such as integrated circuits.

When extending the emitter into the through-holes (thus forming emitter extensions) , isolation between the field region and the emitter region needs to be maintained. Otherwise, a short-circuit will be formed. In the wrap-25 through technology, a common approach for maintaining such isolation is the application of a trench or a groove, such that a portion of the field region adjacent to the through-hole is removed. A trench may have the additional benefit that the emitter is further somewhat shortened, leading to 30 both a lateral and a vertical separation of the emitter region and the field region.

Such isolation subsequent to the provision of the field region, and often also after provision of the emitter region 3 has the drawback of reducing yield; if the extension of either the field region or the emitter region is not properly under control, a leakage path may be created leading to low shunt resistance. Since a solar cell 5 typically requires a plurality of through-holes and it will only be accepted if there is no issue around any of the through-holes, such a step is therefore disadvantageous.

This problem is particularly present if the substrate is n-type doped, the emitter region is p-type doped, and the 10 field region is n-type doped. While the use of an n-type substrate is considered most beneficial for performance reasons, it provides the issue that a typical p-type dopant species, boron, has a higher diffusion temperature than a typical n-type dopant species such as phosphorous. If the p-15 type dopant species would be diffused first, the through- holes must be made before the doping. This gives rise to the problem how to prevent redoping of the walls of the through-holes in the second doping step. If the n-type dopant species is diffused first, the n-type dopant species will 20 further diffuse upon provision of the p-type diffusion, which increases the issue of properly isolating the field region and the emitter region.

W02010/049268 proposes therefore an alternative solar cell design based on an n-type substrate, wherein the 25 location of the emitter region and the field region are reversed: the field region is located adjacent to the front side of the substrate and along the walls of the through-holes; the emitter region is present adjacent to the rear side of the substrate. This reversal enables the use of 30 aluminium as a p-type dopant species rather than boron. The aluminum is diffused from the solid state and in accordance with a specified pattern: a part of the solid state aluminium dopant source is removed from the second side by 4 etching. This part is an area defining the through-holes and a first area circumferential to the through-hole. Hence, the field region does not extend into a first portion of the substrate laterally adjacent to the through-hole.

5 However, the cell concept of W02010/049268 has some disadvantages; first the reversed location of emitter region and field region is considered disadvantageous for performance perspective: the most relevant junction between the p+ and n-region is shifted from the front to the rear 10 side. Moreover, the use of boron is preferred over aluminium as a p-type dopant.

It is therefore a problem of the invention to overcome this issue and to provide an improved process, in which no additional substrate removal step is required to obtain 15 sufficient isolation of the field region and the emitter region .

SUMMARY OF THE INVENTION

According to a first aspect of the invention, the 20 invention provides a method of manufacturing a solar cell comprising the steps of:

Providing a monocrystalline semiconductor substrate with a first side and an opposed second side comprising of a dopant species of a first conductivity type in a 25 first concentration;

Doping the second side of the substrate with dopant species of the first conductivity type to define at least one field region, wherein the second side is doped in accordance with a predefined pattern, such 30 that a first area intended for the provision of a through-hole will be outside the field region.

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Providing through-holes into the substrate, located in said first areas , each through-hole being provided with a wall;

Applying dopant species of a second conductivity type 5 opposed to the first type for defining at least one emitter region at the first side of the substrate and extending along said walls of the through-holes, and Providing conductive material for definition of conductors extending from contacts of the at least one 10 emitter region through the through-holes.

In accordance with a second aspect, the invention provides a solar cell comprising a monocrystalline semiconductor substrate with a first side and an opposed second side. The substrate is herein provided with a dopant species of a 15 first conductivity type in a first concentration; at least one emitter region defined adjacent to the first side and comprising dopant species of a second conductivity type opposed to the first type; a field region defined adjacent to the second side and comprising dopant species of the 20 first conductivity type at a concentration higher than the first concentration, which emitter region, substrate and field region together defining a p-i-n diode. The solar cell further comprises conductors extending from contacts of the at least one emitter region to first terminals extending 25 from the second side of the substrate, said conductors running in through-holes through the substrate, which through-holes are provided with walls along which said at least one emitter region extends, which through-hole extension of the at least one emitter region being isolated 30 from said field region. The solar cell also comprises second terminals defined locally on the field region at the second side. Herein the field region is patterned, such that a first portion of the substrate at the second side around a 6 through-hole is located outside the field region, and wherein the through-holes and the at least one emitter region therein extend to the second side of the substrate, such that the through-hole extension is isolated from the 5 field region in the first portion of the substrate.

In accordance with a further aspect of the invention, a method of manufacturing a solar cell is provided that comprises the steps of:

Providing a monocrystalline semiconductor substrate 10 with a first side and an opposed second side comprising of a dopant species of a first conductivity type in a first concentration;

Doping the second side of the substrate with dopant species of the first conductivity type to define at 15 least one field region, wherein the second side is doped in accordance with a predefined pattern;

Applying dopant species of a second conductivity type opposed to the first type for defining at least one emitter region at the first side of the substrate and 20 extending along any exposed surfaces towards the second side, and

Providing conductive material for definition of conductors extending from contacts of the at least one emitter region to the second side.

25 In this embodiment, the exposed surfaces may be exposed within through-holes but alternatively or additionally at one or more side faces of the semiconductor substrate, and/or grooves which are not to be filled with conductive material.

30 In accordance with a further aspect of the invention, a solar cell comprising a monocrystalline semiconductor substrate with a first side and an opposed second side is 7 provided. The substrate is herein provided with: a dopant species of a first conductivity type in a first concentration; At least one emitter region defined adjacent to the first side and comprising dopant species of a second 5 conductivity type opposed to the first type; and a field region defined adjacent to the second side and comprising dopant species of the first conductivity type at a concentration higher than the first concentration, which emitter region, substrate and field region together 10 constituting a p-i-n diode. The solar cell further comprises conductors extending from the at least one emitter region to first terminals extending from the second side of the substrate; and second terminals defined locally on the field region at the second side. Herein, the field region is 15 patterned, such that a first portion of the substrate at the second side is located outside the field region, such that the first portion constitutes an isolation between the field region and an extension of the emitter region towards the second side of the substrate.

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In accordance with the process of the invention, the field region is applied in a patterned manner rather than being removed afterwards. It has to be understood that this patterned application of the field region is all but evident 25 in the context of the solar cell manufacturing process: a typical solar cell is based on a monocrystalline substrate with a thickness in the order of 100-300 microns. Such a substrate, particularly when provided in commercially attractive sizes such as 6 inch width and optionally larger 30 than that, is vulnerable to crack initiation, particularly at the high temperatures used for doping steps.

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As a result of the process of the invention, a first portion of the substrate adjacent to the second side thereof constitutes an isolation between the field region and an emitter extension towards the second side. This emitter 5 extension is particularly the through-hole extension along the through-hole walls, but alternatively and/or additionally the substrate surface along an edge of the semiconductor substrate. This first portion is typically lowly doped, in accordancewith the substrate bulk, It is not 10 excluded that the resistance of this first portion is increased, if so desired, and becomes highly resistive up to electrically insulating. Generally, a design may be chosen such that any resistance increase is not needed.

In order to minimize stress, it is typically assumed 15 best to process the substrate in the first steps most symmetrically; typically, any texturing is applied on both sides, and the first doping step is also applied on both sides (and only thereafter removed selectively on one side). This identical processing on both sides moreover serves 20 industrial efficiency: the front side and the rear side need not to be distinguished - hence these are merely a first side and a second side. Such distinction would be difficult in view of the absence of any detectable sign on either side. A mask could be used on one side, but the presence of 25 a mask could lead to development of stress due to differential thermal expansion, and hence a larger risk of crack initiation.

Specifically, the invention thus is based on the insight that a locally applied mask does not substantially 30 increase the risk of crack initiation. In suitable embodiments, it is furthermore applied at a low temperature, 9 so that no further high temperature treatment of the device is needed. Two major embodiments are available

In a first embodiment, the mask comprises a material that can be etched selectively with respect to the silicate 5 glass. Such etch selectivity may be achieved either by difference in material composition, a thickness difference and appropriate choice of the etchant for the silicate glass. It is herein not required that the etch selectivity is high; it is sufficient if any identification is 10 available. Thereto, the mask may further suitably comprises at least one identification reference. Such identification reference is not merely suitable to distinguish first and second side, and hence front side and rear side, but also to provide a reference for the lateral positioning.

15 In a second embodiment, the mask is applied on both sides of the substrate in a corresponding pattern. This enables that the substrate remains symmetric and that there is no need for distinguishing front and rear side. Hence, also if the mask is removed in an etching step typically 20 carried out to remove any silicate glass, the substrate may be safely processed on both sides.

It is observed that the mask may be generated either by deposition of a layer or by modification of the semiconductor substrate surface. The deposition of a layer 25 herein is deemed advantageous, in view thereof that modification of the semiconductor substrate surface typically requires a high temperature process such as thermal oxidation. Moreover, layer deposition allows tuning of the layer composition, which may improve etch 30 selectivity.

It is further observed that the local application of the mask may either be achieved photolithographically or in 10 a printing process. The printing process has the advantage of minimizing processing steps. Moreover, if a texturing has been applied in advance (which is typically done), the substrate surface is no longer planar, requiring a 5 sufficiently thick coating in order to cover the substrate surface appropriately. In a printing process, the printed liquid is deposited where needed/ viscosity of the printing liquid may be tuned so as to prevent outflow in an undesired manner. Furthermore, a printing process has the advantage 10 that the non-printed areas remain clean such that nonuniformities in the doping concentration across the substrate surface due to any mask rests left behind are prevented. The term 'printing' herein is understood to refer to any application technique allowing application of fluid 15 or paste onto a limited area of a surface, including inkjet printing, screenprinting, dot printing and the like.

In one implementation, the mask comprises a sol-gel type material, and is applied as a sol-gel process. This process is a wet-chemical technique for the fabrication of 20 materials (typically a metal oxide) starting from a chemical solution (or sol) that acts as the precursor for an integrated network (or gel) of either discrete particles or network polymers. Typical precursors are metal alkoxides and metal chlorides, which undergo various forms of hydrolysis 25 and polycondensation reactions. One typical example is a spin-on-glass (SOG) material, as known in the art of semiconductor processing, which after conversion into the network typically a silicon oxide. A suitable manner for the conversion into the typically inorganic network is a heat 30 treatment after deposition. Optionally, such heat treatment may be combined with any heating required for the diffusion process. Most suitably, the sol-gel material is provided by printing, for instance inkjet printing 11 A feature resulting from the process is a solar cell with a via extending from the front side to the rear side and having an emitter extension along the via, such that a substrate portion between said via and a field region 5 provides isolation against shortcircuitry between the emitter region and the field region. This solar cell has the benefits of a good performance and a good reliability.

In a specific embodiment of the process, texturisation is applied only after the doping to create the patterned 10 field region, rather than at the beginning of the process. Most suitably, such texturisation is applied at the first, e.g. front side of the substrate only. This embodiment is suitably to improve the shape at the front side. Typically, an etching step is carried out at the front side directly 15 after the first doping step, f.i.with phosphorous. This etching step again reduces the texturisation profile. This embodiment is particularly suitable for combination with the second embodiment as discussed above. In a further implementation thereof, a protective layer is applied on the 20 second, e.g. rear, side prior to such delayed texturisation of the front side. This protective layer will protect the rear side and the doping applied thereto against being removed during texturisation. Particularly, the protective layer allows deposition of the substrate on a plate or chuck 25 without running the risk of introduction of contamination into the substrate from said plate or chuck. Simultaneously, it allows a good identification of front side and rear side.

In one further embodiment, the use of a patterned field region is combined with the application of a diffusion 30 resistance layer within the through-hole. Such diffusion resistance layer aims at prevention of a boron rich layer in the substrate adjacent to the through-hole. This boron rich 12 layer is commonly associated with degradation of the carrier lifetime in the bulk of the wafer. Suitable diffusion resistance layer are for instance silicon oxide, silicon nitride, silicon oxynitride, and the like. The thickness of 5 the barrier layer can be in the range of 0.3 nm to 300 nm, preferably 5 to 30 nm. It is not excluded that the barrier layer comprises a stack of sublayers. The diffusion resistance layer acts as a resistance against diffusion of boron through the layer without completely blocking boron.

10 It is herein not excluded that the boron diffusion may be in the form of diffusion of boron oxide. Most particularly, the diffusion coefficient of the boron diffusion through the diffusion resistance layer at the diffusion temperature is reduced to a level at most equal to the diffusion of boron 15 in the semiconductor substrate at the diffusion temperature.

The diffusion resistance layer is suitably applied by chemical vapour deposition, for instance by Phase Enhanced Chemical Vapour Deposition (PECVD), Low-Pressure Chemical Vapour Deposition (LPCVD), atomic layer deposition (ALD) or 20 the like. Alternatively, the diffusion resistance layer may be applied in a thermal oxidation step. A preferred implementation hereof is the use of a high temperature oxide layer, for instance a thermal oxide or a layer deposited by LPCVD or by ALD.

25 In another further embodiment, a diffusion mask is applied on the front side. This allows the creation of selective emitter regions into the semiconductor substrate. Most suitably, such mask is again a diffusion resistance layer, such that dopant may diffuse through the diffusion 30 resistance layer. A difference in doping concentration is then created between selective emitter regions and diffusion regions. Additional doping may be provided into the 13 selective emitter regions, so as to increase the dopant concentration therein. The resulting emitter is a combination of selective emitter regions defined in accordance with the predefined pattern and a continuous 5 diffusion region at a dopant concentration lower than that in the selective emitter region. Any boron-rich layer that develops in the selective emitter may be subsequently removed by a low-temperature oxidation.

It is not deemed required that the diffusion resistance 10 layer remains in the through-hole and optionally on the front side of the substrate after the diffusion step. However, the maintenance of the diffusion resistance layer in the solar cell is not considered problematic. Particularly, the diffusion resistance layer, when 15 maintained, can be beneficially used as an adhesion layer for an antireflection coating to be provided on the front side of the substrate, and suitably, also on the rear side.

The conductors in the through-holes are for instance applied by screenprinting of metal paste. This metal paste 20 is effectively a mixture of metal and additives for the improvement of the rheology. Preferably, use is made of a metal paste free of acids, so as to ensure that the diffusion resistance layer is not removed while applying the metal paste and/or in any subsequent firing step. After such 25 removal metal could contact the substrate, which easily gives rise to a shunt.

In a further implementation, an additional barrier layer is applied after the boron diffusion step. This barrier layer is particularly suitable, if no diffusion 30 resistance layer is applied or if such diffusion resistance layer is removed after the boron diffusion step. This barrier layer is chosen so as to block diffusion of metals 14 in the paste into the substrate. As a typical metal is aluminium, the barrier layer suitably comprises diffusion barriers against the diffusion of aluminium, more preferably nitrogen containing layers, most particularly layers wherein 5 such elements are available for forming covalent bonds with aluminium. In case of silicon nitride, the composition is thereto suitably tuned so as to provide a nitrogen-rich composition.

Most suitably, the method is embodied such that the 10 dopant species of the n-type field region further diffuses during a heat treatment carried out for diffusion of the p-type dopant species. This results in a double-diffused field region .

The above mentioned specific embodiment and any 15 dependent claim may be combined with any of the above mentioned aspects of the invention. Herein, it is specifically observed that the patterning of the field region may also be used for provision of an isolation to any other extensions of the emitter region, such as along a side 20 face of the substrate.

BRIEF INTRODUCTION OF THE FIGURES

These and other aspects of the invention will be further elucidated with reference to the figures, in which: 25 Fig 1-5 show in diagrammatical cross-sectional view several stages of the method of the invention;

Fig. 6 shows in diagrammatical cross-sectional view the device of the invention according to one embodiment, and

Fig. 7-9 shows in diagrammatical cross-sectional view 30 several stages of a second embodiment of the method of the invention.

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DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The Figures are not drawn to scale and merely intended for illustrative purposes. Equal reference numerals in different figures refer to like or equal parts.

5 Particularly, the semiconductor substrate 10 shown in the following figures is shown as being provided with merely a single through-hole 20 to be converted into a via 40. However, in practice, a plurality of through-holes will be applied into the substrate 10. It is observed that the terms 10 front side will be applied for the first side 11, if and where the first, front side 11 can be distinguished from the second, rear side 12. The semiconductor substrate will also be referred to as the substrate. The term via is used for reference to a through-hole at least partially filled with 15 conductive material so as to constitute a conductor from the first side 11 to the second side 12 of the substrate 10. Where no confusion occurs, the terms may also be used interchangeably, in line with the practice in the art. In addition to providing an well-defined isolation between the 20 field region and the emitter region, the invention further has the advantage of a reduction of process steps.

Fig. 1-6 show consecutive steps of an embodiment of the method of the invention in cross-sectional diagrammatical views. Fig. 1 shows a semiconductor substrate 10 with a 25 first side 11 and a second side 12. The first side 11 and optionally the second side 12 typically have been texturized in advance of doping processes. The semiconductor substrate 10 of this example is a monocrystalline silicon substrate. While silicon substrates constitute the best available 30 compromise between manufacturing costs and quality, it is not excluded that alternative substrates are used. Such alternative substrates could be made of III-V materials, but more likely incorporate one or more layers of a different 16 material, such as a III-V material, or SiGe, SiC and the like as known to the skilled person. The semiconductor substrate is doped with a dopant of the first conductivity type, which is in the preferred example n-type. The doping 5 concentration is moderate, for instance 1016 /cm3.

In accordance with the present invention, the n+-doped region is to be applied on the second side 12 according to a predefined pattern. Thereto, a suitable mask 19A, 19B is applied in advance of the doping step. In a first 10 embodiment, the mask is applied both on the first side 11 and the second side 12. In the second, shown embodiment, the mask is applied on the second side 12 only. The second side is therewith identified as the rear side, and the first side as the front side. The front side is the side that is 15 intended for receiving irradiation during use; the solar cell will be assembled on its rear side 12 to a carrier.

The mask 19A, 19B, will effectively be present on limited areas of the substrate 10 only. The mask 19A, 19B typically comprises portions 19A at locations where in a 20 later stage of the process (see Fig. 6) vias 40 are provided and an isolation is needed between a field region 13 and an emitter 31 extending along the via 40. It therewith defines first areas. These areas are typically roughly circular around a central axis where the via 40 is planned. However, 25 variations of such shape (hexagonal, oval, square, rectangular) are not excluded and may be chosen in view of certain tolerances, or in order to compensate for misalignment in a certain direction when applying through-holes 20. A solar cell with a 6 inch or larger diameter is 30 foreseen to comprise 100 vias or less, suitably less than 50.As a result, the extension of the first areas on the rear side 12 of the substrate will therefore be relatively limited in comparison to the complete surface area.

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The mask further suitably comprises portions 19B that are positioned at and/or adjacent to an edge of the substrate 10. In one embodiment of the process, a side face of the substrate 10 is not protected during doping with a p-5 type dopant such as boron. As a result, some protection is needed in order to provide a shunt at or adjacent to the edge between the field region 13 and the emitter 31. Evidently, alternative process may be envisaged wherein the side face of the substrate 10 is removed or covered or not 10 exposed to the p-type doping process such that such mask portion 19B is not needed.

Several methods are available for application of the mask 19A, 19B that is able to block diffusion from the vapour source. One of these methods is based on the local 15 oxidation of silicon exposed within a patterned nitride layer. After removal of the nitride layer, the diffusion of the dopant species will be blocked through the thermal oxide mask. Another method involves the provision of a mask 19 directly by application of a patterned layer. Such patterned 20 layer is suitably applied either by vapour deposition or by printing; due to the texturing of the substrate that occurs typically both on the first side 11 and on the second side 12, coating processes do not provide a layer with a uniform thickness. Most suitably, use is made of printing; suitably, 25 use is made of a sol-gel type material that is converted into an inorganic layer in a heat treatment. A preferred embodiment thereof is a spin on glass material which after being cured behaves as Si02. A suitable precursor for SiCk is tetraethoxyorthosilicate (TEOS).

30 Fig. 2 shows the substrate 10 after a second stage of the processing. Herein, the semiconductor substrate 10 is provided with a region 13 of n+-doped material. Suitably, use is made of phosphorous doping in a manner known to the 18 skilled person, for instance by vapor deposition. According to one embodiment, the phosphorous doping is diffused into the substrate 10 by a heat treatment of approximately 800 °C for 5-50 minutes in an atmosphere containing O2 and P2O5 5 vapour. This process results in the formation of a silicon oxide film (not shown) which incorporates P2O5. At the interface the substrate and the silicon oxide film, the P2O5 is reduced to elemental phosphorous, which diffuses into the substrate 10, resulting into a region adjacent to the front 10 side 11 (not shown) and a region 13 adjacent to the rear side. Subsequently, the silicon oxide film is removed (also referred to as PSG etch) by dipping the substrate in a 1-50% HF solution for about 0.5-10 minutes, or exposing the substrate to a HF vapour. The thickness of the mask 19A, 19B 15 is preferably chosen such that after the HF treatment it is still of such thickness remains present at the rear-side 12 of the substrate 10. More specifically, the mask 19A, 19B acts as a protection in the boron diffusion step. As will be understood, any boron diffusion in the first portion of the 20 substrate 10 below the mask 19A, 19B, will create a conductive path from an emitter extension along the walls of the through-hole towards the field region. This again would risk a shunt. It is therefore important that the first portion of the substrate is protected in the boron diffusion 25 step, for instance by the mask 19A, 19B.

It is observed that the phosphorous doping may be applied both on the front side 11 and on the rear side 12. Then, the region adjacent to the front side 11 is removed by etching, for instance using a mixed solution of 1-30% HF and 30 0.1-50% HNO3. This result in a substrate 10 that has been doped at its rear side 12 with a dopant species of the first conductivity type to define at least one field region 13.

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Instead of using a vapour phase dopant, a solid phase dopant could be applied. Such solid phase dopant could be applied locally, for instance by screenprinting or by patterning a layer of the solid phase dopant in accordance 5 with the desired pattern prior to a heat treatment resulting in the diffusion. This implementation has the advantage that the mask 19a, 19b may be left out.

Fig. 3 shows the substrate 10 after a third stage in the processing. A through-hole 20 is provided into the 10 semiconductor substrate 10, and extends from the front side 11 to the rear side 12 thereof. Typically, a plurality of through-holes 20 is applied in a single solar cell, so as to reduce a lateral distance over which generated current has to be transported to a terminal. The through-holes are 15 typically applied by laser etching, although other forms of etching, such as reactive ion etching or a combination of reactive ion etching and wet-etching are not excluded. While the through-hole 20 is shown to be straight, it is not excluded that the through-hole 20 is further modified to 20 have a varying diameter, or that any sharp edges at its top and bottom side, i.e. on the front side 11 and the rear side 12 are removed. The diameter of the through-hole is typically in the order of 5-400 microns. In one implementation, the through-hole is filled with a conductor 25 in a metal-wrap through cell. In another implementation, the through-hole is filled with a conductor in an emitter-wrap through cell. The diameter of the through-hole is suitable less in the emitter-wrap through cell than in the metal-wrap through cell.

30 Optionally, a diffusion resistance layer 22 is suitably applied by chemical vapour deposition or thermal oxidation, and more preferably by low pressure chemical vapour deposition (LPCVD), atomic layer deposition (ALD) or a rapid 20 thermal anneal (RTA). The diffusion resistance layer is further intended to create selective emitter regions, localized emitter regions on the front side 11 having a higher dopant concentration than other portions of the 5 emitter region and being highly suitable as contact areas for a conductor to be applied on the surface. It is not excluded, and it may even be advantageous, that outside the selective emitter regions p+ material is present but in a lower dopant concentration, particularly resulting from 10 diffusion through the diffusion resistance layer. The diffusion resistance layer for instance has a thickness of 2-100 nm, preferably 3 to 30 nm.

Fig. 4 shows the substrate 10 in a fourth stage, after the provision of the doping species of a second type, in 15 this case p type, and more particularly a boron diffusion.

The Boron diffusion source may be a vapour source or a coating source. In the oven the substrate is heated for a certain period of time and to a certain temperature so as to diffuse Boron into the front side of the substrate 10, and 20 create an emitter region 31. The emitter 31 herein also extends along walls of the through-hole 20, therein defining a through-hole extension 31C of the emitter 31. Simultaneously, the phosphorous doping at the rear side 12 of the substrate 10 is diffused as well, so as to create a 25 double-diffused field region 13. Successful results have been obtained with a Boron vapour source for the diffusion. Two substrates are put back-to-back into the oven and heated at 900-1000°C for 30-120 minutes, for instance at 950 °C for 1 hours in an atmosphere including an O2 and boron oxide 30 (B203) vapor. As explained above, this B203 vapor is typically in situ created from a Boron tribromide (BBr3) vapour in the presence of oxygen. The boron oxide vapour reacts with the silicon surface to create elemental boron and silicon oxide.

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The elemental boron then diffuses into the silicon substrate .

The silicon oxide is typically contaminated with boron oxide, resulting in a borosilicate glass. After the 5 termination of the diffusion treatment, the borosilicate glass is suitably removed. The removal of the borosilicate glass may be effected either with an acid such as HF or hot water or any other known etchant which allows etching of the borosilicate glass.

10 Fig. 5 shows the substrate 10 after the provision of a layer or layer stack 32A, 32B, 32C. The layer or layer stack may be used as a passivation layer and/or as an antireflection coating. For sake of clarity, it will be referred to as a passivation layer. The passivation layer 32A, 32B, 15 32C is in this embodiment applied on the front side 11, in the through-hole 20 and on the rear side 12. The passivation layer suitably comprises SiN, as known to the skilled person, but alternative materials are by no means excluded. It goes without saying that the passivation layers 32A, 32B, 20 32C could be applied in separate steps and then do not need to have identical composition. A thickness and shape of layer 32C will depend very much on the deposition method employed. Similarly to layer 32C also a layer at the edge of the wafer may be formed; this layer is not shown in the 25 figure. When using SiN, it is deemed beneficial to apply an adhesion layer between the substrate surface and the silicon nitride layer, for instance an oxide. It is not excluded that the passivation layer 32A, 32B, 32C comprises a plurality of thin layers, which are particularly optimized 30 with respect to its further use as anti-reflection coating.

A further alternative for the passivation layer 32A, 32B, 32C resides in the provision of an amorphous silicon layer stack. These amorphous silicon layers are suitably deposited 22 by Plasma enhanced chemical vapour deposition (PECVD), for instance in a parallel plate plasma deposition driven by a 13.5 MHz power source, or in an inductively coupled plasma PECVD set up. The thickness of amorphous silicon layers in 5 the stack is suitably 20 nm or less, preferably lo nm or less. The stacks typically comprise an intrinsic layer and a p-doped layer on the front side 11, and an intrinsic layer and an n-doped layer at the rear side 12. It has turned out that such amorphous silicon layers not merely act as 10 passivation layers, but also result in silicon heterojunction solar cells with higher efficiency.

Fig. 6 shows the resulting solar cell 100, obtained by the provision of conductive material to define conductors 40, 41 and terminals 51, 52. The conductors include a via 15 40, i.e. the filled through-silicon through-hole and the conductor 41 on the front side 11. The conductor 41 on the front side 11 suitably comprises silver and or aluminum, the via 40 for instance comprises a silver/aluminum alloy or silver. Such type of conductors are typically applied using 20 a metal paste by screenprinting in a process known in the art, as deemed most beneficial from a cost perspective. The screenprinting paste applied on the front side 11 is typically an acid-containing screenprinted paste that is able, upon heating, to etch away underlying layers, i.e.

25 portions of the passivation layer 32A. After deposition, the screen printed paste is typically fired. The through-holes 20 are suitably filled with conductive material by screenprinting a non-firing through paste, most suitably from the rear side 12. Such non-firing through paste, 30 typically a specific paste composition without or with a low level of activators. Activators in paste material typically include organic acids, such as alkyl and aryl carboxylic acids, organic halogen acid adducts, halogenated organics, 23 ammonium halides and halogenated pyridines. A non-firing through paste is also known as a low-activity paste, for instance HeraSol SOL 109 as commercially available from Heraeus GmbH.

5 The present solar cell device 100 is provided with first terminals 51 and second terminals 52. It is observed that typically a plurality of both the first terminals 51 and the second terminals 52 are present on the rear side 12 of the substrate 10. The first terminals 51 are electrically 10 connected to the vias 40; the second terminals 52 are electrically coupled to the field region 13. It is suitable that the field region 13 is contacted in a distributed pattern, for instance in the form of a star, H-shape or the like. The shape may be optimized to reduce series resistance 15 to the field region 13 and to reduce metal consumption. The second terminals 52 may comprise such distributed contacts. Alternatively, an additional layer may be provided for the definition of such contacts. Suitably, both the first and the second terminals 51, 52 are substantially dot-shaped 20 where contact will be made to a conductor in a panel carrier, which is known per se as a back sheet foil. Suitably, the processing is carried out such that both terminals are applied in a single process step. Therefore, most suitably, the via 40 extends to the same level as the 25 substrate 10.

Fig. 7-9 show three steps in an alternative embodiment of the method in accordance with the invention, corresponding to the steps indicated in Fig. 3-5. The other figures are not reproduced again, but it is intended that 30 the process of this second embodiment comprises the same steps as illustrated therein. This is an alternative version of the second embodiment of the invention, based on selective processing of the rear side 12, wherein also an 24 identification of the rear side 12 relative to the front side 11 is maintained.

Fig. 7 shows the substrate 10 after a third step. Herein, following the patterned provision of the field 5 region 13 on the rear side 12 of the substrate, the rear side 12 is coated with a protective layer or layer stack 15. In a preferred embodiment, this is a layer stack comprising an adhesion layer, for instance an oxide, such as silicon oxide and another layer, for instance a nitride, such as 10 silicon nitride. This protective layer 15 is suitably provided with chemical vapour deposition, typically low-pressure chemical vapour deposition as known to the skilled person for the provision of passivation layers. This Fig. 7 does not show the mask 19A, 19B, but it is suitably left in, 15 as shown in Fig. 3 to reduce the number of process steps.

That is beneficial for identification of rear side 12. After deposition of the protective layer 15, the identification can be based hereon. Even though it suitably extends on the complete rear side 12, such protective layer 15 will have a 20 surface structure different from that of the blank semiconductor substrate exposed on the front side 11.

Fig. 8 shows the substrate after the fourth stage. Suitably, it is only at this stage that a texturisation step is applied on the front side 11. This late texturisation 25 leads to better controlled front-side pyramids and hence better light trapping. It moreover leads to an improved silicon-oxide interface definition at the front side, reducing dark current and/or surface recombination. Additionally, the late texturization step removes any 30 phosphorous doping from the front side 11 of the substrate 10. Such phosphorous doping of the first side 11 of the substrate 10 may occur intentionally or unintentionally during the phosphorous doping step as shown in Fig.2. While 25 in the conventional process an additional step of removing a substrate part on the first side 11 is required, this step can be left out with the present late texturisation embodiment. This is considered a relevant process 5 improvement, particularly suitable in combination with the patterned application of the field region 13 and deemed most suitable for an MWT (metal wrap through) type solar cell.

Furthermore, the late texturization step may further be exploited to remove any phosphorous doping from the wafer 10 edge, i.e. a side face of the semiconductor substrate 10. This removal of wafer edge doping is suitable so as to prevent a shunt between the emitter region and the field region .

Suitably, the protective layer 15 prevents 15 texturisation of the rear side 12.Texturisation is typically carried out with wet-chemical etching, for instance with an etchant such as potassium hydroxide (KOH). The substrate 10 is then for instance put into suitable bath with the etchant. This protection layer furthermore will prevent 20 occurrence of any parasitic boron doping during the subsequent diffusion step of p-type charge carriers.. The fourth stage further comprises the definition of through-holes 20, either before or after the texturisation.

Fig. 9 shows the diffusion step of the p-type charge 25 carriers, particularly boron on the front side 11, along the walls in the through-holes 20 and along the side faces of the substrate 10. It is observed that any further modification as discussed above, such as the creation of selective emitters on the front side 11 could also be 30 applied in this embodiment.

26

Nrs in Figures 10 semiconductor substrate 11 first side of semiconductor substrate 5 12 second side of semiconductor substrate 13 field region (n+ doped) on the second side 15 protective layer 19A mask corresponding to a first area 19B mask near an edge of the substrate 10 10 20 through-hole 31 emitter region (p+ doped) 31C through-hole extension of the emitter region 31 32A passivation layer on front side 32B passivation layer on rear side 15 32C passivation layer on the walls of the through-holes 40 via (filled through-hole) 41 conductor on the front side 51 first terminal 52 second terminal 20 100 solar cell

Claims

A method for manufacturing a solar cell, comprising the steps of:

The method of claim 11, wherein doping the second side comprises applying a mask (19A) to the first region and applying the doping through the mask.

3. Method as claimed in claim 2, wherein the mask (19A, 19B) is only applied on the second side and further serves to identify the second side as a rear side.

A method according to claim 3, wherein a protective layer (15) is applied prior to the application of the dopant in the form of charge carriers of the second conductivity type.

The method according to claim 4, wherein a texturization step is applied to the first side after applying the protective layer (15) to the second side (12).

5. Providing a monocrystalline semiconductor substrate (10) having a first side (11) and an opposite second side (12) doped with charge carriers of a first conductivity type in a first concentration;

6. Method as claimed in claim 1 or 2, wherein both the semiconductor substrate (10) is doped on both the first side (11) and on the second side (12) with charge carriers of the first conductivity type according to predetermined pattern, and wherein a layer of the semiconductor substrate (10) with said charge carriers 20 is removed from one of the first side (11) prior to mounting the charge carriers of the second conductivity type, by which removal step the first side (11) is distinguished from the second side (12) ) and is determined as the front.

The method of claim 1, further comprising the step of applying a diffusion resistance layer to the walls of the holes (through holes).

A method according to claim 7, wherein the diffusion resistance layer is selected such that charge carriers of the second conductivity type diffuse through the diffusion resistance layer with a diffusion speed that is at most substantially equal to a diffusion speed of said charge carriers of the second conductivity type in the semiconductor substrate.

The method of claim 1, wherein the definition of the emitter regions includes the definition of selective emitter regions on predetermined local regions on the first side of the semiconductor substrate.

10. The method of claim 9, wherein the definition of the emitter region further comprises the step of defining diffusion regions around said selective emitter regions, and wherein the selective emitter regions are provided with the charge carriers in a higher concentration than the diffusion regions.

10. Doping the second side (12) of the semiconductor substrate with charge carrier of the first conductivity type for defining a first field region, wherein the second side is doped according to a predetermined pattern such that a first region in which a hole through the semiconductor substrate (through-hole) is planned, remains outside the field area. Providing the holes through the semiconductor substrate from the first side to the second side, each hole having a wall; Providing doping in the form of charge carriers of a second conductivity type opposite to the first conductivity type for defining at least one emitter region on the first side (11) of the semiconductor substrate (10) and extending along the walls of the holes, and The provision of conductive material for the definition of conductors extending from the at least one emitter region through the holes. 30

11. The method of claim 1, wherein the field region is further patterned by dividing the field region into the substrate into various field regions.

A solar cell comprising a monocrystalline semiconductor substrate with a first side and an opposite second side, said semiconductor substrate comprising: 20. doping in the form of charge carriers of a first conductivity type in a first concentration comprising at least an emitter region present on the first side and comprising doping in the form of charge carriers of a second conductivity type opposite to the first type, and; a field region present on the second side and comprising doping in the form of charge carriers of the first conductivity type in a concentration higher than the first concentration, which emitter region, substrate and field region together form a p-i-n diode; Which solar cell further comprises: conductors extending from the at least one emitter region to first contacts located on the second side of the substrate, which conductors run through holes in the substrate and which holes have walls along which said at least emitter area, which through-hole extension or of the at least one emitter area is isolated from the field area, and second contacts located locally on the field area, wherein the field area is patterned such that a first portion of the substrate is on the second side around the hole is outside the field area, and wherein the holes and the at least one emitter extend along it to the second side of the substrate, such that the through-hole extension is isolated from the field area by the first portion of the substrate .

Solar cell according to claim 12, wherein only the first side of the substrate is provided with texturization.

The solar cell of claim 12, wherein the field area in the substrate is subdivided into various field areas

15. Solar panel comprising at least one solar cell as claimed in any of the claims 12-14 and a panel lifter, wherein at least some of the first and second contacts of the solar cell are connected to conductors in the panel support.

A method for manufacturing a solar cell, comprising the steps of:

25. Providing a monocrystalline semiconductor substrate (10) having a first side (11) and an opposite second side (12) doped with charge carriers of a first conductivity type in a first concentration;

30. Doping the second side (12) of the semiconductor substrate with charge carrier of the first conductivity type for defining a first field region, in which the second side is doped according to a predetermined pattern, - Applying doping in the form of charge carriers of a second conductivity type 5 opposite to the first conductivity type for defining at least one emitter region on the first side (11) of the semiconductor substrate (10) and extending along an exposed surface of the substrate toward its second side, and The provision of conductive material for the definition of conductors extending from the at least one emitter region to contacts on the second side.

17. Method as claimed in claim 16, characterized in that the field region is patterned under the definition of undoped regions next to an edge of the semiconductor substrate and wherein the charge carriers of the second conductivity type extend along a side of the semiconductor substrate.

The method of Claim 16, wherein the field area 20 is patterned for subdivision into various field areas.

19. Solar cell comprising a monocrystalline semiconductor substrate with a first side and an opposite second side, which semiconductor substrate 25 is provided with: doping in the form of charge carriers of a first conductivity type in a first concentration at least one emitter region present on the first side and comprising doping in the form of charge carriers 30 of a second conductivity type opposite to the first type, and; a field region present on the second side and comprising doping in the form of charge carriers of the first conductivity type in a concentration higher than the first concentration, which emitter region, substrate and field region together form a p-i-n diode; Which solar cell further comprises: 5. conductors extending from the at least one emitter area to first contacts located on the second side of the substrate, and second contacts lying locally on the field area, wherein the field area is patterned such that a the first part of the substrate on the second side is outside the field area, so that the first part forms an insulation between the field area and an extension of the emitter area that extends to the second side.