NL1027012C2 - Reusable hardware IP protocol for system on a chip devices, determines whether hardware IP parameters are required and enters function parameter or search signal - Google Patents

Abstract

The protocol describes a hardware behaviour using a software function and operates using the following steps: (A) determining whether the hardware IP (Intellectual Property) requires parameters; (B) entering at least one function parameter into the hardware IP if parameters are required and using corresponding detection data item to observe whether the parameter is incorrect or has been entered completely; (C) entering a search signal for the hardware IP if no parameters are required; (D) waiting for a confirmation signal from the hardware IP; (E) generating result data from the hardware IP and using a detection result for observing whether the result data has been entered completely or is incorrect; and (F) resetting or rebooting the hardware IP.

Description

REUSABLE IP PROTOCOL PROCESS FOR A COMPOSITION-ON-CHIP DEVICE

Background of the Invention 1. Field of the Invention

The present invention relates to a protocol method for an assembly-on-chip device and more particularly a reusable hardware IP protocol method for an assembly-on-chip device.

5 2. Description of related technology

Assembly-on-chip ("system-on-chip") designs have become a major trend in current circuit designs that integrate the various functionally interconnected switch blocks on one chip. Taking an assembly-on-chip microprocessor in the field of calculations as an example, the assembly-on-chip internal circuit integrates the switching blocks of a CPU, a "chip set" and a graphics chip so that the assembly-on-chip microprocessor includes the functionality of all these three circuit blocks. The assembly-on-chip design not only reduces manufacturing costs but also the total circuit area to thereby reduce the total circuit size. Each circuit block is assembled from 1027012-2 from various distinguishable circuit modules that include counters, adders, encoders, decoders, etc., which are known as hardware IP (intellectual property). The assembly-on-chip design 5 uses hardware IPs to build the necessary circuit blocks and then integrates these circuit blocks on a single chip. Generally, such assemblies are known from Renaudin M.: "Asynchronous circuits and systems: a promising design alternative", Microe-lectronic Engineering, Elsevier, part 54, no. 1-2, December 2000, pages 133-149, and from US-A1-2004 / 013210.

However, there are certain problems with the assembly-chip design. The most important is clock frequency control between the various hardware IP components. A clock frequency signal is used to control the operating speed of each hardware IP component in the chip-based system. When the clock frequency signal is sent to each circuit block in the assembly-on-chip, all hardware IP components in the circuit block will operate at the same frequency. Since every hardware. IP component has its own individual operating frequency to enable various hardware IP components to work. at a single clock frequency, the clock frequency signal meets the lowest clock frequency to prevent incorrect timing. However, this reduces overall efficiency.

It is therefore desirable to provide a reusable hardware IP component protocol method for an on-chip assembly to reduce or eliminate these aforementioned problems.

Summary of the invention

The main purpose of the present invention is to provide a reusable hardware IP component protocol method for an assembly-on-chip that can describe hardware behavior through software functions.

1027012-3

Another object of the present invention is to provide a reusable IP component protocol method for an assembly-on-chip that can be reused several times.

Another object of the present invention is to provide a hardware IP component protocol method for an assembly-on-chip that can be used in asynchronous circuit designs.

To achieve the above objectives, the present invention discloses a reusable hardware IP component protocol method for an assembly-on-chip, which method comprises: (A) determining whether parameters are required, corresponding to a determination step of or the hardware module requires parameters; wherein when parameters are needed, the step (B) is proceeded to, and if this is not the case, the step (C) is proceeded; (B) inputting at least one functional parameter corresponding to an input step at the hardware module for at least one functional data parameter; (C) calling a software function corresponding to a signal request step of the hardware module; (D) waiting for a return value of the software function corresponding to a confirmation signal step of the hardware module; (E) returning the return value of the software function corresponding to performing a result data step of the hardware module; and (F) terminating the software function corresponding to a hardware reset step of the hardware module.

Ultimately, the software function is used to generate hardware description language and the hardware description language is used to generate IP components. The assembly-on-chip is designed for at least one hardware module, and the hardware module operates asynchronously. The software function of the present invention can be used to describe the hardware performance and can be used for both synchronous and asynchronous circuit designs to achieve the objects of the present invention.

Other objects, advantages and novel features of the invention will become apparent from the following detailed description which is to be read together. be with the accompanying drawings.

Brief Description of the Figures Figure 1 is a software flow chart of a reusable hardware IP component protocol method for an assembly-on-chip according to the present invention; Figure 2 shows a flow chart of hardware IP component performance according to Figure 1; and Figure 3 is a schematic drawing of the hardware IP component performance.

Detailed description of the preferred embodiment 20

Figure 1 shows a software flow chart of a reusable hardware IP component procotol method for an assembly-on-chip according to the present invention. The method of the present invention uses a software function to describe hardware IP component behavior and calls the software module to correspond to the output of hardware IP components. Referring to Figures 1, 2 and 3, Figure 2 is a flow chart of hardware IP component behavior according to Figure 1. Figure 3 shows a timeline diagram of the hardware IP component behavior. As shown in Figure 1, a method of a procedure of the method of the present invention comprises:

Step 10: determine whether the software function requires parameters; when these are necessary, Step 12 is performed; if this is not necessary, Step 14 is performed. The software function may be the following accumulating function (1) but is not limited to this function: public static int sumTo (int CNT) - (. 1) {int SUM = 0; for (int i = 1; i <= CNT; i ++) 10 {SUM + = i; } 15 return SUM; } 20 To call the function (1), a function parameter must be set and entered, for example, setting the function parameters CNT to 5.

As is well known, when the hardware IP component resets or reboots, Step 30 is always executed to initialize the hardware for each successive output. In addition, the hardware operation of Step 30 is shown at an ascending slope 50 of a CLR signal in Figure 3, which means that the CLR signal is set as the high state to delete any data that is temporarily stored in the hardware IP components.

Step 10 for the software function corresponds to Step 32 for the hardware IP component, where Step 32 is performed to determine whether the hardware IP component 35 parameters is needed and if this is the case, Step 34 is performed to enter the parameter data, to correspond to Step 12. When Step 32 determines that 1027012-6 no hardware IP component is required, step 36 is performed to activate a request signal, to correspond to step 14. The hardware operation of Step 34 is shown at a ascending slope 52 from. the parameter data in Figure 3, which means that an external circuit (circuit connected to the hardware IP component) inputs parameter data (such as the aforementioned CNT = 5) into the hardware IP component. The internal circuit may also receive the acknowledgment signal of receiving the input data from the hardware IP component.

Step 14 is performed to invoke the software function. For the function (1), after Step 12, the software should be executed. Step 14 executes the following code 15 int SUM = 0; for (int i = 1; i <= CNT; i ++) {20 SUM + = i; } Furthermore, Step 14 corresponds to Step 36 in Figure 2 which is performed to activate a request (REQ) signal. The REQ signal is input from the external circuit into the hardware IP component at a high state, and the hardware IP component performs an external circuit operation (according to Step 14) according to the functional setting and the input parameters and generates an appropriate response (performing from the result of Step 14). Step 36 is shown at an ascending slope 54 in Figure 3 which means that the external circuit 35 sets the REQ signal to a high state and then the internal circuit in the hardware IP component starts working.

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Step 16 is performed to wait for a return value of the software function. For the function (1), when the parameter is provided (in Step 12) and has been processed (in Step 16), the function (1) will return a resultant value (or a return value).

Furthermore, Step 16 corresponds to Step 38 in Figure 2, which is performed to wait for an acknowledgment (ACK) signal. After the hardware IP component has performed its appropriate processing, the resulting value is generated by the hardware IP component and output to the external circuit. The ACK signal is sent from the hardware IP to the external circuit which indicates that the resulting value is being produced. The hardware IP component is then ready to output the resultant value to the external circuit. Step 38 is shown as an ascending edge 56 of the ACK signal in Figure 3, wherein when the hardware IP raises the ACK signal from a low state to a high state, the hardware IP component completes the requested operation 20 and outputs the resulting value to the external circuit.

Step 18 is performed to return the return value of the software function. After the function (1) has completed the operation, the return value is returned. Since the CNT parameter is 5, the function (1) works and as a result a SUM has a parameter of 15 and returns the SUM parameter. Step 18 corresponds to Step 40 in Figure 2, which is performed to output the resulting data. When the REQ signal and the ACK signal are both set to a high state, the hardware IP component outputs the resulting value of the processing of the external circuit; that is, outputs the resulting data. Step 40 is shown as an ascending edge 58 of the resultant data in Figure 3, indicating execution of the resulting data 15.

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Step 20 is performed to terminate the software function. After the function (1) returns the return value, the function (1) has finished its task and the function can be called again. Step 20 corresponds to step 42 in Figure 2, which is performed to reset the hardware. After receiving the resulting data, the external circuit sets the REQ signal to a low state so that the IP component can erase temporarily stored data and is ready for the next call. Step 42 is shown as a falling edge 60 REQ signal in Figure 3. When the REQ signal is at a low state, the hardware IP component stops executing the resulting data and removes the resulting data in the hardware IP component, as indicated by the falling edge 62 of a data signal shown in Figure 3. When the ACK signal is in a low state, indicating that the resulting data is completely deleted, as indicated at the falling edge 64 of the ACK signal as shown in Fig. 3, the hardware IP component is ready for the next processing.

In addition, during input of the parameters and execution of the resulting data, a double check data representation ("doublé checked 25 that representation") is used to ensure that input / output procedures are completed, as well as the execution of an error detection means. As in Step 34, while entering the parameter data, rounding detection or errordetection (CDED) parameter data is also entered simultaneously by using, for example, a complement technique (also used in Step 40), which determines whether the sum of the parameter data is the CDED parameter data is -1. However, there are many other error-detecting methods that can be used. When the parameter data is entered as CNT * 5, the CDED parameter is entered as CNT '= -6, and its hardware output is shown as a rising edge 53 of the CDED parameter data in Figure 3. When the resultant data is output as SUM = 15, the detection / post-detection parameter data is output as SUM '= -16, and its hardware output is shown as a rising edge 59 of the CDED parameter data in Figure 3. Therefore, the correctness of data transmission.

The software function of this embodiment can be used to indicate the operation or performance of the hardware IP component, and the software function can be called repeatedly, meaning that the hardware IP component can repeat the operation. In this way the software function can be transformed into a practical hardware structure. For example, the software function can be transformed into a well-known VHSIC ("Very High Speed Integrated Circuit") hardware descriptive language ("Hardware Description Language", VHDL) and the VHDL is then transformed into a practical hardware structure. In other words, the pro-20 grammature function can describe the performance of the hardware. Furthermore, when the assembly-on-chip is designed to have more than one software function, since the hardware IP component corresponds to the. software function implemented in accordance with the above steps and independently of the clock frequency, the different hardware IP components have different clock frequencies. Furthermore, the hardware IP component can work correctly in both synchronous and asynchronous assembly-on-chip designs.

Although the present invention has been explained with reference to a preferred embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the invention which is set forth below in the claims.

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Claims (6)

Method for a reusable hardware intellectual property (IP) protocol for an assembly-on-chip device, which is able to describe a hardware behavior via a software function, the method comprising: (A) determining whether parameters are necessary which corresponds to a determination of whether the hardware requires IP parameters; wherein if parameters are needed, the process proceeds to step 10 (B) and, if not, proceeds to step (C); (B) inputting at least one function parameter and at least one detection data corresponding to the at least one function parameter, corresponding to inputting at least one function parameter to the hardware IP, the at least one detection data being used for sensing or the at least one function parameter is incorrect or has been entered completely; (C) calling the software function, which corresponds to an input of a request signal to the hardware IP; (D) waiting for a returned value of the software function, which corresponds to waiting for an output of a confirmation signal from the hardware IP; (E) sending back the return value from the software function and at least one detection result data from the hardware IP, corresponding to an output of the result data from the hardware IP with the at least one detection result data corresponding to resultant data and the at least one detection result data is used to sense whether the at least one result data is incorrect or has been entered completely; and (F) terminating the software function corresponding to a reset or restart of the hardware IP. The method of claim 1, further comprising for step (A) a hardware initialization step for initializing the hardware IP. The method according to claim 1, wherein the at least one detection data is a complementary number of the at least one function parameter. The method of claim 1, wherein the at least one detection resultant data is a complementary number of at least one resultant data. The method of claim 1, wherein the software function can be transformed into a hardware description language. The method of claim 1, wherein the on-chip assembly comprises at least one hardware IP and interaction of each of the at least one hardware IP with an external circuit is asynchronous. -o-o-o-> 10270 12-