US7454604B2 - Reusable hardware IP protocol method for a system-on-chip device - Google Patents
Reusable hardware IP protocol method for a system-on-chip device Download PDFInfo
- Publication number
- US7454604B2 US7454604B2 US10/851,098 US85109804A US7454604B2 US 7454604 B2 US7454604 B2 US 7454604B2 US 85109804 A US85109804 A US 85109804A US 7454604 B2 US7454604 B2 US 7454604B2
- Authority
- US
- United States
- Prior art keywords
- hardware
- software function
- data
- component
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related, expires
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
Definitions
- the present invention relates to a protocol method for a system-on-chip device and, more particularly, to a reusable hardware IP protocol method for a system-on-chip device.
- System-on-chip designs have become an important trend in current circuit designs, integrating several functionally related circuit blocks into one chip.
- the system-on-chip's internal circuitry integrates the circuit blocks of a CPU, a chip set, and a graphical chip, so that the system-on-chip microprocessor contains the functionality of all three circuit blocks.
- the system-on-chip design not only reduces manufacturing costs but also reduces the total circuit area to reduce the entire circuit size.
- Each circuit block is composed of several different circuit modules, which may include counters, adders, coders, decoders, etc., that are known as hardware IP (Intellectual Property).
- the system-on-chip design uses hardware IPs to build the required circuit blocks, and then integrates the circuit blocks together into a single chip.
- a clock frequency signal is used for controlling an operating speed of each hardware IP component in the system-on-chip.
- the clock frequency signal is sent to every circuit block in the system-on-chip, all the hardware IP components in the circuit block will operate at the same frequency. Since every hardware IP component has its individual operating frequency, in order to enable several hardware IP components to operate in a single clock frequency, the clock frequency signal must satisfy the slowest clock frequency to avoid incorrect timing. However, this reduces the overall system efficiency.
- a main objective of the present invention is to provide a reusable hardware IP component protocol method for a system-on-chip that can describe hardware behavior by software functions.
- Another objective of the present invention is to provide a reusable hardware IP component protocol method for a system-on-chip that can be reused many times.
- Another objective of the present invention is to provide a reusable hardware IP component protocol method for a system-on-chip that can be used in asynchronous circuit designs.
- the present invention discloses a reusable hardware IP component protocol method for a system-on-chip, the method includes: (A) determining whether any parameters are needed, corresponding to a determination step of whether the hardware module needs any parameters; wherein if parameters are needed, proceeding to step (B), and if not, proceeding to step (C); (B) inputting at least one functional parameter, corresponding to an inputting step of the hardware module for at least one functional data parameter; (C) calling a software function that corresponds to a signal requesting step of the hardware module; (D) waiting for a return value from the software function corresponding to an acknowledge signal waiting step of the hardware module; (E) sending back the return value from the software function corresponding to an outputting result data step of the hardware module; and (F) ending the software function corresponding to a hardware reset step of the hardware module.
- the software function is utilized to generate hardware description language, and the hardware description language is utilized to generate hardware IP components.
- the system-on-chip is designed for at least one hardware module, and the hardware module performs asynchronously.
- the software function of the present invention can be used to describe the hardware performance and be used for both synchronous and asynchronous circuit designs to achieve the objectives of the present invention.
- FIG. 1 is a software flowchart of a reusable hardware IP component protocol method for a system-on-chip according to the present invention
- FIG. 2 is a flowchart of hardware IP component performance corresponding to FIG. 1 ;
- FIG. 3 is a schematic drawing of the hardware IP component's performance.
- FIG. 1 shows a software flowchart of a reusable hardware IP component protocol method for a system-on-chip according to the present invention.
- the method of the present invention uses a software function to describe hardware IP component's behavior, and calls the software module to correspond to execution of the hardware IP component. Please refer to FIG. 1 , FIG. 2 and FIG. 3 .
- FIG. 2 is a flowchart of hardware IP component's behavior corresponding to FIG. 1 .
- FIG. 3 shows the timing diagram of the hardware IP component's behavior.
- a procedure of the method of the present invention includes:
- Step 10 determining whether the software function needs any parameters; if needed, step 12 is performed; if not, step 14 is performed.
- the software function can be the following accumulation function (1), but is not limited to this function:
- a function parameter Before calling the function (1), a function parameter needs to be set and input, for example setting the function parameter CNT to 5.
- step 30 is always executed to initialize the hardware for any subsequent execution. Moreover, the hardware operation of step 30 is shown at a rising edge 50 of a CLR signal in FIG. 3 , which means that the CLR signal is set as the high state to remove any data temporarily stored in the hardware IP components.
- Step 10 for the software function corresponds to step 32 for the hardware IP component, wherein step 32 is executed to determine whether the hardware IP component needs any parameters, and if yes, step 34 is executed to input parameter data, to correspond to step 12 . If step 32 determines that no hardware IP component is required, step 36 is executed to enable a request signal, to correspond to step 14 .
- Step 14 is executed to call the software function.
- the software should be executed.
- Step 14 executes the following code:
- step 14 corresponds to step 36 in FIG. 2 , which is executed to enable a request (REQ) signal.
- the REQ signal at a high state is input from the external circuit to the hardware IP component, and the hardware IP component executes an internal circuit operation (corresponding to step 14 ) according to functional settings and the input parameter and generates an appropriate response (the outputting result of step 14 ).
- Step 36 is shown as a rising edge 54 in FIG. 3 , which means the external circuit sets the REQ signal with a high state, and then the internal circuit in the hardware IP component begins to operate.
- Step 16 is executed to wait for a return value from the software function.
- the function (1) when the parameter is provided (in step 12 ), and has undergone execution (in step 16 ), the function (1) will send back a resultant value (or a return value).
- step 16 corresponds to step 38 in FIG. 2 , which is executed to wait for an acknowledgment (ACK) signal.
- ACK acknowledgment
- the hardware IP component After the hardware IP component has executed its appropriate operation, the resultant value is generated by the hardware IP component and output to the external circuit.
- the ACK signal is sent from the hardware IP to the external circuit indicating the resultant value is being produced.
- the hardware IP component then is ready to output the resultant value to the external circuit.
- Step 38 is shown as a rising edge 56 of the ACK signal in FIG. 3 , wherein when the hardware IP raises the ACK signal from a low state to a high state, the hardware IP component completes the requested operation and output the result value to the external circuit.
- Step 18 is executed to send back the return value of the software function. After the function (1) has finished operation, the return value is sent back. Since the CNT parameter is 5, the function (1) runs and results a SUM parameter of 15, and sends the SUM parameter back. Step 18 corresponds to step 40 in FIG. 2 , which is executed to output the resultant data.
- the hardware IP component When the REQ signal and the ACK signal are both set to the high state, the hardware IP component outputs the resultant value of the operation to the external circuit, i.e. outputs the resultant data 15 .
- Step 40 is shown as a rising edge 58 of the result data in FIG. 3 , which indicates outputting of the result data 15 .
- Step 20 is executed to end the software function. After the function (1) sends back the return value, the function (1) has finished its task and the function can be called again. Step 20 corresponds to step 42 shown in FIG. 2 , which is executed to reset the hardware. After receiving the resultant data, the external circuit sets the REQ signal to the low state, so that the IP component can clear temporary stored data and is ready to the next call. Step 42 is shown as a descending edge 60 REQ signal in FIG. 3 . When the REQ signal is at a low state, the hardware IP component stops outputting the resultant data and removes all the resultant data in the hardware IP component, as indicated by a descending edge 62 of a data signal shown in FIG. 3 . When the ACK signal is at the low state that indicates the resultant data has been removed completely, as indicated by a descending edge 64 of the ACK signal shown in FIG. 3 , the hardware IP component is ready for a subsequent operation.
- a double-check data representation is used to assure that output/input procedures have been completed, as well as execution of an error detection means.
- completion-detection or error-detection (CDED) parameter data is also input at the same time by using, for example, a complement technique (also used in step 40 ) which determines if the sum of the parameter data with the CDED parameter data equals ⁇ 1.
- a complement technique also used in step 40
- error detecting methods that can be used.
- the software function of this embodiment can be used to indicate the hardware IP component's performance or operation; and the software function can be repeatedly called, which means the hardware IP component can repeat the operation.
- the software function can be transformed into a practical hardware structure.
- the software function can be transformed into a well-known VHSIC (Very High Speed Integrated Circuits) Hardware Description Language (VHDL), and the VHDL is then transformed into a practical hardware structure.
- VHSIC Very High Speed Integrated Circuits
- VHDL Hardware Description Language
- the software function can describe the hardware's performance.
- the system-on-chip is designed to have more than one software function, since the hardware IP component corresponding to the software function is implemented in accordance with the above-mentioned steps and irrelevant to clock frequency, the different hardware IP components can have different clock frequencies. Therefore, the hardware IP component can perform correctly in either synchronous or asynchronous system-on-chip designs.
Abstract
Description
public static int sumTo(int CNT) --(1) | ||
{ | ||
int SUM = 0 ; | ||
for(int i =1 ; i <= CNT ; i ++) | ||
{ | ||
SUM += i ; | ||
} | ||
return SUM ; | ||
} | ||
int SUM = 0 ; | ||
for(int i =1 ; i <= CNT ; i ++) | ||
{ | ||
SUM += i ; | ||
} | ||
Claims (9)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW092120124 | 2003-07-23 | ||
TW092120124A TWI229276B (en) | 2003-07-23 | 2003-07-23 | Protocol method of reusable hardware IP |
Publications (2)
Publication Number | Publication Date |
---|---|
US20050086458A1 US20050086458A1 (en) | 2005-04-21 |
US7454604B2 true US7454604B2 (en) | 2008-11-18 |
Family
ID=34271456
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/851,098 Expired - Fee Related US7454604B2 (en) | 2003-07-23 | 2004-05-24 | Reusable hardware IP protocol method for a system-on-chip device |
Country Status (3)
Country | Link |
---|---|
US (1) | US7454604B2 (en) |
JP (1) | JP2005044328A (en) |
TW (1) | TWI229276B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11074207B1 (en) | 2020-01-29 | 2021-07-27 | Samsung Electronics Co., Ltd. | System-on-chips and methods of controlling reset of system-on-chips |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130329553A1 (en) * | 2012-06-06 | 2013-12-12 | Mosys, Inc. | Traffic metering and shaping for network packets |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6073267A (en) * | 1996-09-25 | 2000-06-06 | Nec Corporation | Semiconductor integrated circuit with error detecting circuit |
US20020101257A1 (en) * | 2001-01-30 | 2002-08-01 | Takayuki Kawahara | Semiconductor device |
US20040024895A1 (en) * | 2000-05-25 | 2004-02-05 | Michel Henrion | Method for mutual transfers of control parameters through a communications network |
US20040098701A1 (en) * | 2002-11-15 | 2004-05-20 | Mentor Graphics Corp. | Automated repartitioning of hardware and software components in an embedded system |
-
2003
- 2003-07-23 TW TW092120124A patent/TWI229276B/en not_active IP Right Cessation
- 2003-11-20 JP JP2003390857A patent/JP2005044328A/en active Pending
-
2004
- 2004-05-24 US US10/851,098 patent/US7454604B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6073267A (en) * | 1996-09-25 | 2000-06-06 | Nec Corporation | Semiconductor integrated circuit with error detecting circuit |
US20040024895A1 (en) * | 2000-05-25 | 2004-02-05 | Michel Henrion | Method for mutual transfers of control parameters through a communications network |
US20020101257A1 (en) * | 2001-01-30 | 2002-08-01 | Takayuki Kawahara | Semiconductor device |
US20040098701A1 (en) * | 2002-11-15 | 2004-05-20 | Mentor Graphics Corp. | Automated repartitioning of hardware and software components in an embedded system |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11074207B1 (en) | 2020-01-29 | 2021-07-27 | Samsung Electronics Co., Ltd. | System-on-chips and methods of controlling reset of system-on-chips |
US11609874B2 (en) | 2020-01-29 | 2023-03-21 | Samsung Electronics Co., Ltd. | System-on-chips and methods of controlling reset of system-on-chips |
Also Published As
Publication number | Publication date |
---|---|
TW200504537A (en) | 2005-02-01 |
JP2005044328A (en) | 2005-02-17 |
TWI229276B (en) | 2005-03-11 |
US20050086458A1 (en) | 2005-04-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW528944B (en) | A processing system and method of resetting a plurality of processing modules | |
JP4599266B2 (en) | Simulation apparatus and simulation method | |
CN114997087B (en) | Clock tree optimization method, optimization device and related equipment | |
CN111064449A (en) | Digital down-sampling filter verification platform and method based on UVM platform | |
CN114239453A (en) | Simulation verification platform construction method, simulation verification method, device and equipment | |
US9305125B2 (en) | Integrated circuit design timing path verification tool | |
US7454604B2 (en) | Reusable hardware IP protocol method for a system-on-chip device | |
CN109932995B (en) | Electronic device | |
US20060259753A1 (en) | Automatic halting of a processor in debug mode due to reset | |
CN111258371B (en) | Device, system and method for synchronizing counters among multiple FPGA chips | |
US7181559B2 (en) | Message based transport mechanism for level sensitive interrupts | |
CN114861594B (en) | Low-power-consumption verification method, device, equipment and storage medium of chip | |
GB2418269A (en) | A reusable hardware IP protocol method for designing a system-on-chip device. | |
US20190020462A1 (en) | Biometric sensing system | |
US7313672B2 (en) | Intellectual property module for system-on-chip | |
CN113177388A (en) | Device, system and method for testing and verifying IP (Internet protocol) core | |
US20050144586A1 (en) | Automated generation method of hardware/software interface for SIP development | |
US20060161422A1 (en) | Virtual emulation modules, virtual development systems and methods for system-on-chip development | |
NL1027012C2 (en) | Reusable hardware IP protocol for system on a chip devices, determines whether hardware IP parameters are required and enters function parameter or search signal | |
CN110765045A (en) | FPGA-based interrupt delay counting system and method | |
WO2024066950A1 (en) | Signal processing method, signal processing apparatus, chip, and electronic device | |
US20080288692A1 (en) | Semiconductor integrated circuit device and microcomputer | |
US20100110954A1 (en) | Method and system for synchronization between application layer controllers and wireless device | |
US7047436B2 (en) | Digital microelectronic circuit with a clocked data-processing unit and a converting unit | |
JP2004157646A (en) | Verification device for integrated circuit, verification method, and generation method for interface model for verifying integrated circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: TATUNG CO., LTD., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHENG, FU-CHIUNG;REEL/FRAME:015373/0843 Effective date: 20040312 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: TATUNG UNIVERSITY, TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TATUNG COMPANY;REEL/FRAME:022596/0617 Effective date: 20090414 Owner name: TATUNG COMPANY, TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TATUNG COMPANY;REEL/FRAME:022596/0617 Effective date: 20090414 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FEPP | Fee payment procedure |
Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20201118 |