NL1004164C2 - Digital filter bank - combines decimation in multi-rate system and distributed arithmetic algorithm in filter bank - Google Patents

Abstract

The filter bank includes an input signal selector which selects the output of an input signal or one out of a number of multi-level low communication signals. A filter bank unit receives the selected signal and defines the current level according to a level status control signal. A proceed wave filter outputs high, medium and low communication signals and feeds back the low signal to the input signal selector. A band selector receives the high, medium and low communication signals from the filter bank and determines one band signal for output.

Description

"DIGITAL FILTER RANGE STRUCTURE AND METHOD FOR OPERATING THESE"

Background of the invention

Field of the invention

The invention generally relates to a structure for digital filter devices and methods of operation thereof. In particular, the invention relates to a digital filter array device using the decimation type in a multi-frame system and using a distributed arithmetic algorithm for design simplification and reduction of physical structure dimensions necessary for device implementation as well as the corresponding method for operating in a time-multiplex mode.

Technical background

When processing audio and / or video signal such as 15 for speech, music, image and movies, digital signal processors (DSP) are often used to implement the necessary operations on digital data in processes such as storage to or retrieval from signal storage media, transmission from a source to a destination, and broadcast-20 thing. Digital signal processors are essentially independent processor integrated chain chips that are powered by firmware programs. These processors serve essentially the sole purpose of digital signal processing and are therefore more expensive to manufacture. However, a DSP design does not physically increase when the signal 5 increases the DSP processes in complexity in terms of, for example, the number and / or category of original signal sources. The complexity of the DSP processing is reflected in the software routines that must be performed to process the signal.

Another scheme for processing audio and / or video signals involves using arrays of either analog or digital filters (more commonly known as filter arrays) to divide an input signal into a number of signal groups, each with a narrower 15 frequency band than the original input. Each of these narrower frequency band signals is normally obtained from the original input signal, based on a general categorization, or on the specific characterization of its respective required processing accent. For example, for an input signal with mixed speech and music sources, in the filter-extracted part of the frequency-weighted speech signal, the processing accent will normally be on speech recognition, while for the music signal part, the processing accent should be on music signal synthesis, in addition to the compression processing which is both are required. Therefore, different signal processing schemes or algorithms will be required when performing specific tasks on the respective parts of the signal obtained from the original input 30 by the filter array device. This approach has an inherent drawback.

The general principle of using different task-oriented algorithms to separately process discrete portions of an input signal inevitably requires too many filter components in the filter array used to break down the original input. The greater the number of filter-obtained signals, the greater the number of required filters in the filter 1004164 3 series. Multipliers, adders and registers are the main building blocks for digital filters. Unfortunately, a digital multiplier is complicated in structure, much more than an adder or a register. Therefore, a product of this filter series processing scheme is a filter series device which has an excessive mold surface area when implemented in a semiconductor device.

The underlying concept of conventional filter arrays used in signal processing is briefly explained with reference to FIG. 1. FIG. 1 shows the block diagram of a conventional filter array that can be used to process audio and / or video signals. A number of R filters filter 1-R in the series have respective inputs connected to a common signal source input signal. Each filter in the series produces its own version of the filtered output, output signal 1-R, based on the inherent filter characteristic assigned and built into it. Each of the filtered output signals has a frequency band 20 that is narrower than that of the original input signal. Generally, the frequency bands of the filtered output signal output signal 1R are not overlapping, or slightly overlapping each other.

Based on differences in filter characteristics, digital filters can generally be categorized as finite impulse response (FIR) or infinite impulse response (I IR) filters. The theory of operation and characteristics of these digital filters are well known to those skilled in the art, and information can be found in many filter-related handbooks and will not be further explained here except for a brief explanation of a drawing to illustrate the principle of demonstrate the invention. For this purpose, Fig. 2 shows a network diagram of a digital filter with FIR characteristics, and Fig. 35 shows a network diagram of a digital filter with IIR characteristic, with a direct form I, while Fig. 4 shows a network with IIR characteristics with a direct form II.

1004164 4

As shown in Figures 2, 3 and 4, when considering a digital filter device, either with the FIR characteristics of Figure 2 or the IIR characteristics of Figures 3 or 4, with an external input signal represented by X ( n) at a time n applied to the input, a filtered signal Y (n) is generated at the output. In the examples of the IIR digital filters of both Figures 3 and 4, a pole signal W (n) is used to indicate an intermediate value of the input signal X (n). This is suitable for the mathematical characterization of the filters, which will be shown in the following expressions, which use a time series to express the signal from the filter output Y (n) as a function of the input signal X (n).

Suppose that in the drawings of Figures 2, 3 and 4, in which each of the filters is modeled as a network of characterized nodes, hc.-hH, a.-aN_ ,, b; -BN .., and c: i-cN_: display filter characteristic coefficients for the described filter at times n = 0, 1, 2, ..., N-2 and N1 20 respectively. In either FIR or IIR filters, a series of expressions expresses the filter output signal Y (n) at time n as a function of the input signal X (n). Specifically, for the described IIR digital filter with direct form I of fig. 3: 2 W (n) = b, xX (n) + b; xX (n-1) + b2xX (n - 2) +. . . + bN_, xX (n- (N-1)), (l) and Y (n) = W (n) + axxY (η -1) + a2xY (n-2) +. . . + aN ^ xY (n- (N-1)). (2)

In this manner, the filter output signal Y (n) at time n can be numerically determined by first evaluating the pole signal value W (n) at time n in an expression that sums a time series of products. As shown in the above expression (1) as well as schematically shown in Fig. 3, each of the input signal values X (n1), X (n-2), ..., X (n- (N-1)) is set at times preceding 35 to n multiplied by a corresponding coefficient 1 0 0 4 1 6 4 5 bo-iVj and then summed together to obtain the pole signal value W (n) at that particular time. In turn, the filtered output Y (n) can be determined at the same time n using expression (2), which also sums a range of products. This mathematical modeling characterizes an IIR digital filter as a series of cascaded network nodes, each delayed with respect to the preceding ones and related by a function Z ', as indicated schematically in the drawing.

The IIR form II digital filter of Fig. 4 can be modeled using similar numeric expressions: W (n) = X (n) + a, xW (n-1) + a; xW (n-2) + . . . + aN..xW (n - (N -1)) (3) 15 and

Yin) = c. xW (n) + c: xW (η -1) + c: xW (n - 2) +. . . + c;,., xW (n- (N -1)). (4)

The simple time sequence equations (1) and '2; (as well as (3) and (4)) for numerically determining the filtered signal output value of an IIR digital filter are, clearly and easily realized when fabricated on a semiconductor device, often impractical when actually implemented. This is because a number of digital adders, multipliers and shift registers are required to perform the numerical evaluations set out in the equations. The size of the digital components increases linearly as the order of an implemented filter increases. When a digital filter array device is designed using these IIR digital filters 30 to process a signal source with multiple sub-sources of music, speech, video, etc., the total number of adder / multiplier (shift registers) increases to a level hardly practical. is for fabrication in a semiconductor integrated chain device. The reason 1004164 for this is, as noted above, that digital multipliers require extensive device matrix surface areas for implementation. Therefore, the dilemma of this implementation is clear: simple in concept, but impractical in application

Summarizes the invention

It is therefore an object of the invention to provide a digital filter array structure and method for its operation, which uses the principles of both decimation in multi-rank systems and uses a distributed arithmetic algorithm to simplify the total digital filter structure configuration using a minimum time multiplex set of filter hardware.

It is another object of the invention to provide a digital filter array structure and method of operation using the principle of decimation and using distributed arithmetics to organize the digital filter arrays of the device in such a way, that the structure has a reduced die surface area of the semiconductor device, which allows for practical implementation.

The invention achieves the above objects by providing a digital signal filter array device for filtering an external input signal to produce a filtered digital output signal. The digital filter device includes an input signal selector with two inputs, for selecting as output thereof either the input signal or a recursive feedback of one of a number of low-pass filtered signals. A filter sequence has an input connected to the output of the input signal selector to receive the output of the input signal selector. The filter array filters this signal and produces high-pass and low-pass filtered signals using a distributed arithmetic algorithm and using a calculation procedure involving the summing of product terms. The 1 0 0 4 1 6 4 7 low-pass filtered signal is fed back to the input selector as one of a number of low-pass filtered signals. The low-pass filtering further utilizes sample rate decimation for each of the 5 recursive feedback outputs to the input signal selector. The apparatus further includes a frequency band selector having an input connected to the output of the filter array for receiving the high pass filtered signal as an input and generating the filtered digital output signal from the digital filter array device.

The invention further achieves the above objects by providing a digital signal filter array device with a filter array comprising a plurality of filters organized as one array of filters. The filters generate filtered outputs with frequency bands that do not overlap or only slightly overlap.

The invention further achieves the above objects by providing a digital signal filter array device in which the filters contain at least one high-pass filter that produces the high-pass filtered signal and a low-pass filter that generates the low-pass filtered signal.

The invention further achieves the above objects by providing a digital signal filter array device in which the filters contain at least one high-pass filter that generates the high-pass filtered signal, a low-pass filter that generates the low-pass filtered signal , and a plurality of band flashes generating a number of band filtered signals, which are also provided to the frequency band selector.

The invention further prepares the above objects by providing a digital filter array device, wherein each of the filters includes a first and a second signal -35 selector, a pool signal processor, a parallel series converter and transmitter, a shift register, a first memory, a second memory, and a zero signal processor. The first signal selector has an input for receiving the selected output from the input signal selector and another input for receiving a first memory data output from the first memory for a selective transmission as the first selected signal.

The pool signal processor is connected to the first and second signal selectors to receive the first selected signal and a second selected signal generated by the second signal selector to generate a pool signal using the divided arithmetic algorithm to sum of products. The second signal selector has an input connected to the pool signal processor for receiving the pool signal, and another input for receiving the data output from the first memory, for selectively generating as the second selected signal, the second selected signal is fed back with the pool signal processor. The parallel series converter and transmitter is connected to the pool signal processor to receive the pool signal and convert it from a parallel signal to a series signal for transmission. The shift register is connected to the parallel series converter and transmitter to receive a serial signal and to construct first and second memory addresses using bits of the serial signal data. The first memory then addresses the shift register to retrieve first digital filter characteristic coefficient data stored in memory locations therein, the retrieved first digital filter characteristic coefficient data 30 being generated as the first memory data and supplied to the second input. from the first signal selector and at the second input of the second signal selector. The second memory then addresses the shift register to retrieve the second digital filter characteristic coefficient data stored in memory locations therein, the retrieved second digital filter characteristic coefficient data being generated as second memory data for transmission. The zero signal processor is tied to a second memory to receive the second memory data to generate the second memory data and independently transfer them as high-pass and low-pass filtered signals of the filter array, using the distributed arithmetic algorithm to calculate a sum of products.

The invention further provides the above objects by providing a method of operating a digital filter array device for filtering an external input signal to generate a filtered digital output signal. The digital filter array device includes an input signal selector, a filter array, and a frequency band selector. The input signal selector has two inputs and selects either the input signal or the recursive feedback of one of a number of low-pass filtered signals as output. The filter array has an input connected to the output of the input signal selector and receives the output of the input signal selector for filtering, to generate high-pass and low-pass filtered signals using a distributed arithmetic algorithm to calculate a sum of products. The low-pass filtered signal is fed back with the input selector as one of a number of low-pass filtered signals. The low pass filtering process further utilizes decimal in the sample rate for each of the recursive feedback signals provided to the input signal selector. The frequency band selector has an input connected to the output of the filter array for receiving the high-pass filtered signal as an input and for generating the filtered digital output signal from the device.

The invention further achieves the above objects by providing a method of operating a digital filter array for filtering an external input signal to generate a filtered digital output signal. The digital filter array includes an input signal selector, a filter array, and a frequency band selector. A summation of the calculation of the products is started by storing an initial product term in an accumulator. The input signal is provided to a pool signal processing unit. The pool signal processor lifts the input signal at the product term stored in the accumulator to obtain a pool signal. The pool signal processing unit sends the processing signal to a parallel series conversion and transmission unit and to a second selector. The parallel series conversion and transmission unit converts the processed data signal and transfers it as a sequence of serial bits to a shift register. The shift register addresses a memory location in first and second memories upon receiving each of the corresponding bits of a zero-order term of processed data, which are converted and transmitted by the parallel series conversion and transmission unit. The first and second memories retrieve the respective memory contents held in memory locations corresponding to those addressed by the shift register. The zero-order term data held by the first memory is retrieved to the pool signal processor and stored therein. The second memory retrieves its addressed zero-order term memory content to the zero signal processing unit. The shift register transmits its first order term of the pole signal data received from the parallel series conversion and transmission unit to both the first and second memory. The first and second memories retrieved their respective addressed first order term memory contents. The first order term data held by the first memory is retrieved to the pool signal processor. The pool signal processing unit divides the stored zero order term data a given number of times and adds it to the first order term data to obtain the new pool signal. The pool signal processing unit retrieves the new pool signal to only the second selector. The second memory retrieves its first order term 1004164 11 data to the zero signal processing unit, which adds it to the zero order term data divided a given number of times. The zero signal processing unit completes and generates the filtered signal data. The pole signal processing unit generates a sum of products for the zero signal processing unit to transfer as the filtered output of the device. This process is repeated until all order terms are complete.

10 Brief description of the drawings

Other objects, features and advantages of the invention will become apparent from the detailed description of the preferred but non-limiting embodiments. The description is made with reference to the accompanying drawings, in which:

Fig. 1 shows a block diagram of a conventional filter array used for signal processing;

Fig. 2 shows a network diagram of a digital filter 20 with finite impulse response (FIR) characteristics;

Fig. 3 shows a network diagram of a digital filter with infinite impulse response (IIR) characteristics having a direct form I;

Fig. 4 shows a network diagram of a digital filter 25 with infinite impulse response characteristics of a direct form II;

Fig. 5 schematically shows the hierargically characterized use of five digital filter arrays using the principle of decimation, according to a preferred embodiment of the invention;

Fig. 6 shows a timing chart showing the timing of the filter-energizing control signals for the five stages of the digital filter arrays of FIG. 5, using the principle of decimation, in accordance with a preferred embodiment of the invention; 1004164 12

Fig. 7 is a block diagram schematically showing the hardware configuration of a digital filter array device using a recursive feedback scheme, according to a preferred embodiment of the invention; FIG. 8 is a block diagram schematically showing the hardware configuration of a filter array unit including the digital filter array device of FIG. 7, using a distributed arithmetic algorithm according to a preferred embodiment of the invention; FIG. 9 schematically shows an input signal selection unit, in accordance with a preferred embodiment of the invention;

Fig. 10 schematically shows a frequency band selection unit, according to a preferred embodiment of the invention;

Fig. 11 schematically shows a selector for the digital filter array unit of FIG. 8, according to a preferred embodiment of the invention;

Fig. 12 shows an operating schedule of the selector of FIG. 11;

Fig. 13 schematically shows another selector for the digital filter array unit of FIG. 8, according to the preferred embodiment of the invention;

Fig. 14 shows an operating time diagram of the selector 2 of FIG. 13,

Fig. 15 schematically shows the pole signal processing unit of FIG. 8, according to a preferred embodiment of the invention;

Fig. 16 shows an operating time diagram of the pile seam sewing processing unit of FIG. 15,

Fig. 17 schematically shows the parallel series conversion and transmission unit of FIG. 8 according to a preferred embodiment of the invention;

Fig. 18 shows an operating time chart of the parallel series conversion and transmission unit of FIG. 17

Fig. 19 schematically shows the shift register of FIG. 8 according to a preferred embodiment of the invention; 1004164 13

Fig. 20 shows an operating time schedule of the shift register of FIG. 19;

Fig. 21 schematically shows the zero signal processing unit of FIG. 8, according to a preferred embodiment of the invention; and

Fig. 22 shows an operation timing of the zero signal processing unit of FIG. 21.

Detailed Description of the Preferred Embodiment The underlying principle of operation of the hardware structure of the digital filter array device of the invention combines two concepts of hardware control schemes. One concept is "decimation in a multi-rank system", the other is "shared arithmetic algorithm-15 me". Both concepts of hardware control schemes are implemented in the device hardware in a time-multiplexed manner.

Essentially, a limited or, in other words, a minimum number of logic components constituting a digital filter 20 is housed in a digital filter array hardware device operating in a frequency-time hierarchically arranged recursive feedback usage scheme based on the concept of decimation of multi-rank system. Such a digital filter array hardware device operates according to the numerical analysis model with summing of products to generate the filter output signal and the calculations are performed in a soft twar scheme based on the concept of a distributed arithmetic algorithm. The use of this mini-30 mum hardware is further made possible by the use of a time-multiplex scheme for the implementation of both the decimation and the shared arithmetic principles of signal processing. The use of such a digital filter array device results in a digital filter hardware architecture which has a semiconductor device matrix surface area significantly reduced by those built around the prior art. concept.

Decimation is used in a system that works at different speeds in different work steps. The decimation is characterized by the repeated use of a limited number of digital filters in a scheme that is hierarchically arranged, time-multiplexed, and involves recursive feedback. Using this limited number of filters, an input signal 10 is divided into a number of frequency bands based on the characteristics and processing requirements of the incoming signal source. Also, the processing applied to each designed frequency band can be accentuated according to the specific requirements of different algorithms.

The concept of a distributed arithmetic algorithm involves processing a signal to generate a summation of products as required for a filter output signal value determination for the digital filters as described above. This concept is characterized by fast processing using fast memory devices with predetermined characteristic coefficients as the contents of a look-up table.

For a detailed description of the hardware concept of decimation in multi-rank systems, see FIG. 5. FIG. 5 schematically illustrates the hierarchically characterized time usage of a number of digital filter arrays using the decimation principle in accordance with a preferred embodiment of the present invention. As shown in the drawing, decimation with different operating speeds is performed by digital filter device hardware architecture using five sets of digital filters SERIES -4-4 although more or less than five series can be used as will be apparent to those skilled in the art.

Each of the digital filter arrays SERIES 0-4 may include the same or similar structural configuration, although this is not necessarily the case. For the sake of clarity in the following description, for example, the hardware configuration in which all five arrays have a similar structural configuration is shown in the drawing. Thus, each filter-5 array includes a high-pass filter HPF, a low-pass filter LPF, and a plurality of N band flashes BPFI-N. The band filters can be omitted in some applications. In other words, the band filters BPF1-N are optional within the scope of the invention.

Essentially, each of the five filter arrays SERIES 0-4 has a high-pass filter HPF providing a high-pass filtered signal, a low-pass filter LPF providing a low-pass filtered signal, and a plurality of band filters BPF1-N that provide respec. -15 tive band-filtered signals. All filter impulse responses within the same series may have non-overlapping or slightly overlapping frequency bands with a cutoff frequency of no more than 3dB, as well as the above conventional filter series devices. These filter arrays SERIES-204 can be cascaded in the direction that the input signal is processed, as shown schematically in the drawing. At this stage, however, it should be noted that there is in reality no physical cascade of filter arrays, as the following descriptive paragraphs explain. The first series SERIES has all inputs of the high-pass, low-pass, and band filters HPF, LPF, and PBF1-N connected together and is powered by the external input signal INPUT SIGNAL. Therefore, these stages will be referred to as being virtually cascaded. The high pass and band filters in SERIES, in turn, generate filtered signals, so designated as the first stage outputs FIRST STAGE HIGH TRANSMISSION and FIRST STAGE BANDSNAL1-N m in the drawing, respectively. The output of the low pass filter from SERIES, first stage low pass signal serves as input to all filters, including high pass, low pass, and band filters, of the second filter series SERIES.

1 0 0 4 1 64 16

In a similar arrangement, the second series SERIES 1 has all the inputs of the high-pass, low-pass and band filters HPF, LPF and BPF1-N bound together and is powered by the FIRST STAGE LOW-SIGNAL. The high-5 pass and band filters in SERIES generate filtered signals, which will be referred to as the second stage outputs, respectively, referred to as SECOND STAGE HIGH-LEVEL SIGNAL and SECOND STAGE BAND SIGNAL1-N. The low pass filter output of SERIES 1, in turn, serves as 10 inputs for all filters, including high pass, low pass, and band filters of the third series of filters SERIES 2. This virtual cascaded arrangement continues for all five sets of digital filters SERIES-4 as shown in Fig. 5. Therefore, the fifth series 15 SERIES4 has an arrangement of filtered output signals FIFTY STAGE H00GD00RLAST SIGNAL, FIFTH STAGE TAPE LOW-THROUGH .

At the outputs of each of the first four of the five series of filters SERIES-3, namely at each of the 20 first, second, third and fourth stages, each of the filtered outputs of the respective low-pass filters LPF, especially first, second, third and fourth stages low pass signal "decimated" in terms of time frequency before being supplied to the inputs of the filters in the next cascaded sequence. By definition, an M-fold decimation refers to a sample rate, which decreases by 1 / M, with each M-th output (i.e., filtered output) of the selected filter, for example, the low-pass filters 30F LPF four series SERIES-3, is selected to be provided as the input to the next series of filters.

Therefore, in a filter array device similar to that shown in FIG. 5, with a virtual hierarchically cascaded configuration with Q stages of filter arrays, an M-fold decimation in each of the arrays results in a proportionally decreased degree of operation in each of the subsequent filter arrays 1004164. This is known as a multi-speed system, since stages in the filter array device sample input signals at different speeds. Specifically, the first stage of the filter arrays in one direction supplies an input signal to the next cascaded (second) stage at a working sample frequency that is M times the frequency that the second carries to the third. In this way, in the fifth stage of the filter arrays of the device shown in FIG. 5, have an in-10 input signal sampled at 1 / M4 of the rate at which the original signal was sampled at the first stage. This situation is better shown in Fig. 6, which is a timing chart showing the timing of the filter energizing control signals L [1], L [2], ..., and 15 L [5] of the five stage digital filter arrays shown in FIG. 5 and use the principle of decimation.

Suppose that in the filter enable control signal sequence for the device of FIG. 5 shown in FIG. 20 6, is a positive logic for the filtering enable signal. In other words, the filtering operation in a series of filtering series is released only when the corresponding filter-releasing control signal L [1: 5] of the five-stage digital filter series configuration 25 of FIG. 5 is a positive pulse. As those skilled in the art understand, the five filter release control signals L [1: 5] outlined in FIG. 6 for the five-stage device of FIG. 5, are easily implemented using, for example, standard discrete logic components.

In the time chart example of FIG. 6, a two-fold (M = 2) decimation is now also assumed. The basic time unit of the entire filter device is provided by the time slot units in the first stage of the filter arrays. The total of 24 base time units are shown for a description of this dual decimation scheme. It is also believed that the control signals are triggered at the falling edge. In particular, at the falling edge of the control signal L [i] in the base time slot 0, the first active period of the control signal L [2] for stage 2 of the filter series is triggered. This first control signal of L [2] is maintained for the entire duration of the basic time slot 1. After this first control signal for L [2] 5 no longer has its influence when time slot 1 expires, the second active period of the control signal L [increases l] again in the third base time slot 2.

In this manner, the filter enable control signal for stage 2 of the filter arrays of the device shown in FIG. 5, adopt a sample rate of one effective filter release pulse per four basic time slots, a two-fold sample rate decrease relative to that of stage 1. Similarly, the filter enable control signal for stage 3 of the filter series takes a sample rate to one effective release pulse per 8 basic time slots, or one release pulse per two release pulses in step 2, a further two-fold decrease in sample rate. Therefore, the filter release control signal sequence for the fifth stage of the filter arrays in the device of FIG. 5 is one effective pulse per 32 basic time slots.

An important characteristic of this filter release scheme for the total of five stages of filter arrays in the device of FIG. 5 should be emphasized. From the shown control time diagram of FIG. 6, it can be seen that no two filter-free control signals are simultaneously output during a time slot. This relates to the above indication that no substantial physical cascade of filter arrays is necessary to implement the digital filter device of the invention.

This control of the control signals is of particular interest to the invention as it allows the use of only one, rather than five, sets of high-pass, low-pass and band flashes to perform all of the digital filtering on the incoming signal INPUT_SIGNAL, in a diagram outlined in the control sequence diagram of FIG. 6, in the manner of the 1004164 19 configuration of FIG. In other words, since, as noted above, each of the filter enable control signals L [1], L [2], ..., and L [5] for the described five stages of digital filter arrays, shown in fig. 5, 5 is independently active (on the time axis), only one of the five sets of filters (SERIES 0 for example) is required, if used repeatedly, to function as equivalent to the first, second, third, fourth and fifth stages of the filter set of FIG. 5. The time-multiplex-10 use of a single series of high-pass, low-pass and band filters is characteristic of the decimation concept in multi-speed systems. There are five different sample rates, which in the operation of the system shown in FIG. 5 and 6 are used. However, those skilled in the art will recognize that more or less than five sets, or five times repeated use of a single set of high pass, low pass and band filters may be used in the signal processing procedure, depending on the system design requirements.

Again referring to the schematically shown hierarchical configuration of FIG. 5, an incoming external signal INPUT_SIGNAL to be processed by the filter sequence device is provided to the combined inputs of all high pass, band and low pass 2Ξ pass filters in the first stage (filter sequence SERIES 0) for the entire time sequence of all outlined basic time slot units, shown in fig. 6. However, there is only one stage of filter arrays in the entire device, shown in FIG. 5, which is released at a given time around the corresponding selected signal of the frequency band of the original input signal, as indicated above. Therefore, there is no situation where two filter-release control signals must be delivered simultaneously throughout the device. This allows for the repeated time multiplexing, as noted above, of the single set of filter array hardware in performing the digital signal processing necessary to implement the digital filter scheme of the invention. Furthermore, this scheme also satisfies the general requirement that high frequency parts of the original signal be sampled at a higher sample rate, while the 5 low frequency parts are sampled at a lower sample rate for successful filtering.

A preferred embodiment of the digital filter device according to the invention is described below to demonstrate how the hierarchically arranged configuration 10 of FIG. 5 can be implemented essentially in a digital filter device. For this purpose, reference is made to FIG. 7. FIG. 7 is a block diagram schematically showing the hardware configuration of a digital filter array device using a recursive feedback scheme 15 according to a preferred embodiment of the invention. As shown in the drawing, the inventive digital filter array device is generally indicated by reference numeral 10, a hardware architecture comprising an input signal selection unit 20, a filter array unit 20, and a frequency band selection unit 40. Essentially, the filter array unit 30 is a hardware structure that is functionally equivalent to one of the five combined filter arrays SERIES-4 shown in FIG. 5, assuming that a device using the five-25 stage decimation described above with respect to FIG. 5 and 6, again used as an example.

At the input end of the input signal selection unit 20, the external input signal 21 together with all five low-pass filter outputs of the respective five equivalent stages of the filter arrays SERIES-4 (denoted as label le_, 2e_, 3e_, 4th_ and 5th_TRAP_LOW-BY-LAST_SIGNAL in Fig. 5 but as respective reference numerals 331-335 in Fig. 7) is provided for selection by the input signal selection unit 20. Only one of these six signals is selected at a given time for sampling and is provided to the next connected component, the filter array unit 30. As the original signal to be processed by the inventive device 1004164 21, the external input signal 21 may be an analog signal which is suitably sampled and converted to a digital format. Furthermore, as described below, each of the five low pass 5 filter outputs 331-335 provided to the input signal selection unit 20 is properly decimated in the filter sequence unit 30 in its respective recursive feedback decimation cycle before being returned. routed to the input signal selection unit 10 20.

The filter array unit 30, as in the case of the filter, shown in FIG. 5 and 6, may contain a virtual arrangement of a number of (in this example 5) filter arrays, which is physically only one array used in a time multiplex scheme. Each of the virtual series, or the single actual series, includes at least one high-pass filter 31 (HPF in Fig. 5) and at least one low-pass filter 35 (LPF) plus a number of optional band filters 33 (PBF1-R) . Since the band filters 33 20 are optional, none of them need be included in the filter array unit 30, but at least a pair of high-pass and low-pass filters 31 and 33 must be included for reasonable operation of the device.

The result of the selection from the external input 25 21 and the back-routed low-pass filter outputs 331-335 by the input signal selection unit 20, i.e. the filter input signal 23, is applied to the inputs of all filters in the first stage of the filter array unit 30, as described above. A filter enable control signal maintenance scheme, such as the one that controls signal L [1: 5] described with respect to FIG. 6 is then applied to the corresponding filters in all five series of the filter series unit 30.

The application of this filter release scheme through the filter sequence unit 30 results in a collection of filtered output signals, some of which are subsequently provided to the frequency band selection unit 40, 1 0 0 4 1 6 4 22 while others are routed back recursively. to the input signal selection unit 20. Essentially, as described above, the outputs of all high pass and band filters, signals 371-375 and signals 381-385 (corresponding to le_-5e_TRAP-HOOGDOOR-LAT_SIGNAL and le_TRAP_BAND_SIGNAL- R of the five stages of the device of Fig. 5), respectively in the filter array unit 30, is independently provided at the input of the frequency band selection unit 40, as determined by the clearing scheme shown in Figs. 6. Likewise, the outputs of all low-pass filters, or the signals 331-335 (respectively corresponding to le_-5e_TRAP_LAG-TRANSMIT_SIGNAL of the device of Fig. 5) in the filter sequence unit 30 are fed back recursively with the input-15 signal selection unit 20. based on the same release schedule.

At the frequency band selection unit 40, one of the high-pass and optional band-filtered signals 371-375 and 381-385 respectively, as well as the low-pass filtered signal 335 of the low-pass filter in the last stage of the virtual filter sequence in the filter array unit 30, selectively selected for generation as the filtered output signal 41 of the device.

Assuming a dual decimation is again used for operation of the filter string unit 30 shown in FIG. 7, at the very beginning of the filter operation, the input signal selection unit 20 first selects the external input signal 21 as the filter input signal 23, and provides it to the filter sequence unit 30. During this first stage, the low-pass filter 25 in the filter sequence unit 30 generates a low-pass filtered signal 331 for feedback to the input signal selection unit 20. This first stage feedback low-pass signal 331 upon receipt at the input signal selection unit 35 is available for selection as the filter input signal 23 during the second stage of the operation of the f filter string unit 30. The selection of the low-pass filtered signal 331 will occur as part of the filter-clearing scheme once in every two appearances thereof (every four time slots), since the example assumes a two-fold decimation. Similarly, the second stage low pass filtered signal 332 will be selected as part of the filter release scheme once in every two appearances thereof (every eight time slots) at the input of the input signal selection unit 20, as the filter input signal 23, which is provided to all filters during the third stage of operation of the filter sequence unit 30. Likewise, the fifth stage low pass filtered signal 335 will be selected in a schedule once during every two appearances thereof at the input signal selection unit 20 and will be provided to all filters during the fifth stage of operation of the filter array unit 30.

At the frequency band selection unit 40, as described above, the high pass and optional band filtered signals 371-375 and 381-385, respectively, as well as the low pass filtered signal 335 2C of the last stage low pass filter are provided for selection. as the filtered output signal 41 of the device. The selection decision for the terminal output signal of the device is also based on the filter release scheme. The correspondence of the output signal selection in the frequency band selection unit 40 of the digital filter array device 10 with the filter enable control signal output scheme of FIG. 6 is described below and shows the detailed operational steps that are made with respect to the 30 base time slot units.

As shown in Fig. 6, during the base time slot is 0, L [1] = i, indicating that the digital filter array device 10 is in the first stage of filtering operation, herein referred to as being in the first stage state. In this state, the input signal selection unit 20 selects the external input signal 21 to provide it to the filter sequence unit 30. Since the filter sequence unit 30 is in the first stage condition, 1004164 24 thus generates a first stage high pass filtered signal 371. , a set of optional first stage band-filtered signals 381 (381_1-R), assuming that a total of R band filters are present) as well as a first stage low-pass filtered signal 331. These outputs are maintained until the following time slot for the first stage, base time slot 2.

During the base time slot 1, L [2] -1 means that the digital filter array device 10 is in the second stage. In this state, the input signal selection unit 20 selects the feedback first stage low-pass filtered signal 331 to provide it to the filter array unit 30. Since the filter array unit 30 is in the second stage state, it generates this mode a second stage high pass filtered signal 372, a set of optional second stage band filtered signals 282 (382_1-R, again assuming that the total of R band filters are present), as well as a second stage low pass-filtered signal 332. These output signals 20 are again maintained until the next time slot for the second stage, base time slot 5.

Then again, during base time slot 2, L is [1] = 1, indicating that the digital filter array device 10 is in a first stage state. In this state 25, the input signal selection unit 20 again selects the external input signal 21 to provide to the filter sequence unit 30. Since the first stage condition is again established, the filter sequence unit 30 generates the first stage high-pass filtered signal 371, the 30 collection of optional first stage band-filtered signals 381 (38i-1-R, assuming that the total of R band filters are present), as well as the first stage low-pass filtered signal 331. These outputs are again maintained until the following basic time-35 slot for the first stage, base time slot 4.

Based on the same control, the digital filter array device 10 is driven to operate on the external input signal 21 in accordance with the filter control scheme shown in FIG. 6 to generate the filtered output signal 41. Again, attention is drawn to the fact that no two filter stages are valid simultaneously, and thus the filter-5 arrays are time-multiplexed at a number of sample rates, using a single sample rate. set of filters.

The following paragraphs detail the design of the basic input signal selection unit 20, the filter sequence unit 30, and the frequency band selection unit 40, which together form 10 in the digital filter sequence device 10. In the following examples, it is assumed that there is a digital filter array device 10 with a five-stage configuration operating under a dual-decimation sample scheme.

Fig. 9 is a simplified schematic of an input signal selection unit 20 according to a preferred embodiment of the invention. As noted above, it is again assumed that there is a five-stage filter array device 10, and the input signal selection unit 20 is shown and generally includes an arrangement 90 of 20 three-state buffers.

It should be noted that, under normal circumstances, practical filter devices such as the filter array device 10 will process digital audio and / or video signals with a resolution of more than a few bits. For example, conventional digital music signals processed in audio equipment such as audio compact disc players usually have a resolution of 14 to 16 bits. In the example of FIG. 9, a 16-bit signal resolution is used, indicated by the destination of the input signal as XIN [0:15].

Therefore, the arrangement of the three-state buffers includes five sets of buffer devices, generally designated IBUF1 [0:15], IBUF2 [0:15], IBUF3 [0:15, IBUF4 [); 15), and IBUF5 [0:15], Each of the five sets of buffers contains a total of 16 three-state buffers, which is apparent from the reference numerals, although not shown separately in the drawing. For example, the set of buffers with 1 0 0 4 1 6 4 26 contains three states IBUF1_0-15 buffer devices IBUF [0], IBUF1 [1], ... and IBUF1 [15].

Therefore, the input end of the input signal selection unit 20 is powered by the digital external input signal XIN [0:15], which has a data width, or resolution, of 16 bits, as well as four other recursive feedback low-pass filtered signals. a width of 16 bits FBI [0:15], FB3 [0:15] and FB4 [0:15]. Specifically, each of the 16 data bits of the external input signal XIN0: 15 is supplied to the corresponding input line of the first set of three-state buffers IBUF1 [0:15]. Each of the 16 low-pass filtered signal bits FBI [0:15] fed back from the first stage filter sequence output of the filter array 15 is supplied to the corresponding input line of the second set of three-state buffers IBUF2 [0:15 ], and each of the 16 low-pass filtered signal bits FB4 [0:15] fed back from the fourth stage filter sequence output of the filter array 20 unit 30 is provided to the corresponding input line of the fifth array of three state buffers IBUF5 [ 0:15], etc.

In FIG. 9, an inverted version of the filter enable control signal LB [1: 5] is shown, which is generated and provided to the buffer control input pins of the five sets of three-state buffers in the arrangement 90. The inversion is necessary, since the three-state buffers in the arrangement 90 are shown with active low output enable control inputs. As will be apparent to those skilled in the art, the original ie non-inverted version of L [1: 5], such as that described with respect to FIG. 6, are used to directly control the output enable inputs of the three-state buffers, provided that another compatible version of a three-state buffer 35 is used in the arrangement 90.

Particular attention should be given to the fact that the outputs of the five sets of buffers with three states IBUF [0:15], IBUF2 [0:15], IBUF3 [0:15], 1004164 27 IBUF4 [0:15] and IBUF5 [0:15] are connected together in a wiring OR manner. More specifically, the outputs of the three-state buffers IBUF1 [0], IBUF2 [0 [, IBUF3 [0], IBUF4 [0] and IBUF5 [0] are linked together, the outputs of the three-buffer buffers states IBUF1 [1], IBUF2 [1], IBUF3 [1], IBUF4 [1] and IBUF5 [1] are connected together etc. A total of 16 lines, each containing five connected outputs, are formed to output the output signal OUT [ 0:15] with a data width of 16 bits. it is possible to connect these outputs together because the buffers in the arrangement 90 naturally have three states and only one of the five sets of buffers in the arrangement 90 is designed such that it is energized by the control signals LB [1: 5] a given time.

When LB [1] = 0 and LB [2: 5] = 1, the result obtained at the output OFF [0:15] of the input signal selection unit 20 is: OFF [0:15] = XIN [ 0:15].

Similarly, when LB [2] = 0, LB [1] = i and 20 LB [3: 5] = 1, the result obtained at the output OFF [0:15} of the input signal selection unit is 20 ·.

OFF [0:15] = FBI [0:15].

Based on the same reasoning, therefore, the filter release control signals L [1: 5] or in particular the inverted versions LB [1: 5] can be used for the hierarchically-characterized and time-multiplex control of the filter arrays by appropriately filter input signal to be processed by assigning the operation of the input signal selection unit 20. Either the original input signal data word XIN [0:15] or one of the low-pass filtered signal words FBI [0:15] -FB4 [0:15] that are fed back by the corresponding stage of the filter set can be selected and 1004164 28 sent to the filter string unit 30 connected together for the required filter processing.

The design of the input signal selection unit 20 described above assumes a two-fold decimation scheme for the low-pass filter sample operation, as indicated above. In the embodiment of the inventive digital filter array device 10 shown in FIG. 7, either the original input signal data word XIN [0:15] or one of the low-10 pass-filtered signal words FBI [0:15] -FB4 [0:15] which can be fed back by the corresponding stage of the filter sequence in this way are selected by the input signal selection unit 20 as the input to the filter sequence unit for subsequent filter processing. Due to the recursive flow of low-pass filtered feedback signals, each low-pass filtered signal will be selected for subsequent filter processing only once every two appearances at the input of the input signal selection unit 20, drawing attention to the fact that a dual decimation- schedule is used.

The frequency band selection unit 40 used in the inventive digital filter array device 10 shown in FIG. 7, is now discussed. Fig. 10 is a simplified schematic diagram of the frequency band selection unit 40 in accordance with a preferred embodiment of the invention. In describing the frequency band selection unit 40, it is assumed that the digital filter sequence unit 10 includes five stage filter sequences 30 operating under a two-fold decimation scheme. As shown in the drawing, the frequency band selection unit 40 is shown as generally comprising an array 100 of three-state buffers.

Particular attention should again be paid to the fact that the components of the filter sequence device 10, the input signal selection unit 20, the frequency band selection unit 40, and the filter sequence unit 30 can process an audio and / or video digital data signal 1004164 29 with a few bit resolution. In the example of FIG. 10, a 16-bit signal resolution is again used, as indicated by using the YUIT [0:15] designation for the output of the filter array device 10.

The multiple number array of three-state buffers comprises six sets of buffer devices generally referred to as FBBUF1 [0:15], FBBUF2 [0:15], FBBUF3 [0:15], FBBUF4 [0 : 15], 10 FBBUF5 [0:15] AND fbbuf6 [0:15]. Each of the six sets of buffer devices comprises a total of 16 three-state buffers, again not individually but instead shown collectively in the drawing. For example, the set of three-state buffers FBBUF1_0-15 contains the buffer devices FBBUF1 [0], FBBUFl [1], ...

and FBBUF1 [15].

Therefore, the input end of the frequency band selection unit 40 is powered by the outputs of the filter array unit 30, as shown in FIG. 7. In Figure 7, it can be seen that the filter array unit 30 provides the high pass and optional band filtered signals 371-375 and 381-3S5, respectively. It should be remembered, however, that another set of signals is provided at the input of the frequency band selection unit 40. These are the low pass filtered signals from the last (fifth) stage of the filter sequences in the filter sequence unit 30. Note that the high pass filtered signals 371-375 of FIG. 7, which are also digital signals each with a resolution of 16 bits, are now designated as HIGH1 [0:15], HIGH2 {0:15], 30 ..., and HIGH5 [0; 15] respectively in the embodiment of Fig. 10.

Also note that for clarity in the description of the frequency band selection unit 40, the band filtered signals 381-385 shown in FIG. 7, not 35 are included in FIG. 10. This is permissible because the use of band filters in the filter array of the device 10 is optional. In contrast, low-pass filtered outputs from the last (fifth) stage in the filter 1004164 30 sequence unit 30 with a resolution of 16 bits are provided to this frequency band selection unit 40 with an indication of LOW [0:15].

Specifically, each of the 16 high-pass 5 filtered signal bits HIGH [0:15] is generated by the first stage of filter sequences in the filter sequence unit 30 provided to the corresponding line of the first set of three-state buffers FBBUF1 [0 15], each of the 16 high-pass filtered signals HIGH2 [0:15] generated by the second stage of the filter arrays in the filter array unit is provided to the corresponding line of the second set of three-state buffers. FBBUF5 [0:15], etc. Similarly, each of the 16 low-pass filtered signal bits LOW [0:15] generated by the last (fifth) stage of the filter sequences in the filter sequence unit 30 is fed to the corresponding line in the sixth set of three-state buffers FBBUF6 [0:15].

In FIG. 10, an inverted and expanded version 20 of the filter enable control signal CHB [1: 6] is shown, generated and provided to the buffer control input pins of the six sets of three-state buffers in the array 100. Again, the inversion is necessary since the three-state buffers in the arrangement 100, 25 are shown with active low output enable control inputs.

It is necessary to draw attention to the fact that the output of each of the six sets of three-state buffers FBBUF1 [0:15], FBBUF2 [0:15], FBBUF3 [0:15], FBBUF4 [0: 15], FBBUF5 [0:15] and FBBUF6 [0:15] 30 are connected together in a wiring OR manner. More specifically, the outputs of the three-state buffers FBBUF1 [0], FBBUF2 [0], FBBUF3 [0], FBBUF4 [0], FBBUF5 [0] and FBBUF6 [0] are connected together, the outputs of the buffers with three states FBBUFlfl], FBBUF2 [1], 35 FBBUF3 [1], FBBUF4 [1], FBBUF5 [1] and LOW [1] are connected together etc. A total of 16 lines, each containing five connected outputs, are configured to form the output signal YUIT [0:15] of the frequency band selection 1004164 31 unit 40 with a data width of 16 bits. Again, it is possible to connect these outputs together because the buffers in the array 100 naturally have all three states, and only one of the six sets of buffers in the array 100 is designed to be energized by the control signals CHB [ 1: 6] at some point.

Essentially, when CHB [1] = 0 and CHB [2: 6] = 1, the result obtained at the output YUIT [0:15] of the 10 frequency band selection unit is 40: YUIT [0:15] = HIGH1 [0:15.

Likewise, when CHB [2] = 0, CHB [1] = 1 and CHB [3: 6] = 1, the result obtained at the output YUIT [0:15] of the frequency band selection unit is 40:15 YUIT [0:15] = H00G2 [0:15].

Therefore, the buffer output enable control signals CHB [1: 6] can be used for the hierarchically-characterized and time-multiplex control of the filter arrays by properly assigning the filtered signals to be processed by the operation of the frequency band selection. unit 40. Either the low-pass filtered version of the signal output from the last stage of the filter sequence unit 30 or one of the high-pass filtered signal words HIGH [0:15] -H00G5 [0:15] generated by the corres-25 pondering stage of the filter array unit 30, may be selected and generated as the output of the inventive digital filter array device 10 shown in FIG. 7.

Before proceeding with a description of the details of a hardware configuration of a filter array unit 30, an introduction to the distributed arithmetic algorithm constituting the conceptual basis of another phase of the digital filter device according to the invention should now be provided, to follow.

1004164 32

The main differences between digital high-pass filters (HPF), low-pass flashes (LPF) and band filters (BPF) used as the basic building blocks for the filter block device of the invention are the coefficients and product terms used in the expression of the characteristic equation obtained in expression (5) shown below. Before describing this characteristic equation for digital filters in detail, some 10 variables must be defined.

Assume that the time represented by the variable n is the independent variable for determining a filtered output based on the processing of an input data signal, which is also a function of the time n 15. A total of N base time slots are used for the following analysis. In the expression, {c_} is used to denote a set of digital filter coefficients, where j = 0, 1, 2,. . . , and N-1 is another variable used to count by the coefficients in the analysis, corresponding to the time variables n. When analyzing the filtering operation, since it is assumed that the time n is measured in terms of basic time slot units n = 0, 1, etc. N, Y (n) can be used to display the filtered output signal at the current time. In contrast, {W (n-j)} represents the sequence of pool signals at a previous time (n-j). Therefore, when j = 0, {W (n)} represents a pool signal at the current time.

Based on the above definitions, the filtered output of a digital filter array device, expressed as a function of a time variable, can be given as:

Note that the expression (5) is essentially the same as the expression (4) described above for the IIR digital filter with a direct form II, shown in 1 0 0 4 1 6 4 33 expression of the characteristic equation obtained in expression (5) shown below. Before describing this characteristic equation for digital filters in detail, some 5 variables must be defined.

Assume that the time represented by the variable n is the independent variable for determining a filtered output based on the processing of an input data signal, which is also a function of the time n10. A total of N base time slots are used for the following analysis. In the expression, {c_} is used to denote a set of digital filter coefficients, where j = 0, 1, 2,. . . , and N-1 is another variable used to count by the coefficients in the analysis, corresponding to the time variables. When analyzing the filtering operation, since it is assumed that the time n is measured in terms of basic time slot units n = 0, 1, etc. N, Yin} can be used to display the filtered output signal at the current time. In contrast, {W i n-j}} represents the sequence of pool signals at a previous time (n-j '. Therefore, when j = 0, {W (n)} represents a pool signal at the current time.

Based on the above definitions, the filtered output var, a digital filter array device, expressed as a function of a time variable, can be given as: Y (n) = c0 x W (n) + c, x W (n - 1 ) + c: x W (n - 2) + ... + cs_, x W (n - (Nl)) (5)

Note that the expression (5) is essentially the same as the expression (4) described above for the IIR digital filter with a direct form II, shown in FIG. 4. However, if the pool signal W (n) for the filter device is processed as expression (6) in the binary numeral system below with a total 1004164 34 number of K data bits for each signal, or, in other words, with a resolution of K bits, then: (6) where p | e {0, 1}, p = 0, 1, 2, ..., and K-1 is the 5 variable for counting by all data bits in a multi-bit resolution data signal, and j = 0, 1, 2,. . . , and N-1 /, '1 is the variable for tilting through all time slot units; 10 is the most significant bit (MSB), which is ^ the sign bit; and is the least significant bit (LSB).

When the sequence is used to represent the polar signal W (nl), W (nj), ..., and W (0) in the decimal number system, the value range of {W (nj)} will be between +1 and -1 that is, -1 <{W (nj)} <1, where j = 0, 1, 2,. . ., and N1 and the pole signal W (nj) at the preceding time can then be processed as in the following expression (c): W (»- j) = ((- 1) / ^ / + 2 'hl7 +,., +2, k 'UKjl0 (7) 2 0 When the expression (7) is combined in (5), the expression 95) for Y (n) becomes the filtered output signal at the current time then expression (8): 1004164 35 Y (n) = (-l) (cnhKn - '+ ctf \' + cy; \ '+) + (2') {c hyi ^ cb!;:. J] +. + (ϊκ * ί ic / ... - c h; ^ c: bi: +) + (2 λ "[c h *, h * (./: ... j. (S,

Each of the decimal terms in the above expression (8) is respectively defined as: 0-the-order term: U./V, C] bn, cMn (9) lt -ordeteim: j V /> ,. 4 c, A '. + Γ, Λ; . -. (10) 5 and then, (K-2) -deorder term: ^ nr + c <^> + CA: + -) ,, () I) and (K-1) -deorder term: + ^ ,,: +) ,, - (12)

The 0th order term, represented by expression (9; 10) is obtained by combining the LSB (zero bit, B) of the input signal, the LSB (zero bit, b., B, ...) of the previous input signals, and the coefficients {C-,} Similarly, the pth term is obtained by combining the pth bit (b; j.) of the input signal, the pth bit ( bp, .. 2, bpn_2, ...) of the previous input 1004164 36 signal and the coefficients {c3}, where p = 0.1, and Ki. Therefore, there is a total of K-bits of resolution .

A method according to the invention for operating the digital filter device based on the part arithmetic algorithm as outlined in the above expression (8) can generally be described in the following procedural steps: a. Determine and preset an accumulation term in

10 to a value of 0. The pole input signal W (n) receives K.

bits of signal data in a sequence namely the zero bit, the first bit etc. and the (K-1) -th bit.

b. Solve the value of the 0-th bit sequentially as the input signal and then store the resolved result in the accumulation term. The value of the zero term is determined by the following form: c. Divide the accumulation term by two and save it again as the accumulation term.

20 d. Solve the value of the first term when the first bit is sequentially provided as the input signal, and then store the resolved result in the accumulation term. The value of the first term is determined by the following formula:

It h "" * r / t + c./>j i}.

25 e. Add the value of the first term obtained in step d to the accumulation term to obtain the new accumulation term.

f. Divide the accumulation term by two and save it again as the new accumulation term.

30 g. When the mth sequential input is for the input signal, repeat the above steps until the 1004164 37 value for the mth term is determined, wherein m = 2. .

K-2. The value of the m-th term is determined by the following formula: (εΛ "+ ί · ΛΜι + c, Am- +) '1 o' h. Count the value of the m-th term obtained in step 5 g , on the accumulation term to obtain the new accumulation term.

i. Divide the accumulation term by two and save it again as the new accumulation term.

j. Solve the value of the (KD-th 10th term when the (Kl) -th bit is sequentially provided as the input signal, and then store the resolved result in the accumulation term. The value of the (Kl) -th bit term is determined by the following formula: (c., // 1 -t r.//. '+ c, h "t) · k. Count the value of the (Kl) -th term, obtained in 15 step j in the accumulation term to obtain the new accumulation term.

l. After the last bit ((K-1) -th bit!) Is received, the accumulated value becomes Y (n).

The above illustrates the procedural steps of implementing the calculation of the product term for one sample cycle using the distributed arithmetic algorithm of the invention.

When determining the numerical results of a filtered signal as processed by the digital filter array device of the invention, the above-described procedure steps can be implemented using pre-stored look-up tables to determine the value of the necessary filter characteristic coefficients. When determining the numerical values of the pool signal, all K-bits of the multi-bit 1004164 38

Address (b ^ ..- ,, bpn_i) Area data

(0.0) O

(0.1) cx (1.0) c0 5 (1.1) Cq "1 * Cj

Fig. 8 is a block diagram schematically showing the hardware configuration of a substantial equivalent of the filter array unit 30 contained in the digital filter array device 10 of FIG. 7, which uses a distributed arithmetic algorithm in accordance with a preferred embodiment of the invention. Note that although Fig. 7, in particular, the term filters, whether high-pass, band or low-pass filters as components constituting the filter array unit 30, are shown in the embodiment in FIG. 8 no "filter" functional blocks shown. This is because the outlined functional blocks such as the pole signal processing unit 83, the parallel series conversion and transmission unit 84, and the zero signal processing unit 86 in FIG. 8, as will be described in detail later, are combined to illustrate the functions of these digital filters outlined in FIG. 7, to implement.

Before describing this essential equivalent of the filter array unit 30 of FIG. 7, attention should be drawn to the fact that its use is particularly suitable for the IIR digital filter array device of direct form II, as outlined in the network diagram of FIG. 4. It should also be explained that the distributed arimetic algorithm described in the foregoing is the underlying working concept. As clearly shown in Fig. 8, this essential equivalent of the filter array unit 30 includes eight functional blocks. These blocks are the selectors 81 and 82, a pole signal processing unit 83, a parallel 35 series conversion and transmission unit 84, a shift register 1004164 39 yesterday 85, memories 91 and 92, and a zero signal processing unit 86.

As mentioned in expression (4) above, in the IIR digital filter of FIG. 4, a numeric expression is constructed for the filtered output Y (n), based on an intermediate pole signal W (n) as: m * C '* W, n> + C'X W <"- I) + c "* W (n - 2) + ... + cs" * W (n. (N - 1,). (4)

The pool signal W (n), based on the above expression (3), is obtained from an input data signal X (n) by: II (n) = X (n) + a, x W (n - I) + n: x W (n - 2) + ... + ii \ .t χ W '(n - (Λ - I}). (') 10 Using a simplified designation, 4 'and (3) can be expressed respectively if if (nn (13) and v- (] 4) H (n) = X (n) - * H ("/ '·

Again with reference to FIG. 4 of the drawing, it can be seen that the evaluation of the intermediate pole signal 15 W (n) as described in the above expression (14) is performed using the left part of the network diagram, which is shown as generally distributed in two parts in the center. In the block diagram of FIG. 8, this corresponds to the portion of the total 20 chain that contains everything to the left of the shift register 85.

Therefore, this includes the selector 81, the pole signal processing unit 83, the selector 82, the parallel series conversion and transmission unit 84 and the memory 91. In contrast, evaluation of the output signal Y (n) of the filter series unit becomes (30 of Fig. 7) as described in expression (13) above, performed using the other half of the network scheme to the right of the shift register 85. This includes the zero signal processing unit 86 and the memory 92 Specifically, the memory 91 contains an addressable memory content which can be accessed in the form of a look-up table for the filter characteristic coefficients a ^ a ,, while the memory 92 contains the look-up table for coefficients c0 = cN.j contains.

In a procedure necessary for the calculation processing to obtain the filtering output data based on the distributed arithmetic algorithm, the coefficient look-up table access and the basic summing operation of products can be implemented using the hardware of FIG. 8 in a process that will be described below. With reference to FIG. 11-22, which show embodiments of circuits as well as the corresponding timing diagrams for some of the eight forming components 81-86 and 91-92 of FIG. 8, the process of numerically obtaining the filter output can be outlined as follows.

A. Begin the summation of products procedure by storing an initial product term in an accumulator. This can be done, for example, by storing an initial value for the product term a..W (n-j) in expression (14) in a stair register set 833 of the pole signal processing unit 83 shown in FIG. 15.

b. Control the filter string to have the input signal processed and provided to the pool signal processor. This can be done, for example, by the control signal CTRL-1 shown in Fig. 8 to a first selector 81 so that the input data signal XIN (SEL1) can be selected by the selector 81 and provided to the associated pole signal processing unit 83.

c. A pool signal processor adds the input 35 signal to a product term held in the accumulator to obtain a pool signal. This can be done, for example, by adding the pole signal processing unit 83, the XIN (SEL1) data signal 1004164 41 to the value a ^ .W ^. ^, In the stage register set 833 of the pole signal processing unit 83 of FIG. 15, thereby obtaining a pole signal POOL or else the intermediate pole signal W (n).

5 d. A pool signal processing unit sends its processing signal to a parallel series conversion and transmission unit and to a second selector. This can be done, for example, by the register 831 in the pole signal processing unit 83 of FIG. 15 which sends the pole-10 signal POOL obtained in step c to the parallel series conversion and transmission unit 84 for the parallel series conversion and then an outside transfer as well as the second selector 82 for the self-selected feedback.

15 e. A parallel series conversion and transmission unit converts the processed data signal into a sequence of serial bits and sends it to a shift register. This can be done, for example, by the parallel series conversion and transmission unit 84 shown in FIG. 17 and transmitting the converted bits of the pool signal POOL, or W (n) held in the register 842 in a form of multiple resolution bits; such as 16 bits in the above example) in a serial sequence to the shift register 85 of FIG. 8. 25 The transfer can be in an order from LSB to MSB or vice versa.

f. A shift register addresses a memory location in a first and second memory means upon receipt of each of the corresponding bits of the zero order term of the data signal which has been processed, converted and transmitted by the parallel series conversion and transfer unit. This can be done, for example, by the shift register 85 upon receipt of each of the W (n) data bits (bcn, bV :, bh,;, ...) of the 0th order term transmitted by the parallel series conversion and transmission unit 84, which addresses one memory location in the indicated address space of the memories 91 and 92 corresponding to the received data bits.

1 0 0 4 1 6 4 42 g. A first and a second memory means retrieve the respective memory contents held in the memory locations corresponding to those addressed by the shift register. This can be done, for example, by the memories 91 and 92 which retrieve their respective memory contents MEM1 and MEM2 which are held in the memory locations corresponding to those addressed by the shift register 85 upon receipt of W (n) data bits (bcn, b ° n_i, b ° n_2, ...) of the zero 10 order term.

h. Have the 0th order term data held by the first memory retrieved and stored therein to the toll signal processor. This can be done, for example, by outputting a control signal CTRL-2 to a second selector 82, so that the 0 th order memory content MEM1 (SEL2) held in a memory 91 can be selected by the selector 82 and retrieved to the register 833 of the pole signal processing unit 83 of FIG. 15.

20 i. The second memory device retrieves its addressed zero order term memory content to a zero signal processing unit. This can be done, for example, by the memory 92 which retrieves the zero order term memory content MEK2 and sends the content to a register 861 and then to the stage register set 863 of the zero signal processing unit 86 shown in FIG. 21.

j. A shift register sends a first order term of the pool signal data received from the parallel series conversion and transmission unit to both the first and second memory devices. This can be performed, for example, by the shift register 85 which is the direct and non-reprocessed first order term pool signal data W (n) with data bits (bh, b: nl, b1, ..-, ...) as received from the parallel series conversion and transmission unit 84 35 to the memories 91 and 92.

k. A first and second memory means fetch the addressed first order term memory contents, respectively. This can be performed, for example, by the memory 1004164 43 gene 91 which retrieves the addressed first order memory content NIEM1 and the memory 92 which retrieves the addressed first order memory content MEM 2, both addressed by the first order pool signal data W (n) having data bits 5 (b1 ,,, b: nl, b1n.2,...).

l. Have the first order term data held by the first memory retrieved to the pool signal processing unit. This can be done, for example, by outputting a control signal CTRL-1) to the first selector 81 so that the first order term memory content MEM1, which is held in the memory 91, can be selected by the selector 81 and retrieved to the pool signal processor. 83.

m. A pool signal processing unit divides the zero 15 order term data held in step h an appropriate number of times and adds it to the first order term data to obtain the new pool signal. This can be performed, for example, by the pole signal processor 83 which divides the zero order term data held in step h two times and adds this to the first order term data MEM1 to obtain the new pool signal POOL and positions it in the register 831 of the pole signal processor 83 shown in Fig. 15.

n. A pool signal processing unit fetches the new pool signal obtained in step m only to the second selector. This can be done, for example, by the pool signal processing unit 83 which retrieves the new pool signal POOL obtained in step m only to the second selector 82 and not to the parallel series conversion and transmission unit 84, so that the pool signal W ( (n) that it is retained therein, not refreshed.

o. A second memory device retrieves the first order term data to the zero signal processing unit, which adds it to the zero order term data which has been divided a designated number of times. This can be performed, for example, by the memory 92 which retrieves the first order term data MEM2 to the zero signal processing unit 86 shown in 1004164 44

Fig. 21, which adds the zero order term data coupled by the register 863 in step i that is divided twice to the first order term data MEM2 and holds the added result in the register 861 of the zero signal-5 processor 86.

p. A zero signal processing unit repeats this to complete and generate the filtered signal data. This can be generated, for example, by repeatedly fully processing all the bits that form the pool signal data 10 W (n) generated by the stair register set 863 of the zero signal processing unit 86 as the filtered signal Y (n).

q. A pool signal processing unit generates a sum of products for a zero signal processing unit to generate it as the filtered output of the device and returns to step a until all order terms are complete. This can be done, for example, by the pole signal processing unit 83 which accumulates the a.W (n + 1-j) terms in its stage register set 833 and the stage set 863 of the zero signal processing unit 86 generates the filtered signal Y (n) from the device. Then, the procedure returns to step a until all order terms are completed.

The above description generally depicts a process implementing a digital signal failure in a digital filter array device as shown in FIG. 7. The filter array unit 30 in FIG. 7 shown in FIG. 8 is detailed, includes several components which, while each may contain electronic functional elements known in the art, are combined to unambiguously achieve the functionality useful for the digital signal processing of the invention. These components known to those skilled in the art will not be described in further detail, but some components that are unique will require some further discussion with reference to FIG. 11-22 of the drawing.

Fig. 11 is a schematic diagram of a selector 81 for the digital filter array unit 30 of FIG. 8 in accordance with a preferred embodiment of the invention, while FIG. 12 shows a work rule diagram thereof. As shown in Fig. 11, showing a selector suitable for processing a digital input signal with the resolution of 16 bits, the selector 81 generally comprises two sets of a number of buffers with three states XBUF [0:15] and M1BUF [0:15]. Each of the first set of 16 buffers with three states XBUF [0:15] captures the corresponding data signal bit of the 16 bit input digital signal XIN [0:15]. Likewise, each of the second set of 16 three-state buffers M1BUF [0:15] receives the corresponding signal bits from the 16 bit feedback signal MEM1 [0:15],

The corresponding outputs of the three-state buffers in the two sets of XBUF [0:15] and MlBUF [0:15] are bound together resulting in a total of the 16 output signal bits SEL1 [0:15] that the selector output SEL1 of Fig. 8. The buffer output enable controls of the first set of three-state buffers XBUF [0:15] are connected together and directly connected to the signal CTRL-1. The line is directly connected to the release controllers of the first set of XBUF [0:15], while the release controllers of the second set of MlBUF [0:15] are controlled by an inverted version of the CTRL-1 signal, as shown in the drawing by the presence of the inverter 811, which inverts the CTRL-1 signal before controlling the three-state buffers. Therefore, the selector 81 of FIG. 11 capable of selecting either the input signal XIN [0:15] or the feedback signal MEM [0:15] under the control of the signal CTRL-1. The selection of either is based on the time sequence sequence shown in FIG. 12. In a signal processing example involving a data resolution of K bits, the selection scheme can be implemented in processing time slots, which are divided into K units 0, 1, ..., and K-i, as shown in FIG. 12. The timing diagram of Fig. 12 therefore only gives the scheme for 1004164 46 selecting the XIN signal in the time slot O for the LSB of the processed data.

For the other selector 82 of the digital filter array 30 of FIG. 8, shows the schematic diagram of FIG. 13 a design implementation thereof. Fig. 14 shows the work rule diagram of the Fgi selector. 13. The embodiment of the selector 82 of FIG. 13 is in hardware circuit configuration similar to that of the selector 81 shown in FIG. 11, except that the three-state buffer set 10 MBFU [0:15] selects the multi-bit coupling signal MEM1 [0:15], while PBUF [0-15] selects the multi-bit pool signal POOL [0:15]. Either the feedback signal MEM1 or the pole signal POOL is selected by the control signal CTRL-2 as the selected output signal SEL2 from the selector 82. The buffer set MBUF; 0: 15] is directly connected to CTRL-2 to MEM1 [0 : 15] to select when CTRL-2 makes its impact. An inverter 821 is similarly used to obtain an inverted version of the CTRL-20 signal for the TBUF [0:15] selection control to select POOL [0:15].

Fig. 15 is a schematic diagram of the pole signal processing unit 83 of FIG. 8, in accordance with a preferred embodiment of the invention. As the drawing shows, the pool signal processing unit 83 generally includes a register arrangement 831, an adder arrangement 832, a set of stair register arrangements 833, and a support logic in the form of an AND-OR gate arrangement 837. Again, since the pool signal processing 30 operation unit 83 is a component of the digital filter array unit 30, the example shown in FIG. 15, that digital signal data is processed with a resolution of 16 bits. This is expressed in the drawing by designations such as LOCKO [0:15], ADD [0:15], LOCK-35 SHARE1 [0:15], ..., LOCK5 [0:15], and MUX1 [0:15 ], ...

and MUX5 [0:15] for the components.

In general, with reference to FIG. 8, the described pole signal processor 83 1004164 47 receives two input signals SEL1 and SEL2 for processing and generating the output pole signal POOL. The detailed logic of FIG. 15, however, shows that further control signals are also involved in the processing. Specifically, these LB [1] -LB [5], respectively, which are the inverted version of the stage status control signals L [1] -L [5], comprise the stage register signals CL [1] -Cl [5] for the first to fifth stages of the set of five stage registers latching 1-5 of the arrangement 833 as well as the conditioning signal SEL3 for the AND-OR gates MUX1-5 of the arrangement 837, which decides whether or not to split the input SEL2 M-fold or divided by two in the described embodiment. Essentially, the first data signal SEL1 [0:15] with a 16-bit resolution and which is provided to the pole signal processing unit 83 forms the B input of the adder ADD of the adder array 832, while the second data signal SEL2 [0: 15] the data input is to each of the set of stair register arrangements 833.

In operation, the second data signal SEL2 [0:15] is first locked to the selected register of the stair registers LOCK-5 to the arrangement 833 by the activated signal of the latch control signals CL [1] -CL [5]. The selection is made from one of the five stages of the illustrated embodiment. The inverted stage status control signals L [1] and L [5] then select one register in the arrangement 833 for transfer to the corresponding AND-OR gate arrangement 837. The selected gate in the arrangement 837 retrieves the selected register content under conditioning 30 of the signal SEL3. the arrangement 833 to the A gate of the adder 832. The unit 83 is driven by a clock signal CK which is immediately retransmitted to the data load control signal of the register 831, which receives the output of the adder arrangement 832 and the POOL. the output of the pole signal processor 83 at its Q port. In the example of FIG. 15, the adder arrangement 832 also includes in-feed and out-feed CIN and CO [0:14], respectively. Fig. 16 shows the operational time recording scheme of the pole signal processing unit 83 of FIG. 15.

Fig. 17 is a schematic diagram of the parallel 5 series conversion and transmission unit 84 of FIG. 8 according to a preferred embodiment of the invention, and FIG. 18 is the corresponding timing scheme. This is a parallel series conversion unit which includes a cascaded array 841 of flip-flop type registers FD [0:14]. An arrangement 842 of registers LAT0 [0:15] for locking the 16 bits of processed data, namely the pool data POOL [0:15] as generated by the pole signal processing unit 83, is controlled by a signal HALF holding the data for one time slot unit 15 and generates an output referred to as bits BIT [0:15]. A control signal LOAD provides data input control for each of registers FD [0:14] in array 841 after each of the corresponding bits BIT [0:15] received from registers 842 is conditioned by the Q output of the preceding stage through a corresponding gate of the OF -OR gates, GMUXO-15 in the arrangement 843, as well as through the corresponding bits of BIT [0:15]. This circuit arrangement allows the data BIT [0.-15] to be loaded into the flip-flop type registers 2 5 FD [0:14], when the LOAD signal becomes logic low (i.e. LOAD = 0) and the clock CK signal changes state. As shown in Fig. 18, the operation of the parallel series conversion and transmission unit 84 of FIG. 8 allows the parallel-series conversion of the 30 parallel 16 bit POOL [0:15] signal into the desired serial signal SERIAL.

Fig. 19 is a schematic diagram of the shift register 85 of FIG. 8 according to a preferred embodiment of the invention. As shown in Fig. 8, the shift register 85 receives and holds the serial data, as provided by the parallel series conversion and transmission unit 84, in a clocked sequence. SHIF [1] -SHIF [5] are used to clock the sequential shift of the 1004164 49 incoming data bits in the five stages. The inverted versions of the stage status control signals L [1] -L [5] namely LB [1] -LB [5] are used to individually select the source of the five stages every 5 address signal bits ADDR [1] -ADDR [3 ] as described by way of example in the logic of the drawing, based on the control sequence of FIG. 20. The constructed address signal bits ADDR [1: 3] are then provided to the memory devices 91 and 92 (FIG. 8) to access the coefficient data stored in the appropriate format in the look-up table held therein. These memory devices can be, for example, conventional ROMs, PALs or any other suitable semiconductor memory device.

FIG. 21 is a schematic diagram of the zero signal processing unit 86 of FIG. 8 according to a preferred embodiment of the invention. As shown in the drawing, the zero signal processing unit 86 includes a register arrangement 861, an adder arrangement 862, a set of 20 stair register arrangements 863, and support logic in the form of ΕΝ -OR gate arrangement 867. Since the zero signal processing unit 86 is still a main component of the digital filter array unit 30, shows the example shown in FIG. 21, again digital signal data with a resolution of 16 bits. This is indicated in the drawing by designations such as LOCK [0:15], ADD [0:15], LOCK [0:15], ..., LOCK [0:15], and MUX1 [0:15],. .., and MUX5 [0:15] for the components.

Referring again to FIG. 8, the described zero signal processing unit 86 forms the input signal MEM2 for processing generating the output signal, which in this case is the final output of the filtered signal for the digital filter sequence unit 30, indicated as signal 371-375 of FIG. 7, or as H00G1 [0:15], ..., HIGH5 [0:15] in the description of the frequency band selection unit 40, shown in FIG. 10. The detailed logic of FIG. 21 shows, however, that further control signals are also involved in the processing. These 1004164 50 specifically include LB [1] -LB [5], the inverted version of the staircase status control signals L [1] -L [5], respectively, the staircase register control signals CL [1] -CL [5] for the first to fifth stage of the set of five 5 stage registers LOCK1-5 of the arrangement 863, as well as the conditioning signal SEL3 for the AND-OR gates MUX1-5 of the arrangement 867, which determines whether or not the input MEM2 is M-divided , or divided by 2 in the described embodiment.

Essentially, the data signal MEM-2 [0:15] with a 16-bit resolution, which is provided to the zero signal processing unit 86, is the B input of the adder ADD of the adder arrangement 862.

In operation, each bit of the data signal MEM2 [0:15] is again sent to the B port of the adder array 862, while its A port is supplied with the feedback version of the data held in the selected register of the five stair registers LOCK1-5 of the arrangement 863. The selection 20 of each of the five stages is determined by the status of the lock control signals CL [1] -CL [5], The inverted staircase status signals L [1] -L [5] selects then one register in the arrangement 863 for transmission to its corresponding OF -OR gate in the arrangement 86Ά The selected gate in the arrangement 867 gets, under the condition of the signal SEL3, the choice. register contents in the arrangement 863 to the A gate of the adder in the arrangement 862. As in the case when the pole signal processing unit 83 was described with reference to FIG. 15, the zero signal processing unit 86 is driven by a clock signal CK which is directly retransmitted to the data load control signal of the register 861, which receives the output of the adder arrangement 862, and at the Q gate the signal 35 ZERO [0:15 ] causes the output of the zero signal processing unit to become 86. In the described example of the operation of FIG. 21, the adder arrangement 862 also uses the inward and outward 1004164 51 CIN and CO [0:14] respectively. Fig. 22 shows the operation control diagram of the zero signal processing unit 86 of FIG. 21.

While the invention has been described by way of example and in terms of preferred embodiments, it will be apparent to those skilled in the art that the invention is not limited to the embodiments shown. For example, the digital filter array arrangement is not limited to a depth of five steps, and the data signal is not limited to a 16-bit resolution. The invention is therefore intended to include various modifications and similar arrangements. The scope of the claims is therefore subject to the broadest interpretation and therefore includes all such modifications and similar structures.

1 0 0 4 1 6 4

Claims (33)

1. Digital signal filter array device for filtering an external input signal to generate a filtered digital output signal, the device comprising: input signal selectors for selecting between the external input signal and a pre-low pass filtered feedback signal to provide a filter input signal; Filter stretchers for receiving the filter input signal and filtering the filter input signal to generate a high-pass filtered signal and a low-pass filtered signal, the low-pass filtered signal a low-pass filtered output signal and a low-pass filtered feedback signal; and frequency range selecters responsive to the high-pass filtered signal for generating the filtered digital output signal; Wherein the filter array members comprise means for applying a distributed arithmetic algorithm to the filter input signal to generate first and second summations of product terms representing the high-pass filtered signal and the low-pass filtered signal, respectively, and wherein the filter array members further low-pass filter means includes for generating the low-pass filtered feedback signal using a decimated sample rate. The digital signal filter array device of claim 1, wherein the filter array members comprise a plurality of filter members organized as one array of filter members, the plurality of filter members generating a plurality of filtered outputs with a plurality of frequency bands, and each of the plurality of frequency bands 1004164 at most another of the number of frequency bands slightly overlaps. The digital signal filter array device of claim 1, wherein the filter array members comprise a plurality of filter members organized as a plurality of array of filter members, the plurality of filter members generating a plurality of filtered outputs with a plurality of frequency bands, and each of the plurality of frequency bands another from the number of frequency bands at most 10 overlaps slightly. The digital signal filter array device of claim 2, wherein the plurality of filter means includes a high-pass filter means for generating the high-pass filtered signal and low-pass filter means 15 for generating the low-pass filtered signal. The digital signal filter array device of claim 2, wherein the plurality of filter means includes high-pass filter means for generating the high-pass filtered signal, low-pass filter means for generating the low-pass filtered signal, and a plurality of band filter means for generating a number of band-filtered signals, and the frequency-range selector further provides a response to the number of band-filtered signals to generate the filtered digital output signal. The digital signal filter array device of claim 1, further comprising analog-to-digital converters for converting the external input signal into a digital format for processing by the input signal selector. The digital signal filter array device of claim 4, wherein the high-pass filter members and the low-pass filter members simultaneously receive the filter input signal. The digital signal filter array device of claim 5, wherein the high-pass filter members, the low-pass filter members and the plurality of band filter members simultaneously receive the filter input signal. 10 0 4 1b *. The digital signal filter array device of claim 1, wherein the input signal selector means comprises first and second arrays of three-state buffer means having respective first and second output lines, the first and second output lines being connected to form a selector output line to carry the filter input signal, the The first arrangement of the three-state buffer members comprises a first input for receiving the external input signal, the second arrangement of the three-state buffer members comprising a second input for receiving the low-pass filtered feedback signal, and wherein the first and second arrangements of the three-state buffer members include an output enable input to control selection between the external input signal and the low pass filtered feedback signal to provide the filter input signal. The digital signal filter array device of claim 1, wherein the low-pass filtered feedback signal consists of a plurality of feedback signals, the input signal selector means including a first number of arrangements of three-state buffer means having a first number of output lines, the first number of arrangements comprising: a first arrangement of three-state buffer members with a corresponding first output line, and a second plurality of arrangements of three-state buffer members with a respective second number of output lines, the first number of output lines being connected together to form a selector output to carry the filter input signal wherein the first array of three-state buffer means includes a first input for receiving the external input signal, 1004164 wherein the second plurality of arrangements each includes a second input for receiving a correspond honored signal of the number of feedback signals, and wherein the first number of arrangements of three-state buffer means comprises an output enable input to control the selection between the external input signal and the number of feedback signals to provide the filter input signal. The digital signal filter array device of claim 1, wherein the frequency band selectors comprise first and second arrays of three-state buffer members having respective first and second output lines, the first and second output lines being connected to form a device output to carry the device output signal. wherein the first arrangement of three-state buffer members comprises a first input to receive the high-pass filtered signal, wherein the second arrangement of three-state buffer members comprises a second interval for receiving the low-pass filtered signal, and wherein the first and second arrays of three-state buffer organs include respective first and second output enable inputs to independently control the respective selection of the high-pass filtered signal and the low-pass filtered signal for transfer to the device u itgang. The digital filter array device of claim 30 11, wherein the low-pass filtered output signal is a signal of a sequence of low-pass filtered feedback signals and the low-pass filtered signal received by the second arrangement of the three-state buffer members a final low-pass 35 filtered feedback signal is in the sequence of low-pass filtered feedback signals. The digital signal filter array device of claim 5, 1004164 wherein the frequency band selector comprises a first plurality of arrangements of three-state buffer members having a plurality of output lines, the first plurality of arrangements of three-state buffer members comprising: a first array of three-state buffer members, a second array of three-state buffer members, and a second plurality of array of three-state buffer members, the plurality of output lines being connected to form a device output to carry the device output signal, the first arrangement of three-state buffer members a first input for receiving the high-pass filtered signal, the second arrangement of three-state buffer means comprising a second input for receiving the low-pass filtered signal, the second number of arrangements of three-state buffer members each includes a third input for receiving a corresponding signal from the plurality of band-filtered signals, and the first number of arrangements of three-state buffer members comprises a plurality of respective output enable inputs to independently to control the respective selection of the high-pass filtered signal, the low-pass filtered signal and a plurality of band-filtered signals for transmission at the output of the device. The digital signal filter array device of claim 13, wherein the low-pass filtered output signal is a signal of a sequence of low-pass filtered feedback signals and the low-pass filtered signal received by the second array of three-state buffer means and a final 1 0 0 4 1 6 4 low-pass filtered feedback signal is in the sequence of low-pass filtered feedback signals. The digital signal filter array device of claim 2, wherein each of the filter means includes first and second signal selectors, pool signal processors, parallel series conversion means, shift register means, first and second memory means, and zero signal processing means, the first signal selector comprising first input for receiving the filter input signal, a second input for receiving a first memory data output from the first memory device, and an output for selectively transferring the first memory data output as a first selected signal, and the pool signal processor a includes a first input for receiving the first selected signal and a second input for receiving a second selected output from the second signal selector, the pole signal processor generating a pole signal for inclusion in the summations of the product terms and the distributed arithmetic algorithm; the second signal selector has a first input for receiving the pool signal, a second input for receiving the first memory data output, and output for transferring the selected first memory data output as a second selected signal, the parallel series converter an input has 30 for receiving a pool signal, wherein the parallel-series converter converts the pool signal from a parallel format into a serial format comprising a number of data bits, the shift register has an input for receiving the pool signal in serial format and includes means for constructing first and second memory addresses using data bits of the serial format pool signal; 1004164 the first memory means includes first addressing means for retrieving first digital filter characteristic coefficient data stored in the shift register and for storing the retrieved first digital filter characteristic coefficient data as first memory data, the second memory means contains second addressing means for retrieving second digital filter characteristic coefficient data stored in the shift -10 register and for storing the retrieved second digital filter characteristic coefficient data as second memory data, and the zero signal processor includes an input for receiving the second memory data, means for processing the second memory data as summations of product terms according to the distributed arithmetic algorithm, and means for transferring the processed second memory data as the high pass filtered signal and the low pass filtered rd signal. 16. The digital signal filter array device of claim 15, wherein the zero signal processing means includes means for transmitting the processed second memory data as the high pass filtered signal, the low pass filtered signal and a tape filtered sig-2. The digital filter array device of claim 16, wherein the first signal selector comprises first and second arrays of three-state buffer members with respective first and second output lines, the first and second output lines being connected to form a first selection, and wherein the first and second second arrangements of the three state buffer members comprising respective first and second output enable inputs to independently control the provision of the first selected signal to the first selection output. The digital filter array device of claim 16, wherein the second signal selector comprises first and second arrangements of three-state buffer members with respective first and second output lines, the first and second output lines being connected to form a second selection output , and wherein the first and second arrangements of the three-state buffer members include respective first and second output enable inputs to independently control the provision of the second selected signal to the second selection output. The digital filter array device of claim 16, wherein the pool signal processor comprises an array of registers, an array of adders, an array of trap register arrays and an array of OF-OR logic gates, the array of trap register arrays for receiving the second selected signal and for locking the second selected signal for transmission to the arrangement of OF-OR logic gates, er. The arrangement of OF -OR logic gates includes means for receiving the locked second selected signal, means for conditioning the locked second selected signal, and means for transferring the conditioned second selected signal to the arrangement of adders, and the arrangement of adders comprises means for receiving the conditioned second selected signal, means for receiving the first selected signal, and means for adding the conditioned second selected signal and the first selected signal to a selected signal sum to generate for transfer to the arrangement of registers, and the arrangement of registers includes means for receiving the selected signal sum and for locking the selected signal sum as the pool signal according to a clock signal. 1 0 0 4 1 6 4 The digital filter array device of claim 16, wherein the first memory means is a permanent memory. The digital filter array device of claim 5 16, wherein the second memory means is a permanent memory. The digital filter array device of claim 16, wherein the first memory means is a memory device with programmable logic blocks. The digital filter array device of claim 16, wherein the second memory means is a memory device with programmable logic building blocks. The digital filter array device of claim 15, wherein the zero signal processing means comprises an array of registers, an array of adders, a set of stair register arrangements, and an array of OF-OR logic gates, the array of ΕΝ-OR logic gates including means for receiving of a register output from the set of stage register arrangements, means for conditioning the register output to produce a conditioned pool signal, and means for providing the conditioned pool signal to the arrangement of adders, the arrangement of adders comprising means for receiving the conditioned pool signal and the second memory data, means for adding the conditioned pool signal and the second memory data to produce a summing, and means for providing the summing to the arrangement of registers, wherein the arrangement of r egisters includes means for receiving and locking the summation and means for providing a summing to the set of stair register arrangements according to a clock signal and the set of stair register arrangements comprising means for receiving the locked sum and means for providing the locks summation 100416 «to the frequency range selector as the high-pass filtered signal and the low-pass filtered signal. The digital filter array device of claim 24, wherein the zero signal processing means further comprises means 5 for providing the locked summing to the frequency range selector as a band-filtered signal. 26. A method of operating a digital filter sequence device for filtering an external input signal and generating a filtered digital output signal, comprising the steps of: a. Selecting between the external input signal and a low-pass feedback signal about a filter input to select; 15 b. filtering the filter input as a first summation of product terms according to a distributed arithmetic algorithm, to produce a high-pass filtered signal; c. filtering the filter input as a second summation of product terms according to the distributed arithmetic algorithm and at a decimated sample rate, to produce a low-pass filtered signal, d. performing a subsequent selection of the filter input as in step a, using the low-pass filtered signal as the low-pass feedback signal; and e. transmitting the high pass filtered signal as the filtered digital output signal. The method of claim 26, 30 wherein steps b and c are performed by a filter array comprising a plurality of filters organized as a single array of filters, the plurality of filters generating a plurality of filtered outputs with a number of frequency bands, and each of the plurality of frequency bands overlapping slightly differently from the plurality of frequency bands at most. 28. The method of claim 26, 1 0 0 4 1 6 4 wherein steps b and c are performed by a filter sequence comprising a plurality of filters organized as a plurality of filter sequences, the plurality of filters generating a plurality of filtered outputs with a 5 number of frequency bands, and wherein each of the number of frequency bands overlaps slightly different from the number of frequency bands at the most. 29. The method of claim 27, wherein the plurality of filters comprise at least a high-pass filter for generating the high-pass filtered signal and a low-pass filter for generating the low-pass filtered signal. A method according to 27, 15 wherein the plurality of filters comprises at least one high-pass filter for generating the high-pass filtered signal, a low-pass filter for generating the low-pass filtered signal and a plurality of band filters for generating a respective number of 20 band-filtered signals, and further selecting between the high-pass filtered signal and the band-filtered signal to select the filtered digital output signal. The method of claim 29, wherein steps 25 b and c are performed simultaneously. The method of claim 30, wherein the filter input is filtered as a third summation of product terms according to a distributed arimetic algorithm to generate a band-filtered signal, and wherein steps b and c and filtering the filter input are third summation of products terms are all executed simultaneously. 33. A method of operating a digital filter array for filtering an external input signal to produce a filtered digital output signal, comprising the following steps: a. Storing an initial product term; 1004164 b. providing the external input signal to a pole unit; c. adding the external input signal to the initial product term to obtain a polar signal, d. converting the pool signal into a sequence of serial bits to provide a serialized pool signal, e. addressing a first zero-term memory location bits of the serialized pool signal; f. addressing a second memory location according to the zero-order term bits of the serialized pool signal; g. providing zero order term data corresponding to the first memory location to the pool unit, h. providing zero order term data corresponding to the second memory location to a zero unit; i. addressing a first memory location according to first order term bits of the serialized pool signal; j. addressing a second memory location according to the first order term bits of the serialized pool signal; k. providing the first order term data corresponding to the first memory location to the pool unit; l. dividing the zero order term data provided to the pool unit a given number of times to obtain a division result and adding the division result 30 to the first order term data provided to the pool unit, to obtain a new pool signal, m providing the first order term data corresponding to the second memory location to the zero unit; N. dividing the zero order term data provided to the zero unit a number of times to obtain a division result and adding the division order result with the first order term data provided to the zero unit to obtain filtered signal data to gain; o. adding the new pool signal to the filtered signal data; and 5 p. repeating steps a through n to N-1 order terms are generated and added, N being a predetermined number. 1004164